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References: <20220823033414.198525-1-seanga2@gmail.com>
Subject: Re: [RESEND PATCH] clk: ls1c: Fix PLL rate calculation
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Yang Ling <gnaygnil@gmail.com>, linux-kernel@vger.kernel.org,
        Kelvin Cheung <keguang.zhang@gmail.com>,
        Stephen Boyd <sboyd@codeaurora.org>,
        Du Huanpeng <dhu@hodcarrier.org>,
        Sean Anderson <seanga2@gmail.com>
To:     Sean Anderson <seanga2@gmail.com>, linux-clk@vger.kernel.org,
        linux-mips@vger.kernel.org
Date:   Mon, 17 Oct 2022 14:09:47 -0700
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Quoting Sean Anderson (2022-08-22 20:34:14)
> While reviewing Dhu's patch adding ls1c300 clock support to U-Boot [1], I
> noticed the following calculation, which is copied from
> drivers/clk/loongson1/clk-loongson1c.c:
>=20

Nobody has provided a review for this patch. If it is still important,
please resend. Thanks.