From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC7E0C4332F for ; Wed, 19 Oct 2022 11:20:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232347AbiJSLUE (ORCPT ); Wed, 19 Oct 2022 07:20:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231620AbiJSLSt (ORCPT ); Wed, 19 Oct 2022 07:18:49 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3D69191D56 for ; Wed, 19 Oct 2022 03:48:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666176513; x=1697712513; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1YbzoiUXSvQWzBUraiDzjfmE9NvY0qFctz1F+7sN7Sw=; b=UQuPoghWFZHvCq7rzMzBdsvgJG+u1opDMS3CXDOCPmEShpBunNYiSFyj 7Q48EspvwLnwn0Q5KOwWjnpY+IULtMJA1kngX0xA0M7K0ZtYbMqEJqSxF HE+C24Vv3BumQlP2vMJ7ivjAa9O+rAZLnwMHx4GJkin45qq5E1WrFV+Q1 cJFmfa7P5kj7KD/FzhHiP1IetWL2BqLQ44Ye4mEnL78GApKse5rgKZHtP 0badRB2FDaLCK7DwCcbNv+Z11RnUslYijwjzGjXTASbnN9vtVt76Lylbv kX11OF51IbybZojZidZfy4bIt5+YTy95B7YKw6EGrGf0tvuXXBMrLFgXw g==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="293770257" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="293770257" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 03:46:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="804242250" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="804242250" Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga005.jf.intel.com with ESMTP; 19 Oct 2022 03:46:21 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 3/5] x86/gsseg: make asm_load_gs_index() take an u16 Date: Wed, 19 Oct 2022 03:23:08 -0700 Message-Id: <20221019102310.1543-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019102310.1543-1-xin3.li@intel.com> References: <20221019102310.1543-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "H. Peter Anvin (Intel)" Let gcc know that only the low 16 bits of load_gs_index() argument actually matter. It might allow it to create slightly better code. However, do not propagate this into the prototypes of functions that end up being paravirtualized, to avoid unnecessary changes. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 2 +- arch/x86/include/asm/special_insns.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 9953d966d124..e0c48998d2fb 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -779,7 +779,7 @@ _ASM_NOKPROBE(common_interrupt_return) /* * Reload gs selector with exception handling - * edi: new selector + * di: new selector * * Is in entry.text as it shouldn't be instrumented. */ diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index 35f709f619fb..a71d0e8d4684 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,7 +120,7 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } -extern asmlinkage void asm_load_gs_index(unsigned int selector); +extern asmlinkage void asm_load_gs_index(u16 selector); static inline void native_load_gs_index(unsigned int selector) { -- 2.34.1