From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23B9CC4332F for ; Thu, 20 Oct 2022 07:59:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231185AbiJTH7P (ORCPT ); Thu, 20 Oct 2022 03:59:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231168AbiJTH7C (ORCPT ); Thu, 20 Oct 2022 03:59:02 -0400 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E71D18027C for ; Thu, 20 Oct 2022 00:59:00 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id 128so18536450pga.1 for ; Thu, 20 Oct 2022 00:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pAsIYw7sZ9pedrVTYHgIfzcW6BaLpjWwdgXvgEmQOaY=; b=KVCqQo/Qymbi41s1GUvHpj3Wa5ZypO8gqStPS/9xn5zgaSL7zarcIcxDhnsDA/Iv6H xDxS2Ox3UAG1mZR376x/ShdVFwZWb1o8wEai1lgskVK8Y2IGL9/Ulx0HVzk8RtyhbKhm QP/grnXg+4nuN2+5lplMkJjPRv6pcSnWZCLkH/y8xE86Y4JaQp9Cijci1o5tTkUDzGPj rZU62/JDjfV98OLvz/x0lhSpy3gj5m3JOcNChEIHA6cpCS4LSCXSz7KKmPPpcsPMgEdl JOAGQSC4At6e1OBUJ0L17wsET+PnN4fPY/XJvBo81AgTiL+SNJb5OfHwaMExuIQ2rZ+/ 2AzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pAsIYw7sZ9pedrVTYHgIfzcW6BaLpjWwdgXvgEmQOaY=; b=7+74mbtNyuRoyBJcpNfNmc6UQCE5DK3vCKfOMYxKvwar5RbwfceQAILkbX1ve+oIzP 6tEwViBTeiCJdv5QS/HkpsL4wB/0SyZbfux0frhMs10/CDa7UIKxTcWURgFbEBrwKdjr Akb3QwyOaIkaDathZ4N7U+23o9LCGWO7pIYjEuCzQga8rpln9N1mTMuT+G35zlH+Zgkv ddn2RZG/6qS7ENl9+LNpEWcfyimv0bDc/PrAZOWda2HL59Bg3dP5FkJkL0NBwFdV9jFH aoKgM+nQx2T8EmBPkMLet7IV6S3Y8Dt4/4UUWrp64HeUoJoSHrlucr5oHPqM1GiihLUF OyVQ== X-Gm-Message-State: ACrzQf2aD3VWOpBTmegn2jb0xd+xBg1Ld5tCyTsurBLkSgN/hpbpc9pn aro/kD5Senl8NYSTpY0CfC1F3w== X-Google-Smtp-Source: AMsMyM7UCFvQaa7jwg80SjAqa1N1TyrjSWdPX8DKXF4Z/drUnTh21rNLOzM1OFg/9Bs2UjVCRigQtQ== X-Received: by 2002:a63:cf4f:0:b0:462:da7a:1ded with SMTP id b15-20020a63cf4f000000b00462da7a1dedmr10543458pgj.605.1666252739916; Thu, 20 Oct 2022 00:58:59 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.80.23]) by smtp.gmail.com with ESMTPSA id h30-20020aa79f5e000000b0052dfe83e19csm13206438pfr.16.2022.10.20.00.58.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 00:58:59 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Arnd Bergmann , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Jones , kernel test robot , Anup Patel , Conor Dooley Subject: [PATCH v5 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM Date: Thu, 20 Oct 2022 13:28:43 +0530 Message-Id: <20221020075846.305576-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020075846.305576-1-apatel@ventanamicro.com> References: <20221020075846.305576-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Jones riscv_cbom_block_size and riscv_init_cbom_blocksize() should always be available and riscv_init_cbom_blocksize() should always be invoked, even when compiling without RISCV_ISA_ZICBOM enabled. This is because disabling RISCV_ISA_ZICBOM means "don't use zicbom instructions in the kernel" not "pretend there isn't zicbom, even when there is". When zicbom is available, whether the kernel enables its use with RISCV_ISA_ZICBOM or not, KVM will offer it to guests. Ensure we can build KVM and that the block size is initialized even when compiling without RISCV_ISA_ZICBOM. Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") Reported-by: kernel test robot Signed-off-by: Andrew Jones Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- arch/riscv/include/asm/cacheflush.h | 8 ------ arch/riscv/mm/cacheflush.c | 38 ++++++++++++++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 41 ----------------------------- 3 files changed, 38 insertions(+), 49 deletions(-) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 8a5c246b0a21..f6fbe7042f1c 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -42,16 +42,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local); #endif /* CONFIG_SMP */ -/* - * The T-Head CMO errata internally probe the CBOM block size, but otherwise - * don't depend on Zicbom. - */ extern unsigned int riscv_cbom_block_size; -#ifdef CONFIG_RISCV_ISA_ZICBOM void riscv_init_cbom_blocksize(void); -#else -static inline void riscv_init_cbom_blocksize(void) { } -#endif #ifdef CONFIG_RISCV_DMA_NONCOHERENT void riscv_noncoherent_supported(void); diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 6cb7d96ad9c7..57b40a350420 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #ifdef CONFIG_SMP @@ -86,3 +87,40 @@ void flush_icache_pte(pte_t pte) flush_icache_all(); } #endif /* CONFIG_MMU */ + +unsigned int riscv_cbom_block_size; +EXPORT_SYMBOL_GPL(riscv_cbom_block_size); + +void riscv_init_cbom_blocksize(void) +{ + struct device_node *node; + unsigned long cbom_hartid; + u32 val, probed_block_size; + int ret; + + probed_block_size = 0; + for_each_of_cpu_node(node) { + unsigned long hartid; + + ret = riscv_of_processor_hartid(node, &hartid); + if (ret) + continue; + + /* set block-size for cbom extension if available */ + ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); + if (ret) + continue; + + if (!probed_block_size) { + probed_block_size = val; + cbom_hartid = hartid; + } else { + if (probed_block_size != val) + pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", + cbom_hartid, hartid); + } + } + + if (probed_block_size) + riscv_cbom_block_size = probed_block_size; +} diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index b0add983530a..d919efab6eba 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -8,13 +8,8 @@ #include #include #include -#include -#include #include -unsigned int riscv_cbom_block_size; -EXPORT_SYMBOL_GPL(riscv_cbom_block_size); - static bool noncoherent_supported; void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, @@ -77,42 +72,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, dev->dma_coherent = coherent; } -#ifdef CONFIG_RISCV_ISA_ZICBOM -void riscv_init_cbom_blocksize(void) -{ - struct device_node *node; - unsigned long cbom_hartid; - u32 val, probed_block_size; - int ret; - - probed_block_size = 0; - for_each_of_cpu_node(node) { - unsigned long hartid; - - ret = riscv_of_processor_hartid(node, &hartid); - if (ret) - continue; - - /* set block-size for cbom extension if available */ - ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); - if (ret) - continue; - - if (!probed_block_size) { - probed_block_size = val; - cbom_hartid = hartid; - } else { - if (probed_block_size != val) - pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", - cbom_hartid, hartid); - } - } - - if (probed_block_size) - riscv_cbom_block_size = probed_block_size; -} -#endif - void riscv_noncoherent_supported(void) { WARN(!riscv_cbom_block_size, -- 2.34.1