From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: <ira.weiny@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
"Li, Ming" <ming4.li@intel.com>,
Bjorn Helgaas <helgaas@kernel.org>,
Matthew Wilcox <willy@infradead.org>,
Lukas Wunner <lukas@wunner.de>,
Alison Schofield <alison.schofield@intel.com>,
"Vishal Verma" <vishal.l.verma@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
"Ben Widawsky" <bwidawsk@kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
<linux-pci@vger.kernel.org>,
Gregory Price <gregory.price@memverge.com>
Subject: Re: [PATCH V16 3/6] PCI/DOE: Add DOE mailbox support functions
Date: Tue, 25 Oct 2022 12:03:15 +0100 [thread overview]
Message-ID: <20221025120315.00006cc3@huawei.com> (raw)
In-Reply-To: <20220719205249.566684-4-ira.weiny@intel.com>
On Tue, 19 Jul 2022 13:52:46 -0700
ira.weiny@intel.com wrote:
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> Introduced in a PCIe r6.0, sec 6.30, DOE provides a config space based
> mailbox with standard protocol discovery. Each mailbox is accessed
> through a DOE Extended Capability.
>
> Each DOE mailbox must support the DOE discovery protocol in addition to
> any number of additional protocols.
>
> Define core PCIe functionality to manage a single PCIe DOE mailbox at a
> defined config space offset. Functionality includes iterating,
> creating, query of supported protocol, and task submission. Destruction
> of the mailboxes is device managed.
>
> Cc: "Li, Ming" <ming4.li@intel.com>
> Cc: Bjorn Helgaas <helgaas@kernel.org>
> Cc: Matthew Wilcox <willy@infradead.org>
> Acked-by: Bjorn Helgaas <helgaas@kernel.org>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Co-developed-by: Ira Weiny <ira.weiny@intel.com>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
FYI. Gregory Price reported an an issue that I think
is related to calling INIT_WORK() rather than INIT_WORK_ONSTACK()
and associated debug options in his build.
https://lore.kernel.org/linux-cxl/20221014151045.24781-1-Jonathan.Cameron@huawei.com/T/#m88a7f50dcce52f30c8bf5c3dcc06fa9843b54a2d
I've highlighted one path to this below.
> diff --git a/drivers/pci/doe.c b/drivers/pci/doe.c
> new file mode 100644
> index 000000000000..e402f05068a5
> --- /dev/null
> +++ b/drivers/pci/doe.c
> @@ -0,0 +1,536 @@
> +static int pci_doe_discovery(struct pci_doe_mb *doe_mb, u8 *index, u16 *vid,
> + u8 *protocol)
> +{
> + u32 request_pl = FIELD_PREP(PCI_DOE_DATA_OBJECT_DISC_REQ_3_INDEX,
> + *index);
> + u32 response_pl;
> + DECLARE_COMPLETION_ONSTACK(c);
> + struct pci_doe_task task = {
> + .prot.vid = PCI_VENDOR_ID_PCI_SIG,
> + .prot.type = PCI_DOE_PROTOCOL_DISCOVERY,
> + .request_pl = &request_pl,
> + .request_pl_sz = sizeof(request_pl),
> + .response_pl = &response_pl,
> + .response_pl_sz = sizeof(response_pl),
> + .complete = pci_doe_task_complete,
> + .private = &c,
> + };
This structure contains a work_struct and is on the stack. However...
> + int rc;
> +
> + rc = pci_doe_submit_task(doe_mb, &task);
> + if (rc < 0)
> + return rc;
> +
> + wait_for_completion(&c);
> +
> + if (task.rv != sizeof(response_pl))
> + return -EIO;
> +
> + *vid = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_VID, response_pl);
> + *protocol = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_PROTOCOL,
> + response_pl);
> + *index = FIELD_GET(PCI_DOE_DATA_OBJECT_DISC_RSP_3_NEXT_INDEX,
> + response_pl);
> +
> + return 0;
> +}
...
> +int pci_doe_submit_task(struct pci_doe_mb *doe_mb, struct pci_doe_task *task)
> +{
> + if (!pci_doe_supports_prot(doe_mb, task->prot.vid, task->prot.type))
> + return -EINVAL;
> +
> + /*
> + * DOE requests must be a whole number of DW and the response needs to
> + * be big enough for at least 1 DW
> + */
> + if (task->request_pl_sz % sizeof(u32) ||
> + task->response_pl_sz < sizeof(u32))
> + return -EINVAL;
> +
> + if (test_bit(PCI_DOE_FLAG_DEAD, &doe_mb->flags))
> + return -EIO;
> +
> + task->doe_mb = doe_mb;
> + INIT_WORK(&task->work, doe_statemachine_work);
Here we don't call the INIT_WORK_ONSTACK() Variant.
> + queue_work(doe_mb->work_queue, &task->work);
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(pci_doe_submit_task);
next prev parent reply other threads:[~2022-10-25 11:03 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-19 20:52 [PATCH V16 0/6] CXL: Read CDAT ira.weiny
2022-07-19 20:52 ` [PATCH V16 1/6] PCI: Add vendor ID for the PCI SIG ira.weiny
2022-07-19 20:52 ` [PATCH V16 2/6] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
2022-07-19 20:52 ` [PATCH V16 3/6] PCI/DOE: Add DOE mailbox support functions ira.weiny
2022-08-15 2:17 ` Li, Ming
2022-08-15 9:50 ` Jonathan Cameron
2022-08-15 22:42 ` Dan Williams
2022-10-25 11:03 ` Jonathan Cameron [this message]
2022-07-19 20:52 ` [PATCH V16 4/6] cxl/pci: Create PCI DOE mailbox's for memory devices ira.weiny
2022-07-19 22:16 ` Bjorn Helgaas
2022-07-19 20:52 ` [PATCH V16 5/6] driver-core: Introduce BIN_ATTR_ADMIN_{RO,RW} ira.weiny
2022-07-19 20:52 ` [PATCH V16 6/6] cxl/port: Read CDAT table ira.weiny
2022-07-19 22:57 ` [PATCH V16 0/6] CXL: Read CDAT Dan Williams
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