From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Atish Patra <atishp@atishpatra.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 1/9] RISC-V: Add AIA related CSR defines
Date: Fri, 11 Nov 2022 10:11:59 +0530 [thread overview]
Message-ID: <20221111044207.1478350-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20221111044207.1478350-1-apatel@ventanamicro.com>
The RISC-V AIA specification improves handling per-HART local interrupts
in a backward compatible manner. This patch adds defines for new RISC-V
AIA CSRs.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
arch/riscv/include/asm/csr.h | 92 ++++++++++++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 0e571f6483d9..4e1356bad7b2 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -73,7 +73,10 @@
#define IRQ_S_EXT 9
#define IRQ_VS_EXT 10
#define IRQ_M_EXT 11
+#define IRQ_S_GEXT 12
#define IRQ_PMU_OVF 13
+#define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1)
+#define IRQ_LOCAL_MASK ((_AC(1, UL) << IRQ_LOCAL_MAX) - 1)
/* Exception causes */
#define EXC_INST_MISALIGNED 0
@@ -156,6 +159,26 @@
(_AC(1, UL) << IRQ_S_TIMER) | \
(_AC(1, UL) << IRQ_S_EXT))
+/* AIA CSR bits */
+#define TOPI_IID_SHIFT 16
+#define TOPI_IID_MASK 0xfff
+#define TOPI_IPRIO_MASK 0xff
+#define TOPI_IPRIO_BITS 8
+
+#define TOPEI_ID_SHIFT 16
+#define TOPEI_ID_MASK 0x7ff
+#define TOPEI_PRIO_MASK 0x7ff
+
+#define ISELECT_IPRIO0 0x30
+#define ISELECT_IPRIO15 0x3f
+#define ISELECT_MASK 0x1ff
+
+#define HVICTL_VTI 0x40000000
+#define HVICTL_IID 0x0fff0000
+#define HVICTL_IID_SHIFT 16
+#define HVICTL_IPRIOM 0x00000100
+#define HVICTL_IPRIO 0x000000ff
+
/* xENVCFG flags */
#define ENVCFG_STCE (_AC(1, ULL) << 63)
#define ENVCFG_PBMTE (_AC(1, ULL) << 62)
@@ -250,6 +273,18 @@
#define CSR_STIMECMP 0x14D
#define CSR_STIMECMPH 0x15D
+/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
+#define CSR_SISELECT 0x150
+#define CSR_SIREG 0x151
+
+/* Supervisor-Level Interrupts (AIA) */
+#define CSR_STOPEI 0x15c
+#define CSR_STOPI 0xdb0
+
+/* Supervisor-Level High-Half CSRs (AIA) */
+#define CSR_SIEH 0x114
+#define CSR_SIPH 0x154
+
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
#define CSR_VSTVEC 0x205
@@ -279,8 +314,32 @@
#define CSR_HGATP 0x680
#define CSR_HGEIP 0xe12
+/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+#define CSR_HVIEN 0x608
+#define CSR_HVICTL 0x609
+#define CSR_HVIPRIO1 0x646
+#define CSR_HVIPRIO2 0x647
+
+/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
+#define CSR_VSISELECT 0x250
+#define CSR_VSIREG 0x251
+
+/* VS-Level Interrupts (H-extension with AIA) */
+#define CSR_VSTOPEI 0x25c
+#define CSR_VSTOPI 0xeb0
+
+/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
+#define CSR_HIDELEGH 0x613
+#define CSR_HVIENH 0x618
+#define CSR_HVIPH 0x655
+#define CSR_HVIPRIO1H 0x656
+#define CSR_HVIPRIO2H 0x657
+#define CSR_VSIEH 0x214
+#define CSR_VSIPH 0x254
+
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
+#define CSR_MIDELEG 0x303
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#define CSR_MENVCFG 0x30a
@@ -297,6 +356,25 @@
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
+/* Machine-Level Window to Indirectly Accessed Registers (AIA) */
+#define CSR_MISELECT 0x350
+#define CSR_MIREG 0x351
+
+/* Machine-Level Interrupts (AIA) */
+#define CSR_MTOPEI 0x35c
+#define CSR_MTOPI 0xfb0
+
+/* Virtual Interrupts for Supervisor Level (AIA) */
+#define CSR_MVIEN 0x308
+#define CSR_MVIP 0x309
+
+/* Machine-Level High-Half CSRs (AIA) */
+#define CSR_MIDELEGH 0x313
+#define CSR_MIEH 0x314
+#define CSR_MVIENH 0x318
+#define CSR_MVIPH 0x319
+#define CSR_MIPH 0x354
+
#ifdef CONFIG_RISCV_M_MODE
# define CSR_STATUS CSR_MSTATUS
# define CSR_IE CSR_MIE
@@ -307,6 +385,13 @@
# define CSR_TVAL CSR_MTVAL
# define CSR_IP CSR_MIP
+# define CSR_IEH CSR_MIEH
+# define CSR_ISELECT CSR_MISELECT
+# define CSR_IREG CSR_MIREG
+# define CSR_IPH CSR_MIPH
+# define CSR_TOPEI CSR_MTOPEI
+# define CSR_TOPI CSR_MTOPI
+
# define SR_IE SR_MIE
# define SR_PIE SR_MPIE
# define SR_PP SR_MPP
@@ -324,6 +409,13 @@
# define CSR_TVAL CSR_STVAL
# define CSR_IP CSR_SIP
+# define CSR_IEH CSR_SIEH
+# define CSR_ISELECT CSR_SISELECT
+# define CSR_IREG CSR_SIREG
+# define CSR_IPH CSR_SIPH
+# define CSR_TOPEI CSR_STOPEI
+# define CSR_TOPI CSR_STOPI
+
# define SR_IE SR_SIE
# define SR_PIE SR_SPIE
# define SR_PP SR_SPP
--
2.34.1
next prev parent reply other threads:[~2022-11-11 4:43 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 4:41 [PATCH 0/9] Linux RISC-V AIA Support Anup Patel
2022-11-11 4:41 ` Anup Patel [this message]
2022-11-11 4:42 ` [PATCH 2/9] RISC-V: Detect AIA CSRs from ISA string Anup Patel
2022-11-13 14:20 ` Conor Dooley
2022-11-11 4:42 ` [PATCH 3/9] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2022-11-11 4:42 ` [PATCH 4/9] dt-bindings: Add RISC-V incoming MSI controller bindings Anup Patel
2022-11-11 9:11 ` Atish Patra
2022-11-13 14:48 ` Conor Dooley
2022-11-14 12:29 ` Anup Patel
2022-11-15 22:34 ` Conor Dooley
2022-11-16 9:00 ` Krzysztof Kozlowski
2022-11-16 9:20 ` Conor Dooley
2022-11-16 9:21 ` Krzysztof Kozlowski
2022-11-16 10:34 ` Anup Patel
2022-11-16 13:29 ` Conor Dooley
2022-11-14 9:49 ` Krzysztof Kozlowski
2022-11-14 12:06 ` Anup Patel
2022-11-14 12:14 ` Conor Dooley
2022-11-14 12:21 ` Krzysztof Kozlowski
2022-11-14 15:04 ` Anup Patel
2022-11-15 14:15 ` Krzysztof Kozlowski
2022-11-16 19:14 ` Rob Herring
2023-01-02 15:59 ` Anup Patel
2022-11-11 4:42 ` [PATCH 5/9] irqchip: Add RISC-V incoming MSI controller driver Anup Patel
2022-11-11 16:02 ` Andrew Bresticker
2023-01-02 16:25 ` Anup Patel
2022-11-11 4:42 ` [PATCH 6/9] dt-bindings: Add RISC-V advanced PLIC bindings Anup Patel
2022-11-13 15:44 ` Conor Dooley
2023-01-02 16:50 ` Anup Patel
2023-01-02 18:17 ` Conor Dooley
2023-01-03 5:10 ` Anup Patel
2023-01-03 8:59 ` Krzysztof Kozlowski
2023-01-03 13:05 ` Anup Patel
2022-11-14 9:51 ` Krzysztof Kozlowski
2022-11-14 12:11 ` Anup Patel
2022-11-16 19:27 ` Rob Herring
2023-01-02 17:18 ` Anup Patel
2022-11-11 4:42 ` [PATCH 7/9] irqchip: Add RISC-V advanced PLIC driver Anup Patel
2022-11-11 23:17 ` Andrew Bresticker
2022-11-11 4:42 ` [PATCH 8/9] RISC-V: Select APLIC and IMSIC drivers for QEMU virt machine Anup Patel
2022-11-15 22:29 ` Conor Dooley
2022-11-11 4:42 ` [PATCH 9/9] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2022-11-11 9:07 ` [PATCH 0/9] Linux RISC-V AIA Support Atish Patra
2022-11-11 9:13 ` Atish Patra
2022-11-11 19:01 ` Atish Patra
2023-01-02 10:06 ` Anup Patel
2023-01-02 10:05 ` Anup Patel
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