From: Yang Weijiang <weijiang.yang@intel.com>
To: seanjc@google.com, pbonzini@redhat.com, jmattson@google.com,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: like.xu.linux@gmail.com, kan.liang@linux.intel.com,
wei.w.wang@intel.com, weijiang.yang@intel.com,
Like Xu <like.xu@linux.intel.com>
Subject: [PATCH v2 06/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL for guest Arch LBR
Date: Thu, 24 Nov 2022 23:05:55 -0500 [thread overview]
Message-ID: <20221125040604.5051-7-weijiang.yang@intel.com> (raw)
In-Reply-To: <20221125040604.5051-1-weijiang.yang@intel.com>
From: Paolo Bonzini <pbonzini@redhat.com>
Arch LBR is enabled by setting MSR_ARCH_LBR_CTL.LBREn to 1. A new guest
state field named "Guest IA32_LBR_CTL" is added to enhance guest LBR usage.
When guest Arch LBR is enabled, a guest LBR event will be created like the
model-specific LBR does. Clear guest LBR enable bit on host PMI handling so
guest can see expected config.
On processors that support Arch LBR, MSR_IA32_DEBUGCTLMSR[bit 0] has no
meaning. It can be written to 0 or 1, but reads will always return 0.
Like IA32_DEBUGCTL, IA32_ARCH_LBR_CTL msr is also preserved on INIT.
Regardless of the Arch LBR or legacy LBR, when the LBR_EN bit 0 of the
corresponding control MSR is set to 1, LBR recording will be enabled.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Co-developed-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Co-developed-by: Yang Weijiang <weijiang.yang@intel.com>
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
---
arch/x86/events/intel/lbr.c | 2 -
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/vmx.h | 2 +
arch/x86/kvm/vmx/pmu_intel.c | 67 ++++++++++++++++++++++++++++----
arch/x86/kvm/vmx/vmx.c | 7 ++++
5 files changed, 69 insertions(+), 10 deletions(-)
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index e7caabfa1377..ef589984b907 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -100,8 +100,6 @@
ARCH_LBR_RETURN |\
ARCH_LBR_OTHER_BRANCH)
-#define ARCH_LBR_CTL_MASK 0x7f000e
-
static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
static __always_inline bool is_lbr_call_stack_bit_set(u64 config)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 10ac52705892..2a9eaab2fdb1 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -220,6 +220,7 @@
#define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
#define MSR_ARCH_LBR_CTL 0x000014ce
+#define ARCH_LBR_CTL_MASK 0x7f000e
#define ARCH_LBR_CTL_LBREN BIT(0)
#define ARCH_LBR_CTL_CPL_OFFSET 1
#define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 498dc600bd5c..8502c068202c 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -257,6 +257,8 @@ enum vmcs_field {
GUEST_BNDCFGS_HIGH = 0x00002813,
GUEST_IA32_RTIT_CTL = 0x00002814,
GUEST_IA32_RTIT_CTL_HIGH = 0x00002815,
+ GUEST_IA32_LBR_CTL = 0x00002816,
+ GUEST_IA32_LBR_CTL_HIGH = 0x00002817,
HOST_IA32_PAT = 0x00002c00,
HOST_IA32_PAT_HIGH = 0x00002c01,
HOST_IA32_EFER = 0x00002c02,
diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index 0c78cb4b72be..b57944d5e7d8 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -19,6 +19,7 @@
#include "pmu.h"
#define MSR_PMC_FULL_WIDTH_BIT (MSR_IA32_PMC0 - MSR_IA32_PERFCTR0)
+#define KVM_ARCH_LBR_CTL_MASK (ARCH_LBR_CTL_MASK | ARCH_LBR_CTL_LBREN)
static struct kvm_event_hw_type_mapping intel_arch_events[] = {
[0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES },
@@ -178,7 +179,7 @@ static bool intel_pmu_is_valid_lbr_msr(struct kvm_vcpu *vcpu, u32 index)
(index == MSR_LBR_SELECT || index == MSR_LBR_TOS))
return true;
- if (index == MSR_ARCH_LBR_DEPTH)
+ if (index == MSR_ARCH_LBR_DEPTH || index == MSR_ARCH_LBR_CTL)
return kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR) &&
guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR);
@@ -345,6 +346,30 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu,
return true;
}
+static bool arch_lbr_ctl_is_valid(struct kvm_vcpu *vcpu, u64 ctl)
+{
+ struct kvm_cpuid_entry2 *entry;
+ struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
+
+ if (!pmu->kvm_arch_lbr_depth)
+ return false;
+
+ if (ctl & ~KVM_ARCH_LBR_CTL_MASK)
+ return false;
+
+ entry = kvm_find_cpuid_entry(vcpu, 0x1c);
+ if (!entry)
+ return false;
+
+ if (!(entry->ebx & BIT(0)) && (ctl & ARCH_LBR_CTL_CPL))
+ return false;
+ if (!(entry->ebx & BIT(2)) && (ctl & ARCH_LBR_CTL_STACK))
+ return false;
+ if (!(entry->ebx & BIT(1)) && (ctl & ARCH_LBR_CTL_FILTER))
+ return false;
+ return true;
+}
+
static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
{
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
@@ -377,6 +402,14 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
case MSR_ARCH_LBR_DEPTH:
msr_info->data = lbr_desc->records.nr;
return 0;
+ case MSR_ARCH_LBR_CTL:
+ if (!kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR)) {
+ WARN_ON_ONCE(!msr_info->host_initiated);
+ msr_info->data = 0;
+ } else {
+ msr_info->data = vmcs_read64(GUEST_IA32_LBR_CTL);
+ }
+ return 0;
default:
if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
(pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {
@@ -483,6 +516,18 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
if (kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR))
wrmsrl(MSR_ARCH_LBR_DEPTH, lbr_desc->records.nr);
return 0;
+ case MSR_ARCH_LBR_CTL:
+ if (msr_info->host_initiated && !pmu->kvm_arch_lbr_depth)
+ return data != 0;
+
+ if (!arch_lbr_ctl_is_valid(vcpu, data))
+ break;
+
+ vmcs_write64(GUEST_IA32_LBR_CTL, data);
+ if (intel_pmu_lbr_is_enabled(vcpu) && !lbr_desc->event &&
+ (data & ARCH_LBR_CTL_LBREN))
+ intel_pmu_create_guest_lbr_event(vcpu);
+ return 0;
default:
if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
(pmc = get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) {
@@ -727,12 +772,16 @@ static void intel_pmu_reset(struct kvm_vcpu *vcpu)
*/
static void intel_pmu_legacy_freezing_lbrs_on_pmi(struct kvm_vcpu *vcpu)
{
- u64 data = vmcs_read64(GUEST_IA32_DEBUGCTL);
+ u32 lbr_ctl_field = GUEST_IA32_DEBUGCTL;
- if (data & DEBUGCTLMSR_FREEZE_LBRS_ON_PMI) {
- data &= ~DEBUGCTLMSR_LBR;
- vmcs_write64(GUEST_IA32_DEBUGCTL, data);
- }
+ if (!(vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_FREEZE_LBRS_ON_PMI))
+ return;
+
+ if (kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR) &&
+ guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR))
+ lbr_ctl_field = GUEST_IA32_LBR_CTL;
+
+ vmcs_write64(lbr_ctl_field, vmcs_read64(lbr_ctl_field) & ~0x1ULL);
}
static void intel_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
@@ -801,7 +850,8 @@ void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu)
{
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
- bool lbr_enable = !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR) &&
+ bool lbr_enable = guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR) ?
+ (vmcs_read64(GUEST_IA32_LBR_CTL) & ARCH_LBR_CTL_LBREN) :
(vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR);
if (!lbr_desc->event) {
@@ -829,7 +879,8 @@ void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu)
static void intel_pmu_cleanup(struct kvm_vcpu *vcpu)
{
- bool lbr_enable = !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR) &&
+ bool lbr_enable = guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR) ?
+ (vmcs_read64(GUEST_IA32_LBR_CTL) & ARCH_LBR_CTL_LBREN) :
(vmcs_read64(GUEST_IA32_DEBUGCTL) & DEBUGCTLMSR_LBR);
if (!lbr_enable)
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index cea8c07f5229..1ae2efc29546 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -2120,6 +2120,13 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
VM_EXIT_SAVE_DEBUG_CONTROLS)
get_vmcs12(vcpu)->guest_ia32_debugctl = data;
+ /*
+ * For Arch LBR, IA32_DEBUGCTL[bit 0] has no meaning.
+ * It can be written to 0 or 1, but reads will always return 0.
+ */
+ if (guest_cpuid_has(vcpu, X86_FEATURE_ARCH_LBR))
+ data &= ~DEBUGCTLMSR_LBR;
+
vmcs_write64(GUEST_IA32_DEBUGCTL, data);
if (intel_pmu_lbr_is_enabled(vcpu) && !to_vmx(vcpu)->lbr_desc.event &&
(data & DEBUGCTLMSR_LBR))
--
2.27.0
next prev parent reply other threads:[~2022-11-25 6:10 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-25 4:05 [PATCH v2 00/15] Introduce Architectural LBR for vPMU Yang Weijiang
2022-11-25 4:05 ` [PATCH v2 01/15] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers Yang Weijiang
2022-12-22 10:57 ` Like Xu
2022-12-22 13:29 ` Peter Zijlstra
2022-12-22 17:41 ` Sean Christopherson
2022-12-23 2:12 ` Like Xu
2022-12-27 11:58 ` [tip: perf/core] " tip-bot2 for Like Xu
2022-11-25 4:05 ` [PATCH v2 02/15] KVM: x86: Report XSS as an MSR to be saved if there are supported features Yang Weijiang
2022-11-25 4:05 ` [PATCH v2 03/15] KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS Yang Weijiang
2023-01-26 19:50 ` Sean Christopherson
2023-01-30 6:33 ` Yang, Weijiang
2022-11-25 4:05 ` [PATCH v2 04/15] KVM: PMU: disable LBR handling if architectural LBR is available Yang Weijiang
2023-01-27 20:10 ` Sean Christopherson
2023-01-30 8:10 ` Yang, Weijiang
2022-11-25 4:05 ` [PATCH v2 05/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR Yang Weijiang
2022-12-22 11:00 ` Like Xu
2022-12-25 4:30 ` Yang, Weijiang
2022-12-22 11:15 ` Like Xu
2023-01-27 20:25 ` Sean Christopherson
2023-01-30 11:46 ` Yang, Weijiang
2022-11-25 4:05 ` Yang Weijiang [this message]
2022-12-22 11:09 ` [PATCH v2 06/15] KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL " Like Xu
2022-12-25 4:27 ` Yang, Weijiang
2022-12-22 11:19 ` Like Xu
2022-12-25 4:16 ` Yang, Weijiang
2022-12-22 11:24 ` Like Xu
2022-12-25 4:08 ` Yang, Weijiang
2023-01-27 21:42 ` Sean Christopherson
2022-11-25 4:05 ` [PATCH v2 07/15] KVM: VMX: Support passthrough of architectural LBRs Yang Weijiang
2022-11-25 4:05 ` [PATCH v2 08/15] KVM: x86: Add Arch LBR MSRs to msrs_to_save_all list Yang Weijiang
2023-01-27 21:43 ` Sean Christopherson
2023-01-30 12:27 ` Yang, Weijiang
2022-11-25 4:05 ` [PATCH v2 09/15] KVM: x86: Refine the matching and clearing logic for supported_xss Yang Weijiang
2023-01-27 21:46 ` Sean Christopherson
2023-01-30 12:37 ` Yang, Weijiang
2022-11-25 4:05 ` [PATCH v2 10/15] KVM: x86/vmx: Check Arch LBR config when return perf capabilities Yang Weijiang
2022-12-22 11:06 ` Like Xu
2022-12-25 4:28 ` Yang, Weijiang
2023-01-27 22:04 ` Sean Christopherson
2022-11-25 4:06 ` [PATCH v2 11/15] KVM: x86: Add XSAVE Support for Architectural LBR Yang Weijiang
2023-01-27 22:07 ` Sean Christopherson
2023-01-30 13:13 ` Yang, Weijiang
2022-11-25 4:06 ` [PATCH v2 12/15] KVM: x86/vmx: Disable Arch LBREn bit in #DB and warm reset Yang Weijiang
2022-12-22 11:22 ` Like Xu
2022-12-25 4:12 ` Yang, Weijiang
2023-01-27 22:09 ` Sean Christopherson
2023-01-30 13:09 ` Yang, Weijiang
2022-11-25 4:06 ` [PATCH v2 13/15] KVM: x86/vmx: Save/Restore guest Arch LBR Ctrl msr at SMM entry/exit Yang Weijiang
2023-01-27 22:11 ` Sean Christopherson
2023-01-30 12:50 ` Yang, Weijiang
2022-11-25 4:06 ` [PATCH v2 14/15] KVM: x86: Add Arch LBR data MSR access interface Yang Weijiang
2023-01-27 22:13 ` Sean Christopherson
2023-01-30 12:46 ` Yang, Weijiang
2023-01-30 17:30 ` Sean Christopherson
2023-01-31 13:14 ` Yang, Weijiang
2023-01-31 16:05 ` Sean Christopherson
2022-11-25 4:06 ` [PATCH v2 15/15] KVM: x86/cpuid: Advertise Arch LBR feature in CPUID Yang Weijiang
2022-12-22 11:03 ` Like Xu
2022-12-25 4:31 ` Yang, Weijiang
2023-01-27 22:15 ` Sean Christopherson
2023-01-12 1:57 ` [PATCH v2 00/15] Introduce Architectural LBR for vPMU Yang, Weijiang
2023-01-27 22:46 ` Sean Christopherson
2023-01-30 13:38 ` Yang, Weijiang
2023-06-05 9:50 ` Like Xu
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