* [PATCH v11 1/6] media: platform: chips-media: Move Coda to separate folder [not found] <20221207121350.66217-1-sebastian.fricke@collabora.com> @ 2022-12-07 12:13 ` Sebastian Fricke 2022-12-07 12:54 ` Philipp Zabel 2022-12-07 20:44 ` kernel test robot 2022-12-07 12:13 ` [PATCH v11 2/6] media: chips-media: wave5: Add vpuapi layer Sebastian Fricke ` (4 subsequent siblings) 5 siblings, 2 replies; 22+ messages in thread From: Sebastian Fricke @ 2022-12-07 12:13 UTC (permalink / raw) To: linux-media, Mauro Carvalho Chehab, Philipp Zabel, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team Cc: kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, Sebastian Fricke, linux-kernel, linux-arm-kernel Prepare the folder structure for a second Chips&Media driver. Move the Coda driver to a sub-directory. Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> --- MAINTAINERS | 2 +- drivers/media/platform/chips-media/Kconfig | 17 +---------------- drivers/media/platform/chips-media/Makefile | 5 +---- .../media/platform/chips-media/coda/Kconfig | 18 ++++++++++++++++++ .../media/platform/chips-media/coda/Makefile | 6 ++++++ .../platform/chips-media/{ => coda}/coda-bit.c | 0 .../chips-media/{ => coda}/coda-common.c | 0 .../platform/chips-media/{ => coda}/coda-gdi.c | 0 .../chips-media/{ => coda}/coda-h264.c | 0 .../chips-media/{ => coda}/coda-jpeg.c | 0 .../chips-media/{ => coda}/coda-mpeg2.c | 0 .../chips-media/{ => coda}/coda-mpeg4.c | 0 .../platform/chips-media/{ => coda}/coda.h | 0 .../chips-media/{ => coda}/coda_regs.h | 0 .../platform/chips-media/{ => coda}/imx-vdoa.c | 0 .../platform/chips-media/{ => coda}/imx-vdoa.h | 0 .../platform/chips-media/{ => coda}/trace.h | 0 17 files changed, 27 insertions(+), 21 deletions(-) create mode 100644 drivers/media/platform/chips-media/coda/Kconfig create mode 100644 drivers/media/platform/chips-media/coda/Makefile rename drivers/media/platform/chips-media/{ => coda}/coda-bit.c (100%) rename drivers/media/platform/chips-media/{ => coda}/coda-common.c (100%) rename drivers/media/platform/chips-media/{ => coda}/coda-gdi.c (100%) rename drivers/media/platform/chips-media/{ => coda}/coda-h264.c (100%) rename drivers/media/platform/chips-media/{ => coda}/coda-jpeg.c (100%) rename drivers/media/platform/chips-media/{ => coda}/coda-mpeg2.c (100%) rename drivers/media/platform/chips-media/{ => coda}/coda-mpeg4.c (100%) rename drivers/media/platform/chips-media/{ => coda}/coda.h (100%) rename drivers/media/platform/chips-media/{ => coda}/coda_regs.h (100%) rename drivers/media/platform/chips-media/{ => coda}/imx-vdoa.c (100%) rename drivers/media/platform/chips-media/{ => coda}/imx-vdoa.h (100%) rename drivers/media/platform/chips-media/{ => coda}/trace.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 2bde5e62748a..83801ff3507d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5158,7 +5158,7 @@ M: Philipp Zabel <p.zabel@pengutronix.de> L: linux-media@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/media/coda.yaml -F: drivers/media/platform/chips-media/ +F: drivers/media/platform/chips-media/coda CODE OF CONDUCT M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> diff --git a/drivers/media/platform/chips-media/Kconfig b/drivers/media/platform/chips-media/Kconfig index 57f8f8a22df8..f87a0d693df7 100644 --- a/drivers/media/platform/chips-media/Kconfig +++ b/drivers/media/platform/chips-media/Kconfig @@ -2,19 +2,4 @@ comment "Chips&Media media platform drivers" -config VIDEO_CODA - tristate "Chips&Media Coda multi-standard codec IP" - depends on V4L_MEM2MEM_DRIVERS - depends on VIDEO_DEV && OF && (ARCH_MXC || COMPILE_TEST) - select SRAM - select VIDEOBUF2_DMA_CONTIG - select VIDEOBUF2_VMALLOC - select V4L2_JPEG_HELPER - select V4L2_MEM2MEM_DEV - select GENERIC_ALLOCATOR - help - Coda is a range of video codec IPs that supports - H.264, MPEG-4, and other video formats. - -config VIDEO_IMX_VDOA - def_tristate VIDEO_CODA if SOC_IMX6Q || COMPILE_TEST +source "drivers/media/platform/chips-media/coda/Kconfig" diff --git a/drivers/media/platform/chips-media/Makefile b/drivers/media/platform/chips-media/Makefile index bbb16425a875..5ee693f651c1 100644 --- a/drivers/media/platform/chips-media/Makefile +++ b/drivers/media/platform/chips-media/Makefile @@ -1,6 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -coda-vpu-objs := coda-common.o coda-bit.o coda-gdi.o coda-h264.o coda-mpeg2.o coda-mpeg4.o coda-jpeg.o - -obj-$(CONFIG_VIDEO_CODA) += coda-vpu.o -obj-$(CONFIG_VIDEO_IMX_VDOA) += imx-vdoa.o +obj-y += coda/ diff --git a/drivers/media/platform/chips-media/coda/Kconfig b/drivers/media/platform/chips-media/coda/Kconfig new file mode 100644 index 000000000000..cb7b66c71380 --- /dev/null +++ b/drivers/media/platform/chips-media/coda/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config VIDEO_CODA + tristate "Chips&Media Coda multi-standard codec IP" + depends on V4L_MEM2MEM_DRIVERS + depends on VIDEO_DEV && OF && (ARCH_MXC || COMPILE_TEST) + select SRAM + select VIDEOBUF2_DMA_CONTIG + select VIDEOBUF2_VMALLOC + select V4L2_JPEG_HELPER + select V4L2_MEM2MEM_DEV + select GENERIC_ALLOCATOR + help + Coda is a range of video codec IPs that supports + H.264, MPEG-4, and other video formats. + +config VIDEO_IMX_VDOA + def_tristate VIDEO_CODA if SOC_IMX6Q || COMPILE_TEST diff --git a/drivers/media/platform/chips-media/coda/Makefile b/drivers/media/platform/chips-media/coda/Makefile new file mode 100644 index 000000000000..bbb16425a875 --- /dev/null +++ b/drivers/media/platform/chips-media/coda/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +coda-vpu-objs := coda-common.o coda-bit.o coda-gdi.o coda-h264.o coda-mpeg2.o coda-mpeg4.o coda-jpeg.o + +obj-$(CONFIG_VIDEO_CODA) += coda-vpu.o +obj-$(CONFIG_VIDEO_IMX_VDOA) += imx-vdoa.o diff --git a/drivers/media/platform/chips-media/coda-bit.c b/drivers/media/platform/chips-media/coda/coda-bit.c similarity index 100% rename from drivers/media/platform/chips-media/coda-bit.c rename to drivers/media/platform/chips-media/coda/coda-bit.c diff --git a/drivers/media/platform/chips-media/coda-common.c b/drivers/media/platform/chips-media/coda/coda-common.c similarity index 100% rename from drivers/media/platform/chips-media/coda-common.c rename to drivers/media/platform/chips-media/coda/coda-common.c diff --git a/drivers/media/platform/chips-media/coda-gdi.c b/drivers/media/platform/chips-media/coda/coda-gdi.c similarity index 100% rename from drivers/media/platform/chips-media/coda-gdi.c rename to drivers/media/platform/chips-media/coda/coda-gdi.c diff --git a/drivers/media/platform/chips-media/coda-h264.c b/drivers/media/platform/chips-media/coda/coda-h264.c similarity index 100% rename from drivers/media/platform/chips-media/coda-h264.c rename to drivers/media/platform/chips-media/coda/coda-h264.c diff --git a/drivers/media/platform/chips-media/coda-jpeg.c b/drivers/media/platform/chips-media/coda/coda-jpeg.c similarity index 100% rename from drivers/media/platform/chips-media/coda-jpeg.c rename to drivers/media/platform/chips-media/coda/coda-jpeg.c diff --git a/drivers/media/platform/chips-media/coda-mpeg2.c b/drivers/media/platform/chips-media/coda/coda-mpeg2.c similarity index 100% rename from drivers/media/platform/chips-media/coda-mpeg2.c rename to drivers/media/platform/chips-media/coda/coda-mpeg2.c diff --git a/drivers/media/platform/chips-media/coda-mpeg4.c b/drivers/media/platform/chips-media/coda/coda-mpeg4.c similarity index 100% rename from drivers/media/platform/chips-media/coda-mpeg4.c rename to drivers/media/platform/chips-media/coda/coda-mpeg4.c diff --git a/drivers/media/platform/chips-media/coda.h b/drivers/media/platform/chips-media/coda/coda.h similarity index 100% rename from drivers/media/platform/chips-media/coda.h rename to drivers/media/platform/chips-media/coda/coda.h diff --git a/drivers/media/platform/chips-media/coda_regs.h b/drivers/media/platform/chips-media/coda/coda_regs.h similarity index 100% rename from drivers/media/platform/chips-media/coda_regs.h rename to drivers/media/platform/chips-media/coda/coda_regs.h diff --git a/drivers/media/platform/chips-media/imx-vdoa.c b/drivers/media/platform/chips-media/coda/imx-vdoa.c similarity index 100% rename from drivers/media/platform/chips-media/imx-vdoa.c rename to drivers/media/platform/chips-media/coda/imx-vdoa.c diff --git a/drivers/media/platform/chips-media/imx-vdoa.h b/drivers/media/platform/chips-media/coda/imx-vdoa.h similarity index 100% rename from drivers/media/platform/chips-media/imx-vdoa.h rename to drivers/media/platform/chips-media/coda/imx-vdoa.h diff --git a/drivers/media/platform/chips-media/trace.h b/drivers/media/platform/chips-media/coda/trace.h similarity index 100% rename from drivers/media/platform/chips-media/trace.h rename to drivers/media/platform/chips-media/coda/trace.h -- 2.25.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v11 1/6] media: platform: chips-media: Move Coda to separate folder 2022-12-07 12:13 ` [PATCH v11 1/6] media: platform: chips-media: Move Coda to separate folder Sebastian Fricke @ 2022-12-07 12:54 ` Philipp Zabel 2022-12-07 20:44 ` kernel test robot 1 sibling, 0 replies; 22+ messages in thread From: Philipp Zabel @ 2022-12-07 12:54 UTC (permalink / raw) To: Sebastian Fricke, linux-media, Mauro Carvalho Chehab, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team Cc: kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, linux-kernel, linux-arm-kernel Hi Sebastian, On Mi, 2022-12-07 at 13:13 +0100, Sebastian Fricke wrote: > Prepare the folder structure for a second Chips&Media driver. > Move the Coda driver to a sub-directory. > > Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> > --- > MAINTAINERS | 2 +- > drivers/media/platform/chips-media/Kconfig | 17 +---------------- > drivers/media/platform/chips-media/Makefile | 5 +---- > .../media/platform/chips-media/coda/Kconfig | 18 ++++++++++++++++++ > .../media/platform/chips-media/coda/Makefile | 6 ++++++ > .../platform/chips-media/{ => coda}/coda-bit.c | 0 > .../chips-media/{ => coda}/coda-common.c | 0 > .../platform/chips-media/{ => coda}/coda-gdi.c | 0 > .../chips-media/{ => coda}/coda-h264.c | 0 > .../chips-media/{ => coda}/coda-jpeg.c | 0 > .../chips-media/{ => coda}/coda-mpeg2.c | 0 > .../chips-media/{ => coda}/coda-mpeg4.c | 0 > .../platform/chips-media/{ => coda}/coda.h | 0 > .../chips-media/{ => coda}/coda_regs.h | 0 > .../platform/chips-media/{ => coda}/imx-vdoa.c | 0 > .../platform/chips-media/{ => coda}/imx-vdoa.h | 0 > .../platform/chips-media/{ => coda}/trace.h | 0 TRACE_INCLUDE_PATH in trace.h needs to be updated. For reference, see commit 64441979bda6 ("media: platform: rename coda/ to chips-media/"). regards Philipp ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v11 1/6] media: platform: chips-media: Move Coda to separate folder 2022-12-07 12:13 ` [PATCH v11 1/6] media: platform: chips-media: Move Coda to separate folder Sebastian Fricke 2022-12-07 12:54 ` Philipp Zabel @ 2022-12-07 20:44 ` kernel test robot 1 sibling, 0 replies; 22+ messages in thread From: kernel test robot @ 2022-12-07 20:44 UTC (permalink / raw) To: Sebastian Fricke, linux-media, Mauro Carvalho Chehab, Philipp Zabel, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team Cc: oe-kbuild-all, kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, Sebastian Fricke, linux-kernel, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 2423 bytes --] Hi Sebastian, Thank you for the patch! Yet something to improve: [auto build test ERROR on media-tree/master] [also build test ERROR on robh/for-next linus/master sailus-media-tree/streams v6.1-rc8 next-20221207] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Sebastian-Fricke/Wave5-codec-driver/20221207-201618 base: git://linuxtv.org/media_tree.git master patch link: https://lore.kernel.org/r/20221207121350.66217-2-sebastian.fricke%40collabora.com patch subject: [PATCH v11 1/6] media: platform: chips-media: Move Coda to separate folder config: ia64-allmodconfig compiler: ia64-linux-gcc (GCC) 12.1.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/011f0f8174292005830e2a8b709faa6028c03361 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Sebastian-Fricke/Wave5-codec-driver/20221207-201618 git checkout 011f0f8174292005830e2a8b709faa6028c03361 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=ia64 SHELL=/bin/bash drivers/media/platform/chips-media/coda/ If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): In file included from drivers/media/platform/chips-media/coda/trace.h:175, from drivers/media/platform/chips-media/coda/coda-bit.c:32: >> include/trace/define_trace.h:95:42: fatal error: ../../drivers/media/platform/chips-media/trace.h: No such file or directory 95 | #include TRACE_INCLUDE(TRACE_INCLUDE_FILE) | ^ compilation terminated. vim +95 include/trace/define_trace.h a8d154b0091683 Steven Rostedt 2009-04-10 94 a8d154b0091683 Steven Rostedt 2009-04-10 @95 #include TRACE_INCLUDE(TRACE_INCLUDE_FILE) a8d154b0091683 Steven Rostedt 2009-04-10 96 -- 0-DAY CI Kernel Test Service https://01.org/lkp [-- Attachment #2: config --] [-- Type: text/plain, Size: 287213 bytes --] # # Automatically generated file; DO NOT EDIT. # Linux/ia64 6.1.0-rc4 Kernel Configuration # CONFIG_CC_VERSION_TEXT="ia64-linux-gcc (GCC) 12.1.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=120100 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=23800 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23800 CONFIG_LLD_VERSION=0 CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=123 CONFIG_CONSTRUCTORS=y CONFIG_IRQ_WORK=y # # General setup # CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_COMPILE_TEST=y # CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_BUILD_SALT="" CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_WATCH_QUEUE=y CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_USELIB=y CONFIG_AUDIT=y CONFIG_HAVE_ARCH_AUDITSYSCALL=y CONFIG_AUDITSYSCALL=y # # IRQ subsystem # CONFIG_GENERIC_IRQ_LEGACY=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_PENDING_IRQ=y CONFIG_GENERIC_IRQ_INJECTION=y CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_SIM=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y CONFIG_IRQ_MSI_IOMMU=y CONFIG_GENERIC_IRQ_DEBUGFS=y # end of IRQ subsystem CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_LEGACY_TIMER_TICK=y CONFIG_TIME_KUNIT_TEST=m CONFIG_CONTEXT_TRACKING=y CONFIG_CONTEXT_TRACKING_IDLE=y CONFIG_BPF=y # # BPF subsystem # CONFIG_BPF_SYSCALL=y CONFIG_BPF_UNPRIV_DEFAULT_OFF=y CONFIG_USERMODE_DRIVER=y # end of BPF subsystem CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_PREEMPT_COUNT=y CONFIG_SCHED_CORE=y # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_PSI=y CONFIG_PSI_DEFAULT_DISABLED=y # end of CPU/Task time and stats accounting CONFIG_CPU_ISOLATION=y # # RCU Subsystem # CONFIG_TREE_RCU=y CONFIG_RCU_EXPERT=y CONFIG_SRCU=y CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y CONFIG_FORCE_TASKS_RCU=y CONFIG_TASKS_RCU=y CONFIG_FORCE_TASKS_RUDE_RCU=y CONFIG_TASKS_RUDE_RCU=y CONFIG_FORCE_TASKS_TRACE_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y CONFIG_RCU_FANOUT=64 CONFIG_RCU_FANOUT_LEAF=16 CONFIG_RCU_NOCB_CPU=y CONFIG_RCU_NOCB_CPU_DEFAULT_ALL=y CONFIG_TASKS_TRACE_RCU_READ_MB=y # end of RCU Subsystem CONFIG_BUILD_BIN2C=y CONFIG_IKCONFIG=m CONFIG_IKCONFIG_PROC=y CONFIG_IKHEADERS=m CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_PRINTK_INDEX=y CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y # # Scheduler features # CONFIG_UCLAMP_TASK=y CONFIG_UCLAMP_BUCKETS_COUNT=5 # end of Scheduler features CONFIG_CC_HAS_INT128=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_CGROUP_FAVOR_DYNMODS=y CONFIG_MEMCG=y CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y CONFIG_RT_GROUP_SCHED=y CONFIG_UCLAMP_TASK_GROUP=y CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_RDMA=y CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_HUGETLB=y CONFIG_CPUSETS=y CONFIG_PROC_PID_CPUSET=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_BPF=y CONFIG_CGROUP_MISC=y CONFIG_CGROUP_DEBUG=y CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y CONFIG_NET_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_SCHED_AUTOGROUP=y CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y CONFIG_RD_BZIP2=y CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y CONFIG_RD_LZ4=y CONFIG_RD_ZSTD=y CONFIG_BOOT_CONFIG=y CONFIG_BOOT_CONFIG_EMBED=y CONFIG_BOOT_CONFIG_EMBED_FILE="" CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_SYSCTL_ARCH_UNALIGN_NO_WARN=y CONFIG_EXPERT=y CONFIG_MULTIUSER=y CONFIG_SGETMASK_SYSCALL=y CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KCMP=y CONFIG_EMBEDDED=y CONFIG_PC104=y # # Kernel Performance Events And Counters # # end of Kernel Performance Events And Counters CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y # end of General setup CONFIG_PGTABLE_LEVELS=3 # # Processor type and features # CONFIG_IA64=y CONFIG_64BIT=y CONFIG_MMU=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_DMI=y CONFIG_EFI=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_IA64_UNCACHED_ALLOCATOR=y CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_AUDIT_ARCH=y CONFIG_ITANIUM=y # CONFIG_MCKINLEY is not set # CONFIG_IA64_PAGE_SIZE_4KB is not set # CONFIG_IA64_PAGE_SIZE_8KB is not set CONFIG_IA64_PAGE_SIZE_16KB=y # CONFIG_HZ_100 is not set CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 CONFIG_IA64_BRL_EMU=y CONFIG_IA64_L1_CACHE_SHIFT=6 CONFIG_IA64_SGI_UV=y CONFIG_IA64_HP_SBA_IOMMU=y CONFIG_IA64_CYCLONE=y CONFIG_ARCH_FORCE_MAX_ORDER=17 CONFIG_SMP=y CONFIG_NR_CPUS=4096 CONFIG_HOTPLUG_CPU=y CONFIG_SCHED_SMT=y CONFIG_PERMIT_BSP_REMOVE=y CONFIG_FORCE_CPEI_RETARGET=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_NUMA=y CONFIG_NODES_SHIFT=10 CONFIG_HAVE_ARCH_NODEDATA_EXTENSION=y CONFIG_HAVE_MEMORYLESS_NODES=y CONFIG_ARCH_PROC_KCORE_TEXT=y CONFIG_IA64_MCA_RECOVERY=y CONFIG_IA64_PALINFO=m CONFIG_IA64_MC_ERR_INJECT=m CONFIG_IA64_ESI=y CONFIG_IA64_HP_AML_NFW=y CONFIG_KEXEC=y CONFIG_CRASH_DUMP=y # end of Processor type and features # # Power management and ACPI options # CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_PM_ADVANCED_DEBUG=y CONFIG_DPM_WATCHDOG=y CONFIG_DPM_WATCHDOG_TIMEOUT=120 CONFIG_PM_CLK=y CONFIG_PM_GENERIC_DOMAINS=y CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y CONFIG_PM_GENERIC_DOMAINS_OF=y CONFIG_ENERGY_MODEL=y CONFIG_ARCH_SUPPORTS_ACPI=y CONFIG_ACPI=y CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y CONFIG_ACPI_TABLE_LIB=y CONFIG_ACPI_DEBUGGER=y CONFIG_ACPI_DEBUGGER_USER=m CONFIG_ACPI_SPCR_TABLE=y CONFIG_ACPI_EC_DEBUGFS=m CONFIG_ACPI_AC=m CONFIG_ACPI_BATTERY=m CONFIG_ACPI_BUTTON=m CONFIG_ACPI_TINY_POWER_BUTTON=m CONFIG_ACPI_TINY_POWER_BUTTON_SIGNAL=38 CONFIG_ACPI_VIDEO=m CONFIG_ACPI_FAN=m CONFIG_ACPI_DOCK=y CONFIG_ACPI_CPU_FREQ_PSS=y CONFIG_ACPI_PROCESSOR_CSTATE=y CONFIG_ACPI_PROCESSOR_IDLE=y CONFIG_ACPI_PROCESSOR=m CONFIG_ACPI_IPMI=m CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_THERMAL=m CONFIG_ACPI_PLATFORM_PROFILE=m CONFIG_ACPI_DEBUG=y CONFIG_ACPI_PCI_SLOT=y CONFIG_ACPI_CONTAINER=y CONFIG_ACPI_HOTPLUG_MEMORY=y CONFIG_ACPI_HED=m CONFIG_ACPI_CUSTOM_METHOD=m CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y CONFIG_ACPI_NUMA=y CONFIG_ACPI_HMAT=y CONFIG_ACPI_WATCHDOG=y CONFIG_ACPI_CONFIGFS=m CONFIG_ACPI_PFRUT=m CONFIG_ACPI_PCC=y CONFIG_PMIC_OPREGION=y # # CPU Frequency scaling # # # CPU Frequency scaling # CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_GOV_ATTR_SET=y CONFIG_CPU_FREQ_GOV_COMMON=y CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=m CONFIG_CPU_FREQ_GOV_USERSPACE=m CONFIG_CPU_FREQ_GOV_ONDEMAND=m CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # # CPU frequency scaling drivers # CONFIG_CPUFREQ_DT=m CONFIG_CPUFREQ_DT_PLATDEV=y CONFIG_IA64_ACPI_CPUFREQ=m CONFIG_QORIQ_CPUFREQ=m # end of CPU Frequency scaling # end of CPU Frequency scaling # end of Power management and ACPI options CONFIG_MSPEC=m # # General architecture-dependent options # CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_KPROBES=y CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y CONFIG_KRETPROBES=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_FUNCTION_DESCRIPTORS=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_ARCH_TASK_STRUCT_ON_STACK=y CONFIG_ARCH_TASK_STRUCT_ALLOCATOR=y CONFIG_ARCH_THREAD_STACK_ALLOCATOR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_LTO_NONE=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ISA_BUS_API=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_LOCK_EVENT_COUNTS=y # # GCOV-based kernel profiling # CONFIG_GCOV_KERNEL=y # end of GCOV-based kernel profiling # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODULE_UNLOAD_TAINT_TRACKING=y CONFIG_MODVERSIONS=y CONFIG_ASM_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y CONFIG_MODULE_SIG_FORCE=y CONFIG_MODULE_SIG_ALL=y CONFIG_MODULE_SIG_SHA1=y # CONFIG_MODULE_SIG_SHA224 is not set # CONFIG_MODULE_SIG_SHA256 is not set # CONFIG_MODULE_SIG_SHA384 is not set # CONFIG_MODULE_SIG_SHA512 is not set CONFIG_MODULE_SIG_HASH="sha1" CONFIG_MODULE_COMPRESS_NONE=y # CONFIG_MODULE_COMPRESS_GZIP is not set # CONFIG_MODULE_COMPRESS_XZ is not set # CONFIG_MODULE_COMPRESS_ZSTD is not set CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_BLOCK=y CONFIG_BLOCK_LEGACY_AUTOLOAD=y CONFIG_BLK_RQ_ALLOC_TIME=y CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_ICQ=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BLK_DEV_INTEGRITY_T10=m CONFIG_BLK_DEV_ZONED=y CONFIG_BLK_DEV_THROTTLING=y CONFIG_BLK_DEV_THROTTLING_LOW=y CONFIG_BLK_WBT=y CONFIG_BLK_WBT_MQ=y CONFIG_BLK_CGROUP_IOLATENCY=y CONFIG_BLK_CGROUP_FC_APPID=y CONFIG_BLK_CGROUP_IOCOST=y CONFIG_BLK_CGROUP_IOPRIO=y CONFIG_BLK_DEBUG_FS=y CONFIG_BLK_DEBUG_FS_ZONED=y CONFIG_BLK_SED_OPAL=y CONFIG_BLK_INLINE_ENCRYPTION=y CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y # # Partition Types # CONFIG_PARTITION_ADVANCED=y CONFIG_ACORN_PARTITION=y CONFIG_ACORN_PARTITION_CUMANA=y CONFIG_ACORN_PARTITION_EESOX=y CONFIG_ACORN_PARTITION_ICS=y CONFIG_ACORN_PARTITION_ADFS=y CONFIG_ACORN_PARTITION_POWERTEC=y CONFIG_ACORN_PARTITION_RISCIX=y CONFIG_AIX_PARTITION=y CONFIG_OSF_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_ATARI_PARTITION=y CONFIG_MAC_PARTITION=y CONFIG_MSDOS_PARTITION=y CONFIG_BSD_DISKLABEL=y CONFIG_MINIX_SUBPARTITION=y CONFIG_SOLARIS_X86_PARTITION=y CONFIG_UNIXWARE_DISKLABEL=y CONFIG_LDM_PARTITION=y CONFIG_LDM_DEBUG=y CONFIG_SGI_PARTITION=y CONFIG_ULTRIX_PARTITION=y CONFIG_SUN_PARTITION=y CONFIG_KARMA_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_SYSV68_PARTITION=y CONFIG_CMDLINE_PARTITION=y # end of Partition Types CONFIG_BLK_MQ_PCI=y CONFIG_BLK_MQ_VIRTIO=y CONFIG_BLK_MQ_RDMA=y CONFIG_BLK_PM=y CONFIG_BLOCK_HOLDER_DEPRECATED=y CONFIG_BLK_MQ_STACKING=y # # IO Schedulers # CONFIG_MQ_IOSCHED_DEADLINE=y CONFIG_MQ_IOSCHED_KYBER=m CONFIG_IOSCHED_BFQ=m CONFIG_BFQ_GROUP_IOSCHED=y CONFIG_BFQ_CGROUP_DEBUG=y # end of IO Schedulers CONFIG_PADATA=y CONFIG_ASN1=y CONFIG_UNINLINE_SPIN_UNLOCK=y CONFIG_FREEZER=y # # Executable file formats # CONFIG_BINFMT_ELF=y CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y CONFIG_ELFCORE=y CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y CONFIG_BINFMT_SCRIPT=m CONFIG_BINFMT_MISC=m CONFIG_COREDUMP=y # end of Executable file formats # # Memory Management options # CONFIG_ZPOOL=y CONFIG_SWAP=y CONFIG_ZSWAP=y CONFIG_ZSWAP_DEFAULT_ON=y # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y # CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set # CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" CONFIG_ZBUD=y CONFIG_Z3FOLD=m CONFIG_ZSMALLOC=m CONFIG_ZSMALLOC_STAT=y # # SLAB allocator options # # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set CONFIG_SLAB_MERGE_DEFAULT=y CONFIG_SLAB_FREELIST_RANDOM=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLUB_STATS=y CONFIG_SLUB_CPU_PARTIAL=y # end of SLAB allocator options CONFIG_SHUFFLE_PAGE_ALLOCATOR=y CONFIG_COMPAT_BRK=y CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_NUMA_KEEP_MEMINFO=y CONFIG_MEMORY_ISOLATION=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y CONFIG_MEMORY_HOTREMOVE=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MEMORY_BALLOON=y CONFIG_BALLOON_COMPACTION=y CONFIG_COMPACTION=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 CONFIG_PAGE_REPORTING=y CONFIG_MIGRATION=y CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_MMU_NOTIFIER=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_USE_PERCPU_NUMA_NODE_ID=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_FRONTSWAP=y CONFIG_CMA=y CONFIG_CMA_DEBUG=y CONFIG_CMA_DEBUGFS=y CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=19 CONFIG_DEFERRED_STRUCT_PAGE_INIT=y CONFIG_PAGE_IDLE_FLAG=y CONFIG_IDLE_PAGE_TRACKING=y CONFIG_ZONE_DMA32=y CONFIG_HMM_MIRROR=y CONFIG_GET_FREE_REGION=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_PERCPU_STATS=y CONFIG_GUP_TEST=y CONFIG_ANON_VMA_NAME=y CONFIG_USERFAULTFD=y CONFIG_LRU_GEN=y CONFIG_LRU_GEN_ENABLED=y CONFIG_LRU_GEN_STATS=y # # Data Access Monitoring # CONFIG_DAMON=y CONFIG_DAMON_VADDR=y CONFIG_DAMON_PADDR=y CONFIG_DAMON_SYSFS=y CONFIG_DAMON_DBGFS=y CONFIG_DAMON_RECLAIM=y CONFIG_DAMON_LRU_SORT=y # end of Data Access Monitoring # end of Memory Management options CONFIG_NET=y CONFIG_NET_INGRESS=y CONFIG_NET_EGRESS=y CONFIG_NET_REDIRECT=y CONFIG_SKB_EXTENSIONS=y # # Networking options # CONFIG_PACKET=m CONFIG_PACKET_DIAG=m CONFIG_UNIX=m CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y CONFIG_UNIX_DIAG=m CONFIG_TLS=m CONFIG_TLS_DEVICE=y CONFIG_TLS_TOE=y CONFIG_XFRM=y CONFIG_XFRM_OFFLOAD=y CONFIG_XFRM_ALGO=m CONFIG_XFRM_USER=m CONFIG_XFRM_INTERFACE=m CONFIG_XFRM_SUB_POLICY=y CONFIG_XFRM_MIGRATE=y CONFIG_XFRM_STATISTICS=y CONFIG_XFRM_AH=m CONFIG_XFRM_ESP=m CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=m CONFIG_NET_KEY_MIGRATE=y CONFIG_XFRM_ESPINTCP=y CONFIG_SMC=m CONFIG_SMC_DIAG=m CONFIG_XDP_SOCKETS=y CONFIG_XDP_SOCKETS_DIAG=m CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_FIB_TRIE_STATS=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_ROUTE_CLASSID=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IP_TUNNEL=m CONFIG_NET_IPGRE=m CONFIG_NET_IPGRE_BROADCAST=y CONFIG_IP_MROUTE_COMMON=y CONFIG_IP_MROUTE=y CONFIG_IP_MROUTE_MULTIPLE_TABLES=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=m CONFIG_NET_UDP_TUNNEL=m CONFIG_NET_FOU=m CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_ESP_OFFLOAD=m CONFIG_INET_ESPINTCP=y CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_TUNNEL=m CONFIG_INET_TUNNEL=m CONFIG_INET_DIAG=m CONFIG_INET_TCP_DIAG=m CONFIG_INET_UDP_DIAG=m CONFIG_INET_RAW_DIAG=m CONFIG_INET_DIAG_DESTROY=y CONFIG_TCP_CONG_ADVANCED=y CONFIG_TCP_CONG_BIC=m CONFIG_TCP_CONG_CUBIC=m CONFIG_TCP_CONG_WESTWOOD=m CONFIG_TCP_CONG_HTCP=m CONFIG_TCP_CONG_HSTCP=m CONFIG_TCP_CONG_HYBLA=m CONFIG_TCP_CONG_VEGAS=m CONFIG_TCP_CONG_NV=m CONFIG_TCP_CONG_SCALABLE=m CONFIG_TCP_CONG_LP=m CONFIG_TCP_CONG_VENO=m CONFIG_TCP_CONG_YEAH=m CONFIG_TCP_CONG_ILLINOIS=m CONFIG_TCP_CONG_DCTCP=m CONFIG_TCP_CONG_CDG=m CONFIG_TCP_CONG_BBR=m CONFIG_DEFAULT_RENO=y CONFIG_DEFAULT_TCP_CONG="reno" CONFIG_TCP_MD5SIG=y CONFIG_IPV6=m CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_ESP_OFFLOAD=m CONFIG_INET6_ESPINTCP=y CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m CONFIG_IPV6_ILA=m CONFIG_INET6_XFRM_TUNNEL=m CONFIG_INET6_TUNNEL=m CONFIG_IPV6_VTI=m CONFIG_IPV6_SIT=m CONFIG_IPV6_SIT_6RD=y CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=m CONFIG_IPV6_GRE=m CONFIG_IPV6_FOU=m CONFIG_IPV6_FOU_TUNNEL=m CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y CONFIG_IPV6_MROUTE=y CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y CONFIG_IPV6_PIMSM_V2=y CONFIG_IPV6_SEG6_LWTUNNEL=y CONFIG_IPV6_SEG6_HMAC=y CONFIG_IPV6_RPL_LWTUNNEL=y CONFIG_IPV6_IOAM6_LWTUNNEL=y CONFIG_NETLABEL=y CONFIG_MPTCP=y CONFIG_INET_MPTCP_DIAG=m CONFIG_MPTCP_KUNIT_TEST=m CONFIG_NETWORK_SECMARK=y CONFIG_NET_PTP_CLASSIFY=y CONFIG_NETWORK_PHY_TIMESTAMPING=y CONFIG_NETFILTER=y CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=m # # Core Netfilter Configuration # CONFIG_NETFILTER_INGRESS=y CONFIG_NETFILTER_EGRESS=y CONFIG_NETFILTER_SKIP_EGRESS=y CONFIG_NETFILTER_NETLINK=m CONFIG_NETFILTER_FAMILY_BRIDGE=y CONFIG_NETFILTER_FAMILY_ARP=y CONFIG_NETFILTER_NETLINK_HOOK=m CONFIG_NETFILTER_NETLINK_ACCT=m CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m CONFIG_NETFILTER_NETLINK_OSF=m CONFIG_NF_CONNTRACK=m CONFIG_NF_LOG_SYSLOG=m CONFIG_NETFILTER_CONNCOUNT=m CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y CONFIG_NF_CONNTRACK_PROCFS=y CONFIG_NF_CONNTRACK_EVENTS=y CONFIG_NF_CONNTRACK_TIMEOUT=y CONFIG_NF_CONNTRACK_TIMESTAMP=y CONFIG_NF_CONNTRACK_LABELS=y CONFIG_NF_CT_PROTO_DCCP=y CONFIG_NF_CT_PROTO_GRE=y CONFIG_NF_CT_PROTO_SCTP=y CONFIG_NF_CT_PROTO_UDPLITE=y CONFIG_NF_CONNTRACK_AMANDA=m CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m CONFIG_NF_CONNTRACK_IRC=m CONFIG_NF_CONNTRACK_BROADCAST=m CONFIG_NF_CONNTRACK_NETBIOS_NS=m CONFIG_NF_CONNTRACK_SNMP=m CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m CONFIG_NF_CT_NETLINK_TIMEOUT=m CONFIG_NF_CT_NETLINK_HELPER=m CONFIG_NETFILTER_NETLINK_GLUE_CT=y CONFIG_NF_NAT=m CONFIG_NF_NAT_AMANDA=m CONFIG_NF_NAT_FTP=m CONFIG_NF_NAT_IRC=m CONFIG_NF_NAT_SIP=m CONFIG_NF_NAT_TFTP=m CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y CONFIG_NETFILTER_SYNPROXY=m CONFIG_NF_TABLES=m CONFIG_NF_TABLES_INET=y CONFIG_NF_TABLES_NETDEV=y CONFIG_NFT_NUMGEN=m CONFIG_NFT_CT=m CONFIG_NFT_FLOW_OFFLOAD=m CONFIG_NFT_CONNLIMIT=m CONFIG_NFT_LOG=m CONFIG_NFT_LIMIT=m CONFIG_NFT_MASQ=m CONFIG_NFT_REDIR=m CONFIG_NFT_NAT=m CONFIG_NFT_TUNNEL=m # CONFIG_NFT_OBJREF is not set CONFIG_NFT_QUEUE=m CONFIG_NFT_QUOTA=m CONFIG_NFT_REJECT=m CONFIG_NFT_REJECT_INET=m CONFIG_NFT_COMPAT=m CONFIG_NFT_HASH=m CONFIG_NFT_FIB=m CONFIG_NFT_FIB_INET=m CONFIG_NFT_XFRM=m CONFIG_NFT_SOCKET=m CONFIG_NFT_OSF=m CONFIG_NFT_TPROXY=m CONFIG_NFT_SYNPROXY=m CONFIG_NF_DUP_NETDEV=m CONFIG_NFT_DUP_NETDEV=m CONFIG_NFT_FWD_NETDEV=m CONFIG_NFT_FIB_NETDEV=m CONFIG_NFT_REJECT_NETDEV=m CONFIG_NF_FLOW_TABLE_INET=m CONFIG_NF_FLOW_TABLE=m CONFIG_NF_FLOW_TABLE_PROCFS=y CONFIG_NETFILTER_XTABLES=m # # Xtables combined modules # CONFIG_NETFILTER_XT_MARK=m CONFIG_NETFILTER_XT_CONNMARK=m CONFIG_NETFILTER_XT_SET=m # # Xtables targets # CONFIG_NETFILTER_XT_TARGET_AUDIT=m CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_CT=m CONFIG_NETFILTER_XT_TARGET_DSCP=m CONFIG_NETFILTER_XT_TARGET_HL=m CONFIG_NETFILTER_XT_TARGET_HMARK=m CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m CONFIG_NETFILTER_XT_TARGET_LED=m CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_NAT=m CONFIG_NETFILTER_XT_TARGET_NETMAP=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NOTRACK=m CONFIG_NETFILTER_XT_TARGET_RATEEST=m CONFIG_NETFILTER_XT_TARGET_REDIRECT=m CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m # # Xtables matches # CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CGROUP=m CONFIG_NETFILTER_XT_MATCH_CLUSTER=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_CPU=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ECN=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m CONFIG_NETFILTER_XT_MATCH_HL=m CONFIG_NETFILTER_XT_MATCH_IPCOMP=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_IPVS=m CONFIG_NETFILTER_XT_MATCH_L2TP=m CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_NFACCT=m CONFIG_NETFILTER_XT_MATCH_OSF=m CONFIG_NETFILTER_XT_MATCH_OWNER=m CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_RECENT=m CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_SOCKET=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m # end of Core Netfilter Configuration CONFIG_IP_SET=m CONFIG_IP_SET_MAX=256 CONFIG_IP_SET_BITMAP_IP=m CONFIG_IP_SET_BITMAP_IPMAC=m CONFIG_IP_SET_BITMAP_PORT=m CONFIG_IP_SET_HASH_IP=m CONFIG_IP_SET_HASH_IPMARK=m CONFIG_IP_SET_HASH_IPPORT=m CONFIG_IP_SET_HASH_IPPORTIP=m CONFIG_IP_SET_HASH_IPPORTNET=m CONFIG_IP_SET_HASH_IPMAC=m CONFIG_IP_SET_HASH_MAC=m CONFIG_IP_SET_HASH_NETPORTNET=m CONFIG_IP_SET_HASH_NET=m CONFIG_IP_SET_HASH_NETNET=m CONFIG_IP_SET_HASH_NETPORT=m CONFIG_IP_SET_HASH_NETIFACE=m CONFIG_IP_SET_LIST_SET=m CONFIG_IP_VS=m CONFIG_IP_VS_IPV6=y CONFIG_IP_VS_DEBUG=y CONFIG_IP_VS_TAB_BITS=12 # # IPVS transport protocol load balancing support # CONFIG_IP_VS_PROTO_TCP=y CONFIG_IP_VS_PROTO_UDP=y CONFIG_IP_VS_PROTO_AH_ESP=y CONFIG_IP_VS_PROTO_ESP=y CONFIG_IP_VS_PROTO_AH=y CONFIG_IP_VS_PROTO_SCTP=y # # IPVS scheduler # CONFIG_IP_VS_RR=m CONFIG_IP_VS_WRR=m CONFIG_IP_VS_LC=m CONFIG_IP_VS_WLC=m CONFIG_IP_VS_FO=m CONFIG_IP_VS_OVF=m CONFIG_IP_VS_LBLC=m CONFIG_IP_VS_LBLCR=m CONFIG_IP_VS_DH=m CONFIG_IP_VS_SH=m CONFIG_IP_VS_MH=m CONFIG_IP_VS_SED=m CONFIG_IP_VS_NQ=m CONFIG_IP_VS_TWOS=m # # IPVS SH scheduler # CONFIG_IP_VS_SH_TAB_BITS=8 # # IPVS MH scheduler # CONFIG_IP_VS_MH_TAB_INDEX=12 # # IPVS application helper # CONFIG_IP_VS_FTP=m CONFIG_IP_VS_NFCT=y CONFIG_IP_VS_PE_SIP=m # # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_SOCKET_IPV4=m CONFIG_NF_TPROXY_IPV4=m CONFIG_NF_TABLES_IPV4=y CONFIG_NFT_REJECT_IPV4=m CONFIG_NFT_DUP_IPV4=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y CONFIG_NF_DUP_IPV4=m CONFIG_NF_LOG_ARP=m CONFIG_NF_LOG_IPV4=m CONFIG_NF_REJECT_IPV4=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_SYNPROXY=m CONFIG_IP_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m CONFIG_IP_NF_TARGET_NETMAP=m CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_SECURITY=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # CONFIG_NF_SOCKET_IPV6=m CONFIG_NF_TPROXY_IPV6=m CONFIG_NF_TABLES_IPV6=y CONFIG_NFT_REJECT_IPV6=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m CONFIG_NF_DUP_IPV6=m CONFIG_NF_REJECT_IPV6=m CONFIG_NF_LOG_IPV6=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_MATCH_SRH=m CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_TARGET_SYNPROXY=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m CONFIG_IP6_NF_SECURITY=m CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m # end of IPv6: Netfilter Configuration CONFIG_NF_DEFRAG_IPV6=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m CONFIG_BRIDGE_EBT_T_NAT=m CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m CONFIG_BRIDGE_EBT_IP=m CONFIG_BRIDGE_EBT_IP6=m CONFIG_BRIDGE_EBT_LIMIT=m CONFIG_BRIDGE_EBT_MARK=m CONFIG_BRIDGE_EBT_PKTTYPE=m CONFIG_BRIDGE_EBT_STP=m CONFIG_BRIDGE_EBT_VLAN=m CONFIG_BRIDGE_EBT_ARPREPLY=m CONFIG_BRIDGE_EBT_DNAT=m CONFIG_BRIDGE_EBT_MARK_T=m CONFIG_BRIDGE_EBT_REDIRECT=m CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_NFLOG=m CONFIG_BPFILTER=y CONFIG_IP_DCCP=m CONFIG_INET_DCCP_DIAG=m # # DCCP CCIDs Configuration # CONFIG_IP_DCCP_CCID2_DEBUG=y CONFIG_IP_DCCP_CCID3=y CONFIG_IP_DCCP_CCID3_DEBUG=y CONFIG_IP_DCCP_TFRC_LIB=y CONFIG_IP_DCCP_TFRC_DEBUG=y # end of DCCP CCIDs Configuration # # DCCP Kernel Hacking # CONFIG_IP_DCCP_DEBUG=y # end of DCCP Kernel Hacking CONFIG_IP_SCTP=m CONFIG_SCTP_DBG_OBJCNT=y CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set # CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set CONFIG_SCTP_COOKIE_HMAC_MD5=y CONFIG_SCTP_COOKIE_HMAC_SHA1=y CONFIG_INET_SCTP_DIAG=m CONFIG_RDS=m CONFIG_RDS_RDMA=m CONFIG_RDS_TCP=m CONFIG_RDS_DEBUG=y CONFIG_TIPC=m CONFIG_TIPC_MEDIA_IB=y CONFIG_TIPC_MEDIA_UDP=y CONFIG_TIPC_CRYPTO=y CONFIG_TIPC_DIAG=m CONFIG_ATM=m CONFIG_ATM_CLIP=m CONFIG_ATM_CLIP_NO_ICMP=y CONFIG_ATM_LANE=m CONFIG_ATM_MPOA=m CONFIG_ATM_BR2684=m CONFIG_ATM_BR2684_IPFILTER=y CONFIG_L2TP=m CONFIG_L2TP_DEBUGFS=m CONFIG_L2TP_V3=y CONFIG_L2TP_IP=m CONFIG_L2TP_ETH=m CONFIG_STP=m CONFIG_GARP=m CONFIG_MRP=m CONFIG_BRIDGE=m CONFIG_BRIDGE_IGMP_SNOOPING=y CONFIG_BRIDGE_VLAN_FILTERING=y CONFIG_BRIDGE_MRP=y CONFIG_BRIDGE_CFM=y CONFIG_NET_DSA=m CONFIG_NET_DSA_TAG_AR9331=m CONFIG_NET_DSA_TAG_BRCM_COMMON=m CONFIG_NET_DSA_TAG_BRCM=m CONFIG_NET_DSA_TAG_BRCM_LEGACY=m CONFIG_NET_DSA_TAG_BRCM_PREPEND=m CONFIG_NET_DSA_TAG_HELLCREEK=m CONFIG_NET_DSA_TAG_GSWIP=m CONFIG_NET_DSA_TAG_DSA_COMMON=m CONFIG_NET_DSA_TAG_DSA=m CONFIG_NET_DSA_TAG_EDSA=m CONFIG_NET_DSA_TAG_MTK=m CONFIG_NET_DSA_TAG_KSZ=m CONFIG_NET_DSA_TAG_OCELOT=m CONFIG_NET_DSA_TAG_OCELOT_8021Q=m CONFIG_NET_DSA_TAG_QCA=m CONFIG_NET_DSA_TAG_RTL4_A=m CONFIG_NET_DSA_TAG_RTL8_4=m CONFIG_NET_DSA_TAG_RZN1_A5PSW=m CONFIG_NET_DSA_TAG_LAN9303=m CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m CONFIG_NET_DSA_TAG_XRS700X=m CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y CONFIG_VLAN_8021Q_MVRP=y CONFIG_LLC=m CONFIG_LLC2=m CONFIG_ATALK=m CONFIG_DEV_APPLETALK=m CONFIG_IPDDP=m CONFIG_IPDDP_ENCAP=y CONFIG_X25=m CONFIG_LAPB=m CONFIG_PHONET=m CONFIG_6LOWPAN=m CONFIG_6LOWPAN_DEBUGFS=y CONFIG_6LOWPAN_NHC=m CONFIG_6LOWPAN_NHC_DEST=m CONFIG_6LOWPAN_NHC_FRAGMENT=m CONFIG_6LOWPAN_NHC_HOP=m CONFIG_6LOWPAN_NHC_IPV6=m CONFIG_6LOWPAN_NHC_MOBILITY=m CONFIG_6LOWPAN_NHC_ROUTING=m CONFIG_6LOWPAN_NHC_UDP=m CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m CONFIG_6LOWPAN_GHC_UDP=m CONFIG_6LOWPAN_GHC_ICMPV6=m CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m CONFIG_IEEE802154=m CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y CONFIG_IEEE802154_SOCKET=m CONFIG_IEEE802154_6LOWPAN=m CONFIG_MAC802154=m CONFIG_NET_SCHED=y # # Queueing/Scheduling # CONFIG_NET_SCH_CBQ=m CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_ATM=m CONFIG_NET_SCH_PRIO=m CONFIG_NET_SCH_MULTIQ=m CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFB=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m CONFIG_NET_SCH_TBF=m CONFIG_NET_SCH_CBS=m CONFIG_NET_SCH_ETF=m CONFIG_NET_SCH_TAPRIO=m CONFIG_NET_SCH_GRED=m CONFIG_NET_SCH_DSMARK=m CONFIG_NET_SCH_NETEM=m CONFIG_NET_SCH_DRR=m CONFIG_NET_SCH_MQPRIO=m CONFIG_NET_SCH_SKBPRIO=m CONFIG_NET_SCH_CHOKE=m CONFIG_NET_SCH_QFQ=m CONFIG_NET_SCH_CODEL=m CONFIG_NET_SCH_FQ_CODEL=m CONFIG_NET_SCH_CAKE=m CONFIG_NET_SCH_FQ=m CONFIG_NET_SCH_HHF=m CONFIG_NET_SCH_PIE=m CONFIG_NET_SCH_FQ_PIE=m CONFIG_NET_SCH_INGRESS=m CONFIG_NET_SCH_PLUG=m CONFIG_NET_SCH_ETS=m CONFIG_NET_SCH_DEFAULT=y # CONFIG_DEFAULT_FQ is not set # CONFIG_DEFAULT_CODEL is not set # CONFIG_DEFAULT_FQ_CODEL is not set # CONFIG_DEFAULT_FQ_PIE is not set # CONFIG_DEFAULT_SFQ is not set CONFIG_DEFAULT_PFIFO_FAST=y CONFIG_DEFAULT_NET_SCH="pfifo_fast" # # Classification # CONFIG_NET_CLS=y CONFIG_NET_CLS_BASIC=m CONFIG_NET_CLS_TCINDEX=m CONFIG_NET_CLS_ROUTE4=m CONFIG_NET_CLS_FW=m CONFIG_NET_CLS_U32=m CONFIG_CLS_U32_PERF=y CONFIG_CLS_U32_MARK=y CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m CONFIG_NET_CLS_FLOW=m CONFIG_NET_CLS_CGROUP=m CONFIG_NET_CLS_BPF=m CONFIG_NET_CLS_FLOWER=m CONFIG_NET_CLS_MATCHALL=m CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_STACK=32 CONFIG_NET_EMATCH_CMP=m CONFIG_NET_EMATCH_NBYTE=m CONFIG_NET_EMATCH_U32=m CONFIG_NET_EMATCH_META=m CONFIG_NET_EMATCH_TEXT=m CONFIG_NET_EMATCH_CANID=m CONFIG_NET_EMATCH_IPSET=m CONFIG_NET_EMATCH_IPT=m CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=m CONFIG_NET_ACT_GACT=m CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m CONFIG_NET_ACT_SAMPLE=m CONFIG_NET_ACT_IPT=m CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m CONFIG_NET_ACT_SKBEDIT=m CONFIG_NET_ACT_CSUM=m CONFIG_NET_ACT_MPLS=m CONFIG_NET_ACT_VLAN=m CONFIG_NET_ACT_BPF=m CONFIG_NET_ACT_CONNMARK=m CONFIG_NET_ACT_CTINFO=m CONFIG_NET_ACT_SKBMOD=m CONFIG_NET_ACT_IFE=m CONFIG_NET_ACT_TUNNEL_KEY=m CONFIG_NET_ACT_CT=m CONFIG_NET_ACT_GATE=m CONFIG_NET_IFE_SKBMARK=m CONFIG_NET_IFE_SKBPRIO=m CONFIG_NET_IFE_SKBTCINDEX=m CONFIG_NET_TC_SKB_EXT=y CONFIG_NET_SCH_FIFO=y CONFIG_DCB=y CONFIG_DNS_RESOLVER=m CONFIG_BATMAN_ADV=m CONFIG_BATMAN_ADV_BATMAN_V=y CONFIG_BATMAN_ADV_BLA=y CONFIG_BATMAN_ADV_DAT=y CONFIG_BATMAN_ADV_NC=y CONFIG_BATMAN_ADV_MCAST=y CONFIG_BATMAN_ADV_DEBUG=y CONFIG_OPENVSWITCH=m CONFIG_OPENVSWITCH_GRE=m CONFIG_OPENVSWITCH_VXLAN=m CONFIG_OPENVSWITCH_GENEVE=m CONFIG_VSOCKETS=m CONFIG_VSOCKETS_DIAG=m CONFIG_VSOCKETS_LOOPBACK=m CONFIG_VIRTIO_VSOCKETS=m CONFIG_VIRTIO_VSOCKETS_COMMON=m CONFIG_NETLINK_DIAG=m CONFIG_MPLS=y CONFIG_NET_MPLS_GSO=m CONFIG_MPLS_ROUTING=m CONFIG_MPLS_IPTUNNEL=m CONFIG_NET_NSH=m CONFIG_HSR=m CONFIG_NET_SWITCHDEV=y CONFIG_NET_L3_MASTER_DEV=y CONFIG_QRTR=m CONFIG_QRTR_SMD=m CONFIG_QRTR_TUN=m CONFIG_QRTR_MHI=m CONFIG_NET_NCSI=y CONFIG_NCSI_OEM_CMD_GET_MAC=y CONFIG_NCSI_OEM_CMD_KEEP_PHY=y CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y CONFIG_CGROUP_NET_PRIO=y CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y CONFIG_BPF_STREAM_PARSER=y CONFIG_NET_FLOW_LIMIT=y # # Network testing # CONFIG_NET_PKTGEN=m # end of Network testing # end of Networking options CONFIG_HAMRADIO=y # # Packet Radio protocols # CONFIG_AX25=m CONFIG_AX25_DAMA_SLAVE=y CONFIG_NETROM=m CONFIG_ROSE=m # # AX.25 network device drivers # CONFIG_MKISS=m CONFIG_6PACK=m CONFIG_BPQETHER=m CONFIG_BAYCOM_SER_FDX=m CONFIG_BAYCOM_SER_HDX=m CONFIG_BAYCOM_PAR=m CONFIG_YAM=m # end of AX.25 network device drivers CONFIG_CAN=m CONFIG_CAN_RAW=m CONFIG_CAN_BCM=m CONFIG_CAN_GW=m CONFIG_CAN_J1939=m CONFIG_CAN_ISOTP=m CONFIG_BT=m CONFIG_BT_BREDR=y CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y CONFIG_BT_CMTP=m CONFIG_BT_HIDP=m CONFIG_BT_HS=y CONFIG_BT_LE=y CONFIG_BT_6LOWPAN=m CONFIG_BT_LEDS=y CONFIG_BT_MSFTEXT=y CONFIG_BT_AOSPEXT=y CONFIG_BT_DEBUGFS=y CONFIG_BT_SELFTEST=y CONFIG_BT_SELFTEST_ECDH=y CONFIG_BT_SELFTEST_SMP=y # # Bluetooth device drivers # CONFIG_BT_INTEL=m CONFIG_BT_BCM=m CONFIG_BT_RTL=m CONFIG_BT_QCA=m CONFIG_BT_MTK=m CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y CONFIG_BT_HCIBTUSB_BCM=y CONFIG_BT_HCIBTUSB_MTK=y CONFIG_BT_HCIBTUSB_RTL=y CONFIG_BT_HCIBTSDIO=m CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_SERDEV=y CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_NOKIA=m CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIUART_LL=y CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_INTEL=y CONFIG_BT_HCIUART_RTL=y CONFIG_BT_HCIUART_QCA=y CONFIG_BT_HCIUART_AG6XX=y CONFIG_BT_HCIUART_MRVL=y CONFIG_BT_HCIBCM203X=m CONFIG_BT_HCIBPA10X=m CONFIG_BT_HCIBFUSB=m CONFIG_BT_HCIDTL1=m CONFIG_BT_HCIBT3C=m CONFIG_BT_HCIBLUECARD=m CONFIG_BT_HCIVHCI=m CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m CONFIG_BT_ATH3K=m CONFIG_BT_MTKSDIO=m CONFIG_BT_MTKUART=m CONFIG_BT_QCOMSMD=m CONFIG_BT_HCIRSI=m CONFIG_BT_VIRTIO=m # end of Bluetooth device drivers CONFIG_AF_RXRPC=m CONFIG_AF_RXRPC_IPV6=y CONFIG_AF_RXRPC_INJECT_LOSS=y CONFIG_AF_RXRPC_DEBUG=y CONFIG_RXKAD=y CONFIG_AF_KCM=m CONFIG_STREAM_PARSER=y CONFIG_MCTP=y CONFIG_MCTP_FLOWS=y CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y CONFIG_WEXT_CORE=y CONFIG_WEXT_PROC=y CONFIG_WEXT_SPY=y CONFIG_WEXT_PRIV=y CONFIG_CFG80211=m CONFIG_NL80211_TESTMODE=y CONFIG_CFG80211_DEVELOPER_WARNINGS=y CONFIG_CFG80211_CERTIFICATION_ONUS=y CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y CONFIG_CFG80211_EXTRA_REGDB_KEYDIR="" CONFIG_CFG80211_REG_CELLULAR_HINTS=y CONFIG_CFG80211_REG_RELAX_NO_IR=y CONFIG_CFG80211_DEFAULT_PS=y CONFIG_CFG80211_DEBUGFS=y CONFIG_CFG80211_CRDA_SUPPORT=y CONFIG_CFG80211_WEXT=y CONFIG_CFG80211_WEXT_EXPORT=y CONFIG_LIB80211=m CONFIG_LIB80211_CRYPT_WEP=m CONFIG_LIB80211_CRYPT_CCMP=m CONFIG_LIB80211_CRYPT_TKIP=m CONFIG_LIB80211_DEBUG=y CONFIG_MAC80211=m CONFIG_MAC80211_HAS_RC=y CONFIG_MAC80211_RC_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" CONFIG_MAC80211_MESH=y CONFIG_MAC80211_LEDS=y CONFIG_MAC80211_DEBUGFS=y CONFIG_MAC80211_MESSAGE_TRACING=y CONFIG_MAC80211_DEBUG_MENU=y CONFIG_MAC80211_NOINLINE=y CONFIG_MAC80211_VERBOSE_DEBUG=y CONFIG_MAC80211_MLME_DEBUG=y CONFIG_MAC80211_STA_DEBUG=y CONFIG_MAC80211_HT_DEBUG=y CONFIG_MAC80211_OCB_DEBUG=y CONFIG_MAC80211_IBSS_DEBUG=y CONFIG_MAC80211_PS_DEBUG=y CONFIG_MAC80211_MPL_DEBUG=y CONFIG_MAC80211_MPATH_DEBUG=y CONFIG_MAC80211_MHWMP_DEBUG=y CONFIG_MAC80211_MESH_SYNC_DEBUG=y CONFIG_MAC80211_MESH_CSA_DEBUG=y CONFIG_MAC80211_MESH_PS_DEBUG=y CONFIG_MAC80211_TDLS_DEBUG=y CONFIG_MAC80211_DEBUG_COUNTERS=y CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 CONFIG_RFKILL=m CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y CONFIG_RFKILL_GPIO=m CONFIG_NET_9P=m CONFIG_NET_9P_FD=m CONFIG_NET_9P_VIRTIO=m CONFIG_NET_9P_RDMA=m CONFIG_NET_9P_DEBUG=y CONFIG_CAIF=m CONFIG_CAIF_DEBUG=y CONFIG_CAIF_NETDEV=m CONFIG_CAIF_USB=m CONFIG_CEPH_LIB=m CONFIG_CEPH_LIB_PRETTYDEBUG=y CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y CONFIG_NFC=m CONFIG_NFC_DIGITAL=m CONFIG_NFC_NCI=m CONFIG_NFC_NCI_SPI=m CONFIG_NFC_NCI_UART=m CONFIG_NFC_HCI=m CONFIG_NFC_SHDLC=y # # Near Field Communication (NFC) devices # CONFIG_NFC_TRF7970A=m CONFIG_NFC_SIM=m CONFIG_NFC_PORT100=m CONFIG_NFC_VIRTUAL_NCI=m CONFIG_NFC_FDP=m CONFIG_NFC_FDP_I2C=m CONFIG_NFC_PN544=m CONFIG_NFC_PN544_I2C=m CONFIG_NFC_PN533=m CONFIG_NFC_PN533_USB=m CONFIG_NFC_PN533_I2C=m CONFIG_NFC_PN532_UART=m CONFIG_NFC_MICROREAD=m CONFIG_NFC_MICROREAD_I2C=m CONFIG_NFC_MRVL=m CONFIG_NFC_MRVL_USB=m CONFIG_NFC_MRVL_UART=m CONFIG_NFC_MRVL_I2C=m CONFIG_NFC_MRVL_SPI=m CONFIG_NFC_ST21NFCA=m CONFIG_NFC_ST21NFCA_I2C=m CONFIG_NFC_ST_NCI=m CONFIG_NFC_ST_NCI_I2C=m CONFIG_NFC_ST_NCI_SPI=m CONFIG_NFC_NXP_NCI=m CONFIG_NFC_NXP_NCI_I2C=m CONFIG_NFC_S3FWRN5=m CONFIG_NFC_S3FWRN5_I2C=m CONFIG_NFC_S3FWRN82_UART=m CONFIG_NFC_ST95HF=m # end of Near Field Communication (NFC) devices CONFIG_PSAMPLE=m CONFIG_NET_IFE=m CONFIG_LWTUNNEL=y CONFIG_LWTUNNEL_BPF=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y CONFIG_SOCK_VALIDATE_XMIT=y CONFIG_NET_SELFTESTS=m CONFIG_NET_SOCK_MSG=y CONFIG_NET_DEVLINK=y CONFIG_PAGE_POOL=y CONFIG_PAGE_POOL_STATS=y CONFIG_FAILOVER=m CONFIG_ETHTOOL_NETLINK=y CONFIG_NETDEV_ADDR_LIST_TEST=m # # Device Drivers # CONFIG_HAVE_PCI=y CONFIG_FORCE_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_SYSCALL=y CONFIG_PCIEPORTBUS=y CONFIG_HOTPLUG_PCI_PCIE=y CONFIG_PCIEAER=y CONFIG_PCIEAER_INJECT=m CONFIG_PCIE_ECRC=y CONFIG_PCIEASPM=y CONFIG_PCIEASPM_DEFAULT=y # CONFIG_PCIEASPM_POWERSAVE is not set # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set # CONFIG_PCIEASPM_PERFORMANCE is not set CONFIG_PCIE_PME=y CONFIG_PCIE_DPC=y CONFIG_PCIE_PTM=y CONFIG_PCIE_EDR=y CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_MSI_ARCH_FALLBACKS=y CONFIG_PCI_QUIRKS=y CONFIG_PCI_DEBUG=y CONFIG_PCI_REALLOC_ENABLE_AUTO=y CONFIG_PCI_STUB=m CONFIG_PCI_PF_STUB=m CONFIG_PCI_ATS=y CONFIG_PCI_DOE=y CONFIG_PCI_ECAM=y CONFIG_PCI_BRIDGE_EMUL=y CONFIG_PCI_IOV=y CONFIG_PCI_PRI=y CONFIG_PCI_PASID=y CONFIG_PCI_LABEL=y # CONFIG_PCIE_BUS_TUNE_OFF is not set CONFIG_PCIE_BUS_DEFAULT=y # CONFIG_PCIE_BUS_SAFE is not set # CONFIG_PCIE_BUS_PERFORMANCE is not set # CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_HOTPLUG_PCI=y CONFIG_HOTPLUG_PCI_ACPI=y CONFIG_HOTPLUG_PCI_ACPI_IBM=m CONFIG_HOTPLUG_PCI_CPCI=y CONFIG_HOTPLUG_PCI_SHPC=y # # PCI controller drivers # CONFIG_PCI_AARDVARK=m CONFIG_PCIE_XILINX_NWL=y CONFIG_PCI_FTPCI100=y CONFIG_PCI_TEGRA=y CONFIG_PCIE_RCAR_HOST=y CONFIG_PCIE_RCAR_EP=y CONFIG_PCI_HOST_COMMON=y CONFIG_PCI_HOST_GENERIC=m CONFIG_PCIE_XILINX=y CONFIG_PCIE_XILINX_CPM=y CONFIG_PCI_XGENE=y CONFIG_PCI_XGENE_MSI=y CONFIG_PCI_V3_SEMI=y CONFIG_PCI_VERSATILE=y CONFIG_PCIE_ALTERA=m CONFIG_PCIE_ALTERA_MSI=m CONFIG_PCI_HOST_THUNDER_PEM=y CONFIG_PCI_HOST_THUNDER_ECAM=y CONFIG_PCIE_ROCKCHIP=y CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCIE_ROCKCHIP_EP=y CONFIG_PCIE_MEDIATEK=m CONFIG_PCIE_MEDIATEK_GEN3=m CONFIG_PCIE_BRCMSTB=m CONFIG_PCI_LOONGSON=y CONFIG_PCIE_MICROCHIP_HOST=y CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR=0xfffff000 CONFIG_PCIE_APPLE=m CONFIG_PCIE_MT7621=m # # DesignWare PCI Core Support # CONFIG_PCIE_DW=y CONFIG_PCIE_DW_HOST=y CONFIG_PCIE_DW_EP=y CONFIG_PCI_DRA7XX=m CONFIG_PCI_DRA7XX_HOST=m CONFIG_PCI_DRA7XX_EP=m CONFIG_PCIE_DW_PLAT=y CONFIG_PCIE_DW_PLAT_HOST=y CONFIG_PCIE_DW_PLAT_EP=y CONFIG_PCI_EXYNOS=m CONFIG_PCI_IMX6=y CONFIG_PCIE_SPEAR13XX=y CONFIG_PCI_KEYSTONE=y CONFIG_PCI_KEYSTONE_HOST=y CONFIG_PCI_KEYSTONE_EP=y CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_LAYERSCAPE_EP=y CONFIG_PCI_HISI=y CONFIG_PCIE_QCOM=y CONFIG_PCIE_QCOM_EP=m CONFIG_PCIE_ARMADA_8K=y CONFIG_PCIE_ARTPEC6=y CONFIG_PCIE_ARTPEC6_HOST=y CONFIG_PCIE_ARTPEC6_EP=y CONFIG_PCIE_ROCKCHIP_DW_HOST=y CONFIG_PCIE_INTEL_GW=y CONFIG_PCIE_KEEMBAY=y CONFIG_PCIE_KEEMBAY_HOST=y CONFIG_PCIE_KEEMBAY_EP=y CONFIG_PCIE_KIRIN=m CONFIG_PCIE_HISI_STB=y CONFIG_PCI_MESON=m CONFIG_PCIE_TEGRA194=m CONFIG_PCIE_TEGRA194_HOST=m CONFIG_PCIE_TEGRA194_EP=m CONFIG_PCIE_VISCONTI_HOST=y CONFIG_PCIE_UNIPHIER=y CONFIG_PCIE_UNIPHIER_EP=y CONFIG_PCIE_AL=y CONFIG_PCIE_FU740=y # end of DesignWare PCI Core Support # # Mobiveil PCIe Core Support # CONFIG_PCIE_MOBIVEIL=y CONFIG_PCIE_MOBIVEIL_HOST=y CONFIG_PCIE_MOBIVEIL_PLAT=y CONFIG_PCIE_LAYERSCAPE_GEN4=y # end of Mobiveil PCIe Core Support # # Cadence PCIe controllers support # CONFIG_PCIE_CADENCE=y CONFIG_PCIE_CADENCE_HOST=y CONFIG_PCIE_CADENCE_EP=y CONFIG_PCIE_CADENCE_PLAT=y CONFIG_PCIE_CADENCE_PLAT_HOST=y CONFIG_PCIE_CADENCE_PLAT_EP=y CONFIG_PCI_J721E=y CONFIG_PCI_J721E_HOST=y CONFIG_PCI_J721E_EP=y # end of Cadence PCIe controllers support # end of PCI controller drivers # # PCI Endpoint # CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y CONFIG_PCI_EPF_TEST=m CONFIG_PCI_EPF_NTB=m CONFIG_PCI_EPF_VNTB=m # end of PCI Endpoint # # PCI switch controller drivers # CONFIG_PCI_SW_SWITCHTEC=m # end of PCI switch controller drivers CONFIG_CXL_BUS=m CONFIG_CXL_PCI=m CONFIG_CXL_MEM_RAW_COMMANDS=y CONFIG_CXL_ACPI=m CONFIG_CXL_PMEM=m CONFIG_CXL_MEM=m CONFIG_CXL_PORT=m CONFIG_CXL_REGION=y CONFIG_PCCARD=m CONFIG_PCMCIA=m CONFIG_PCMCIA_LOAD_CIS=y CONFIG_CARDBUS=y # # PC-card bridges # CONFIG_YENTA=m CONFIG_YENTA_O2=y CONFIG_YENTA_RICOH=y CONFIG_YENTA_TI=y CONFIG_YENTA_ENE_TUNE=y CONFIG_YENTA_TOSHIBA=y CONFIG_PD6729=m CONFIG_I82092=m CONFIG_PCCARD_NONSTATIC=y CONFIG_RAPIDIO=m CONFIG_RAPIDIO_TSI721=m CONFIG_RAPIDIO_DISC_TIMEOUT=30 CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS=y CONFIG_RAPIDIO_DMA_ENGINE=y CONFIG_RAPIDIO_DEBUG=y CONFIG_RAPIDIO_ENUM_BASIC=m CONFIG_RAPIDIO_CHMAN=m CONFIG_RAPIDIO_MPORT_CDEV=m # # RapidIO Switch drivers # CONFIG_RAPIDIO_CPS_XX=m CONFIG_RAPIDIO_CPS_GEN2=m CONFIG_RAPIDIO_RXS_GEN3=m # end of RapidIO Switch drivers # # Generic Driver Options # CONFIG_AUXILIARY_BUS=y CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # # Firmware loader # CONFIG_FW_LOADER=y CONFIG_FW_LOADER_PAGED_BUF=y CONFIG_FW_LOADER_SYSFS=y CONFIG_EXTRA_FIRMWARE="" CONFIG_FW_LOADER_USER_HELPER=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_FW_LOADER_COMPRESS=y CONFIG_FW_LOADER_COMPRESS_XZ=y CONFIG_FW_LOADER_COMPRESS_ZSTD=y CONFIG_FW_UPLOAD=y # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y CONFIG_ALLOW_DEV_COREDUMP=y CONFIG_DEV_COREDUMP=y CONFIG_DEBUG_DRIVER=y CONFIG_DEBUG_DEVRES=y CONFIG_DEBUG_TEST_DRIVER_REMOVE=y CONFIG_HMEM_REPORTING=y CONFIG_TEST_ASYNC_DRIVER_PROBE=m CONFIG_SOC_BUS=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=m CONFIG_REGMAP_SLIMBUS=m CONFIG_REGMAP_SPI=y CONFIG_REGMAP_SPMI=m CONFIG_REGMAP_W1=m CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_IRQ=y CONFIG_REGMAP_SCCB=m CONFIG_REGMAP_I3C=m CONFIG_REGMAP_SPI_AVMM=m CONFIG_DMA_SHARED_BUFFER=y CONFIG_DMA_FENCE_TRACE=y # end of Generic Driver Options # # Bus devices # CONFIG_ARM_INTEGRATOR_LM=y CONFIG_BT1_APB=y CONFIG_BT1_AXI=y CONFIG_MOXTET=m CONFIG_HISILICON_LPC=y CONFIG_INTEL_IXP4XX_EB=y CONFIG_QCOM_EBI2=y CONFIG_MHI_BUS=m CONFIG_MHI_BUS_DEBUG=y CONFIG_MHI_BUS_PCI_GENERIC=m CONFIG_MHI_BUS_EP=m # end of Bus devices CONFIG_CONNECTOR=m # # Firmware Drivers # # # ARM System Control and Management Interface Protocol # CONFIG_ARM_SCMI_PROTOCOL=m CONFIG_ARM_SCMI_HAVE_TRANSPORT=y CONFIG_ARM_SCMI_HAVE_SHMEM=y CONFIG_ARM_SCMI_HAVE_MSG=y CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y CONFIG_ARM_SCMI_TRANSPORT_VIRTIO=y CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE=y CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE=y CONFIG_ARM_SCMI_POWER_DOMAIN=m CONFIG_ARM_SCMI_POWER_CONTROL=m # end of ARM System Control and Management Interface Protocol CONFIG_ARM_SCPI_PROTOCOL=m CONFIG_ARM_SCPI_POWER_DOMAIN=m CONFIG_FIRMWARE_MEMMAP=y CONFIG_EFI_PCDP=y CONFIG_DMIID=y CONFIG_DMI_SYSFS=m CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y CONFIG_ISCSI_IBFT=m CONFIG_MTK_ADSP_IPC=m CONFIG_QCOM_SCM=y CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT=y CONFIG_SYSFB=y CONFIG_SYSFB_SIMPLEFB=y CONFIG_TURRIS_MOX_RWTM=m CONFIG_BCM47XX_NVRAM=y CONFIG_BCM47XX_SPROM=y CONFIG_TEE_BNXT_FW=m CONFIG_GOOGLE_FIRMWARE=y CONFIG_GOOGLE_COREBOOT_TABLE=m CONFIG_GOOGLE_MEMCONSOLE=m CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT=m CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=m CONFIG_GOOGLE_VPD=m # # EFI (Extensible Firmware Interface) Support # CONFIG_EFI_VARS_PSTORE=m CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y CONFIG_EFI_BOOTLOADER_CONTROL=m CONFIG_EFI_TEST=m CONFIG_EFI_RCI2_TABLE=y CONFIG_EFI_DISABLE_PCI_DMA=y CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y CONFIG_EFI_DISABLE_RUNTIME=y CONFIG_EFI_COCO_SECRET=y # end of EFI (Extensible Firmware Interface) Support CONFIG_IMX_DSP=m CONFIG_IMX_SCU=y CONFIG_IMX_SCU_PD=y # # Tegra firmware driver # # end of Tegra firmware driver # end of Firmware Drivers CONFIG_GNSS=m CONFIG_GNSS_SERIAL=m CONFIG_GNSS_MTK_SERIAL=m CONFIG_GNSS_SIRF_SERIAL=m CONFIG_GNSS_UBX_SERIAL=m CONFIG_GNSS_USB=m CONFIG_MTD=m CONFIG_MTD_TESTS=m # # Partition parsers # CONFIG_MTD_AR7_PARTS=m CONFIG_MTD_BCM63XX_PARTS=y CONFIG_MTD_BRCM_U_BOOT=m CONFIG_MTD_CMDLINE_PARTS=m CONFIG_MTD_OF_PARTS=m CONFIG_MTD_OF_PARTS_BCM4908=y CONFIG_MTD_OF_PARTS_LINKSYS_NS=y CONFIG_MTD_PARSER_IMAGETAG=m CONFIG_MTD_PARSER_TRX=m CONFIG_MTD_SHARPSL_PARTS=m CONFIG_MTD_REDBOOT_PARTS=m CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y CONFIG_MTD_QCOMSMEM_PARTS=m # end of Partition parsers # # User Modules And Translation Layers # CONFIG_MTD_BLKDEVS=m CONFIG_MTD_BLOCK=m CONFIG_MTD_BLOCK_RO=m # # Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. # CONFIG_FTL=m CONFIG_NFTL=m CONFIG_NFTL_RW=y CONFIG_INFTL=m CONFIG_RFD_FTL=m CONFIG_SSFDC=m CONFIG_SM_FTL=m CONFIG_MTD_OOPS=m CONFIG_MTD_PSTORE=m CONFIG_MTD_SWAP=m CONFIG_MTD_PARTITIONED_MASTER=y # # RAM/ROM/Flash chip drivers # CONFIG_MTD_CFI=m CONFIG_MTD_JEDECPROBE=m CONFIG_MTD_GEN_PROBE=m CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_NOSWAP=y # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set CONFIG_MTD_CFI_GEOMETRY=y CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y CONFIG_MTD_MAP_BANK_WIDTH_8=y CONFIG_MTD_MAP_BANK_WIDTH_16=y CONFIG_MTD_MAP_BANK_WIDTH_32=y CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_I4=y CONFIG_MTD_CFI_I8=y CONFIG_MTD_OTP=y CONFIG_MTD_CFI_INTELEXT=m CONFIG_MTD_CFI_AMDSTD=m CONFIG_MTD_CFI_STAA=m CONFIG_MTD_CFI_UTIL=m CONFIG_MTD_RAM=m CONFIG_MTD_ROM=m CONFIG_MTD_ABSENT=m # end of RAM/ROM/Flash chip drivers # # Mapping drivers for chip access # CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PHYSMAP=m CONFIG_MTD_PHYSMAP_COMPAT=y CONFIG_MTD_PHYSMAP_START=0x8000000 CONFIG_MTD_PHYSMAP_LEN=0 CONFIG_MTD_PHYSMAP_BANKWIDTH=2 CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_PHYSMAP_BT1_ROM=y CONFIG_MTD_PHYSMAP_VERSATILE=y CONFIG_MTD_PHYSMAP_GEMINI=y CONFIG_MTD_PHYSMAP_GPIO_ADDR=y CONFIG_MTD_SC520CDP=m CONFIG_MTD_NETSC520=m CONFIG_MTD_TS5500=m CONFIG_MTD_PCI=m CONFIG_MTD_PCMCIA=m CONFIG_MTD_PCMCIA_ANONYMOUS=y CONFIG_MTD_INTEL_VR_NOR=m CONFIG_MTD_PLATRAM=m # end of Mapping drivers for chip access # # Self-contained MTD device drivers # CONFIG_MTD_PMC551=m CONFIG_MTD_PMC551_BUGFIX=y CONFIG_MTD_PMC551_DEBUG=y CONFIG_MTD_DATAFLASH=m CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y CONFIG_MTD_DATAFLASH_OTP=y CONFIG_MTD_MCHP23K256=m CONFIG_MTD_MCHP48L640=m CONFIG_MTD_SPEAR_SMI=m CONFIG_MTD_SST25L=m CONFIG_MTD_SLRAM=m CONFIG_MTD_PHRAM=m CONFIG_MTD_MTDRAM=m CONFIG_MTDRAM_TOTAL_SIZE=4096 CONFIG_MTDRAM_ERASE_SIZE=128 CONFIG_MTD_BLOCK2MTD=m # # Disk-On-Chip Device Drivers # CONFIG_MTD_DOCG3=m CONFIG_BCH_CONST_M=14 CONFIG_BCH_CONST_T=4 # end of Self-contained MTD device drivers # # NAND # CONFIG_MTD_NAND_CORE=m CONFIG_MTD_ONENAND=m CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_GENERIC=m CONFIG_MTD_ONENAND_SAMSUNG=m CONFIG_MTD_ONENAND_OTP=y CONFIG_MTD_ONENAND_2X_PROGRAM=y CONFIG_MTD_RAW_NAND=m # # Raw/parallel NAND flash controllers # CONFIG_MTD_NAND_DENALI=m CONFIG_MTD_NAND_DENALI_PCI=m CONFIG_MTD_NAND_DENALI_DT=m CONFIG_MTD_NAND_AMS_DELTA=m CONFIG_MTD_NAND_OMAP2=m CONFIG_MTD_NAND_OMAP_BCH=y CONFIG_MTD_NAND_OMAP_BCH_BUILD=m CONFIG_MTD_NAND_SHARPSL=m CONFIG_MTD_NAND_CAFE=m CONFIG_MTD_NAND_ATMEL=m CONFIG_MTD_NAND_MARVELL=m CONFIG_MTD_NAND_SLC_LPC32XX=m CONFIG_MTD_NAND_MLC_LPC32XX=m CONFIG_MTD_NAND_BRCMNAND=m CONFIG_MTD_NAND_BRCMNAND_BCM63XX=m CONFIG_MTD_NAND_BRCMNAND_BCMA=m CONFIG_MTD_NAND_BRCMNAND_BCMBCA=m CONFIG_MTD_NAND_BRCMNAND_BRCMSTB=m CONFIG_MTD_NAND_BRCMNAND_IPROC=m CONFIG_MTD_NAND_BCM47XXNFLASH=m CONFIG_MTD_NAND_OXNAS=m CONFIG_MTD_NAND_GPMI_NAND=m CONFIG_MTD_NAND_FSL_IFC=m CONFIG_MTD_NAND_VF610_NFC=m CONFIG_MTD_NAND_MXC=m CONFIG_MTD_NAND_SH_FLCTL=m CONFIG_MTD_NAND_DAVINCI=m CONFIG_MTD_NAND_TXX9NDFMC=m CONFIG_MTD_NAND_JZ4780=m CONFIG_MTD_NAND_INGENIC_ECC=y CONFIG_MTD_NAND_JZ4740_ECC=m CONFIG_MTD_NAND_JZ4725B_BCH=m CONFIG_MTD_NAND_JZ4780_BCH=m CONFIG_MTD_NAND_FSMC=m CONFIG_MTD_NAND_SUNXI=m CONFIG_MTD_NAND_HISI504=m CONFIG_MTD_NAND_QCOM=m CONFIG_MTD_NAND_MTK=m CONFIG_MTD_NAND_MXIC=m CONFIG_MTD_NAND_TEGRA=m CONFIG_MTD_NAND_STM32_FMC2=m CONFIG_MTD_NAND_MESON=m CONFIG_MTD_NAND_GPIO=m CONFIG_MTD_NAND_PLATFORM=m CONFIG_MTD_NAND_CADENCE=m CONFIG_MTD_NAND_ARASAN=m CONFIG_MTD_NAND_INTEL_LGM=m CONFIG_MTD_NAND_RENESAS=m # # Misc # CONFIG_MTD_SM_COMMON=m CONFIG_MTD_NAND_NANDSIM=m CONFIG_MTD_NAND_RICOH=m CONFIG_MTD_NAND_DISKONCHIP=m CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y CONFIG_MTD_SPI_NAND=m # # ECC engine support # CONFIG_MTD_NAND_ECC=y CONFIG_MTD_NAND_ECC_SW_HAMMING=y CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y CONFIG_MTD_NAND_ECC_SW_BCH=y CONFIG_MTD_NAND_ECC_MXIC=y CONFIG_MTD_NAND_ECC_MEDIATEK=m # end of ECC engine support # end of NAND # # LPDDR & LPDDR2 PCM memory drivers # CONFIG_MTD_LPDDR=m CONFIG_MTD_QINFO_PROBE=m # end of LPDDR & LPDDR2 PCM memory drivers CONFIG_MTD_SPI_NOR=m CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y # CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y # CONFIG_MTD_SPI_NOR_SWP_KEEP is not set CONFIG_SPI_HISI_SFC=m CONFIG_SPI_NXP_SPIFI=m CONFIG_MTD_UBI=m CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_GLUEBI=m CONFIG_MTD_UBI_BLOCK=y CONFIG_MTD_HYPERBUS=m CONFIG_HBMC_AM654=m CONFIG_DTC=y CONFIG_OF=y CONFIG_OF_UNITTEST=y CONFIG_OF_ALL_DTBS=y CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_KOBJ=y CONFIG_OF_DYNAMIC=y CONFIG_OF_ADDRESS=y CONFIG_OF_IRQ=y CONFIG_OF_RESERVED_MEM=y CONFIG_OF_RESOLVE=y CONFIG_OF_OVERLAY=y CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_PARPORT=m CONFIG_PARPORT_PC=m CONFIG_PARPORT_SERIAL=m CONFIG_PARPORT_PC_FIFO=y CONFIG_PARPORT_PC_SUPERIO=y CONFIG_PARPORT_PC_PCMCIA=m CONFIG_PARPORT_AX88796=m CONFIG_PARPORT_1284=y CONFIG_PARPORT_NOT_PC=y CONFIG_PNP=y CONFIG_PNP_DEBUG_MESSAGES=y # # Protocols # CONFIG_ISAPNP=y CONFIG_PNPACPI=y CONFIG_BLK_DEV=y CONFIG_BLK_DEV_NULL_BLK=m CONFIG_BLK_DEV_NULL_BLK_FAULT_INJECTION=y CONFIG_CDROM=m CONFIG_PARIDE=m # # Parallel IDE high-level drivers # CONFIG_PARIDE_PD=m CONFIG_PARIDE_PCD=m CONFIG_PARIDE_PF=m CONFIG_PARIDE_PT=m CONFIG_PARIDE_PG=m # # Parallel IDE protocol modules # CONFIG_PARIDE_ATEN=m CONFIG_PARIDE_BPCK=m CONFIG_PARIDE_COMM=m CONFIG_PARIDE_DSTR=m CONFIG_PARIDE_FIT2=m CONFIG_PARIDE_FIT3=m CONFIG_PARIDE_EPAT=m CONFIG_PARIDE_EPATC8=y CONFIG_PARIDE_EPIA=m CONFIG_PARIDE_FRIQ=m CONFIG_PARIDE_FRPW=m CONFIG_PARIDE_KBIC=m CONFIG_PARIDE_KTTI=m CONFIG_PARIDE_ON20=m CONFIG_PARIDE_ON26=m CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m CONFIG_ZRAM=m CONFIG_ZRAM_DEF_COMP_LZORLE=y # CONFIG_ZRAM_DEF_COMP_ZSTD is not set # CONFIG_ZRAM_DEF_COMP_LZ4 is not set # CONFIG_ZRAM_DEF_COMP_LZO is not set # CONFIG_ZRAM_DEF_COMP_LZ4HC is not set # CONFIG_ZRAM_DEF_COMP_842 is not set CONFIG_ZRAM_DEF_COMP="lzo-rle" CONFIG_ZRAM_WRITEBACK=y CONFIG_ZRAM_MEMORY_TRACKING=y CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 CONFIG_BLK_DEV_DRBD=m CONFIG_DRBD_FAULT_INJECTION=y CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 CONFIG_CDROM_PKTCDVD_WCACHE=y CONFIG_ATA_OVER_ETH=m CONFIG_VIRTIO_BLK=m CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_UBLK=m CONFIG_BLK_DEV_RNBD=y CONFIG_BLK_DEV_RNBD_CLIENT=m CONFIG_BLK_DEV_RNBD_SERVER=m # # NVME Support # CONFIG_NVME_COMMON=m CONFIG_NVME_CORE=m CONFIG_BLK_DEV_NVME=m CONFIG_NVME_MULTIPATH=y CONFIG_NVME_VERBOSE_ERRORS=y CONFIG_NVME_HWMON=y CONFIG_NVME_FABRICS=m CONFIG_NVME_RDMA=m CONFIG_NVME_FC=m CONFIG_NVME_TCP=m CONFIG_NVME_AUTH=y CONFIG_NVME_APPLE=m CONFIG_NVME_TARGET=m CONFIG_NVME_TARGET_PASSTHRU=y CONFIG_NVME_TARGET_LOOP=m CONFIG_NVME_TARGET_RDMA=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_TCP=m CONFIG_NVME_TARGET_AUTH=y # end of NVME Support # # Misc devices # CONFIG_SENSORS_LIS3LV02D=m CONFIG_AD525X_DPOT=m CONFIG_AD525X_DPOT_I2C=m CONFIG_AD525X_DPOT_SPI=m CONFIG_DUMMY_IRQ=m CONFIG_PHANTOM=m CONFIG_TIFM_CORE=m CONFIG_TIFM_7XX1=m CONFIG_ICS932S401=m CONFIG_ATMEL_SSC=m CONFIG_ENCLOSURE_SERVICES=m CONFIG_GEHC_ACHC=m CONFIG_HI6421V600_IRQ=m CONFIG_HP_ILO=m CONFIG_QCOM_COINCELL=m CONFIG_QCOM_FASTRPC=m CONFIG_APDS9802ALS=m CONFIG_ISL29003=m CONFIG_ISL29020=m CONFIG_SENSORS_TSL2550=m CONFIG_SENSORS_BH1770=m CONFIG_SENSORS_APDS990X=m CONFIG_HMC6352=m CONFIG_DS1682=m CONFIG_PCH_PHUB=m CONFIG_LATTICE_ECP3_CONFIG=m CONFIG_SRAM=y CONFIG_DW_XDATA_PCIE=m CONFIG_PCI_ENDPOINT_TEST=m CONFIG_XILINX_SDFEC=m CONFIG_MISC_RTSX=m CONFIG_HISI_HIKEY_USB=m CONFIG_OPEN_DICE=m CONFIG_VCPU_STALL_DETECTOR=m CONFIG_C2PORT=m # # EEPROM support # CONFIG_EEPROM_AT24=m CONFIG_EEPROM_AT25=m CONFIG_EEPROM_LEGACY=m CONFIG_EEPROM_MAX6875=m CONFIG_EEPROM_93CX6=m CONFIG_EEPROM_93XX46=m CONFIG_EEPROM_IDT_89HPESX=m CONFIG_EEPROM_EE1004=m # end of EEPROM support CONFIG_CB710_CORE=m CONFIG_CB710_DEBUG=y CONFIG_CB710_DEBUG_ASSUMPTIONS=y # # Texas Instruments shared transport line discipline # CONFIG_TI_ST=m # end of Texas Instruments shared transport line discipline CONFIG_SENSORS_LIS3_I2C=m # # Altera FPGA firmware download module (requires I2C) # CONFIG_ALTERA_STAPL=m CONFIG_GENWQE=m CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 CONFIG_ECHO=m CONFIG_BCM_VK=m CONFIG_BCM_VK_TTY=y CONFIG_MISC_ALCOR_PCI=m CONFIG_MISC_RTSX_PCI=m CONFIG_MISC_RTSX_USB=m CONFIG_HABANA_AI=m CONFIG_UACCE=m CONFIG_PVPANIC=y CONFIG_PVPANIC_MMIO=m CONFIG_PVPANIC_PCI=m CONFIG_GP_PCI1XXXX=m # end of Misc devices # # SCSI device support # CONFIG_SCSI_MOD=m CONFIG_RAID_ATTRS=m CONFIG_SCSI_COMMON=m CONFIG_SCSI=m CONFIG_SCSI_DMA=y CONFIG_SCSI_NETLINK=y CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=m CONFIG_CHR_DEV_ST=m CONFIG_BLK_DEV_SR=m CONFIG_CHR_DEV_SG=m CONFIG_BLK_DEV_BSG=y CONFIG_CHR_DEV_SCH=m CONFIG_SCSI_ENCLOSURE=m CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y # # SCSI Transports # CONFIG_SCSI_SPI_ATTRS=m CONFIG_SCSI_FC_ATTRS=m CONFIG_SCSI_ISCSI_ATTRS=m CONFIG_SCSI_SAS_ATTRS=m CONFIG_SCSI_SAS_LIBSAS=m CONFIG_SCSI_SAS_ATA=y CONFIG_SCSI_SAS_HOST_SMP=y CONFIG_SCSI_SRP_ATTRS=m # end of SCSI Transports CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_TCP=m CONFIG_ISCSI_BOOT_SYSFS=m CONFIG_SCSI_CXGB3_ISCSI=m CONFIG_SCSI_CXGB4_ISCSI=m CONFIG_SCSI_BNX2_ISCSI=m CONFIG_SCSI_BNX2X_FCOE=m CONFIG_BE2ISCSI=m CONFIG_BLK_DEV_3W_XXXX_RAID=m CONFIG_SCSI_HPSA=m CONFIG_SCSI_3W_9XXX=m CONFIG_SCSI_3W_SAS=m CONFIG_SCSI_ACARD=m CONFIG_SCSI_AACRAID=m CONFIG_SCSI_AIC7XXX=m CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 CONFIG_AIC7XXX_RESET_DELAY_MS=5000 CONFIG_AIC7XXX_DEBUG_ENABLE=y CONFIG_AIC7XXX_DEBUG_MASK=0 CONFIG_AIC7XXX_REG_PRETTY_PRINT=y CONFIG_SCSI_AIC79XX=m CONFIG_AIC79XX_CMDS_PER_DEVICE=32 CONFIG_AIC79XX_RESET_DELAY_MS=5000 CONFIG_AIC79XX_DEBUG_ENABLE=y CONFIG_AIC79XX_DEBUG_MASK=0 CONFIG_AIC79XX_REG_PRETTY_PRINT=y CONFIG_SCSI_AIC94XX=m CONFIG_AIC94XX_DEBUG=y CONFIG_SCSI_HISI_SAS=m CONFIG_SCSI_HISI_SAS_PCI=m CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE=y CONFIG_SCSI_MVSAS=m CONFIG_SCSI_MVSAS_DEBUG=y CONFIG_SCSI_MVSAS_TASKLET=y CONFIG_SCSI_MVUMI=m CONFIG_SCSI_ADVANSYS=m CONFIG_SCSI_ARCMSR=m CONFIG_SCSI_ESAS2R=m CONFIG_MEGARAID_NEWGEN=y CONFIG_MEGARAID_MM=m CONFIG_MEGARAID_MAILBOX=m CONFIG_MEGARAID_LEGACY=m CONFIG_MEGARAID_SAS=m CONFIG_SCSI_MPT3SAS=m CONFIG_SCSI_MPT2SAS_MAX_SGE=128 CONFIG_SCSI_MPT3SAS_MAX_SGE=128 CONFIG_SCSI_MPT2SAS=m CONFIG_SCSI_MPI3MR=m CONFIG_SCSI_SMARTPQI=m CONFIG_SCSI_HPTIOP=m CONFIG_SCSI_BUSLOGIC=m CONFIG_SCSI_FLASHPOINT=y CONFIG_SCSI_MYRB=m CONFIG_SCSI_MYRS=m CONFIG_LIBFC=m CONFIG_LIBFCOE=m CONFIG_FCOE=m CONFIG_SCSI_SNIC=m CONFIG_SCSI_SNIC_DEBUG_FS=y CONFIG_SCSI_DMX3191D=m CONFIG_SCSI_FDOMAIN=m CONFIG_SCSI_FDOMAIN_PCI=m CONFIG_SCSI_IPS=m CONFIG_SCSI_INITIO=m CONFIG_SCSI_INIA100=m CONFIG_SCSI_PPA=m CONFIG_SCSI_IMM=m CONFIG_SCSI_IZIP_EPP16=y CONFIG_SCSI_IZIP_SLOW_CTR=y CONFIG_SCSI_STEX=m CONFIG_SCSI_SYM53C8XX_2=m CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 CONFIG_SCSI_SYM53C8XX_MMIO=y CONFIG_SCSI_IPR=m CONFIG_SCSI_IPR_TRACE=y CONFIG_SCSI_IPR_DUMP=y CONFIG_SCSI_QLOGIC_1280=m CONFIG_SCSI_QLA_FC=m CONFIG_TCM_QLA2XXX=m CONFIG_TCM_QLA2XXX_DEBUG=y CONFIG_SCSI_QLA_ISCSI=m CONFIG_QEDI=m CONFIG_QEDF=m CONFIG_SCSI_LPFC=m CONFIG_SCSI_LPFC_DEBUG_FS=y CONFIG_SCSI_EFCT=m CONFIG_SCSI_DC395x=m CONFIG_SCSI_AM53C974=m CONFIG_SCSI_WD719X=m CONFIG_SCSI_DEBUG=m CONFIG_SCSI_PMCRAID=m CONFIG_SCSI_PM8001=m CONFIG_SCSI_BFA_FC=m CONFIG_SCSI_VIRTIO=m CONFIG_SCSI_CHELSIO_FCOE=m CONFIG_SCSI_LOWLEVEL_PCMCIA=y CONFIG_PCMCIA_AHA152X=m CONFIG_PCMCIA_FDOMAIN=m CONFIG_PCMCIA_NINJA_SCSI=m CONFIG_PCMCIA_QLOGIC=m CONFIG_PCMCIA_SYM53C500=m CONFIG_SCSI_DH=y CONFIG_SCSI_DH_RDAC=m CONFIG_SCSI_DH_HP_SW=m CONFIG_SCSI_DH_EMC=m CONFIG_SCSI_DH_ALUA=m # end of SCSI device support CONFIG_ATA=m CONFIG_ATA_NONSTANDARD=y CONFIG_SATA_HOST=y CONFIG_PATA_TIMINGS=y CONFIG_ATA_VERBOSE_ERROR=y CONFIG_ATA_FORCE=y CONFIG_ATA_ACPI=y CONFIG_SATA_ZPODD=y CONFIG_SATA_PMP=y # # Controllers with non-SFF native interface # CONFIG_SATA_AHCI=m CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=m CONFIG_AHCI_BRCM=m CONFIG_AHCI_DA850=m CONFIG_AHCI_DM816=m CONFIG_AHCI_DWC=m CONFIG_AHCI_ST=m CONFIG_AHCI_IMX=m CONFIG_AHCI_CEVA=m CONFIG_AHCI_MTK=m CONFIG_AHCI_MVEBU=m CONFIG_AHCI_SUNXI=m CONFIG_AHCI_TEGRA=m CONFIG_AHCI_XGENE=m CONFIG_AHCI_QORIQ=m CONFIG_SATA_FSL=m CONFIG_SATA_GEMINI=m CONFIG_SATA_AHCI_SEATTLE=m CONFIG_SATA_INIC162X=m CONFIG_SATA_ACARD_AHCI=m CONFIG_SATA_SIL24=m CONFIG_ATA_SFF=y # # SFF controllers with custom DMA interface # CONFIG_PDC_ADMA=m CONFIG_SATA_QSTOR=m CONFIG_SATA_SX4=m CONFIG_ATA_BMDMA=y # # SATA SFF controllers with BMDMA # CONFIG_ATA_PIIX=m CONFIG_SATA_DWC=m CONFIG_SATA_DWC_OLD_DMA=y CONFIG_SATA_HIGHBANK=m CONFIG_SATA_MV=m CONFIG_SATA_NV=m CONFIG_SATA_PROMISE=m CONFIG_SATA_RCAR=m CONFIG_SATA_SIL=m CONFIG_SATA_SIS=m CONFIG_SATA_SVW=m CONFIG_SATA_ULI=m CONFIG_SATA_VIA=m CONFIG_SATA_VITESSE=m # # PATA SFF controllers with BMDMA # CONFIG_PATA_ALI=m CONFIG_PATA_AMD=m CONFIG_PATA_ARASAN_CF=m CONFIG_PATA_ARTOP=m CONFIG_PATA_ATIIXP=m CONFIG_PATA_ATP867X=m CONFIG_PATA_BK3710=m CONFIG_PATA_CMD64X=m CONFIG_PATA_CS5520=m CONFIG_PATA_CS5530=m CONFIG_PATA_CS5536=m CONFIG_PATA_CYPRESS=m CONFIG_PATA_EFAR=m CONFIG_PATA_FTIDE010=m CONFIG_PATA_HPT366=m CONFIG_PATA_HPT37X=m CONFIG_PATA_HPT3X2N=m CONFIG_PATA_HPT3X3=m CONFIG_PATA_HPT3X3_DMA=y CONFIG_PATA_IMX=m CONFIG_PATA_IT8213=m CONFIG_PATA_IT821X=m CONFIG_PATA_JMICRON=m CONFIG_PATA_MARVELL=m CONFIG_PATA_NETCELL=m CONFIG_PATA_NINJA32=m CONFIG_PATA_NS87415=m CONFIG_PATA_OLDPIIX=m CONFIG_PATA_OPTIDMA=m CONFIG_PATA_PDC2027X=m CONFIG_PATA_PDC_OLD=m CONFIG_PATA_RADISYS=m CONFIG_PATA_RDC=m CONFIG_PATA_SC1200=m CONFIG_PATA_SCH=m CONFIG_PATA_SERVERWORKS=m CONFIG_PATA_SIL680=m CONFIG_PATA_SIS=m CONFIG_PATA_TOSHIBA=m CONFIG_PATA_TRIFLEX=m CONFIG_PATA_VIA=m CONFIG_PATA_PXA=m CONFIG_PATA_WINBOND=m # # PIO-only SFF controllers # CONFIG_PATA_CMD640_PCI=m CONFIG_PATA_ISAPNP=m CONFIG_PATA_IXP4XX_CF=m CONFIG_PATA_MPIIX=m CONFIG_PATA_NS87410=m CONFIG_PATA_OPTI=m CONFIG_PATA_PCMCIA=m CONFIG_PATA_PLATFORM=m CONFIG_PATA_OF_PLATFORM=m CONFIG_PATA_RZ1000=m CONFIG_PATA_SAMSUNG_CF=m # # Generic fallback / legacy drivers # CONFIG_PATA_ACPI=m CONFIG_ATA_GENERIC=m CONFIG_PATA_LEGACY=m CONFIG_MD=y CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m CONFIG_MD_RAID1=m CONFIG_MD_RAID10=m CONFIG_MD_RAID456=m CONFIG_MD_MULTIPATH=m CONFIG_MD_FAULTY=m CONFIG_MD_CLUSTER=m CONFIG_BCACHE=m CONFIG_BCACHE_DEBUG=y CONFIG_BCACHE_CLOSURES_DEBUG=y CONFIG_BCACHE_ASYNC_REGISTRATION=y CONFIG_BLK_DEV_DM_BUILTIN=y CONFIG_BLK_DEV_DM=m CONFIG_DM_DEBUG=y CONFIG_DM_BUFIO=m CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING=y CONFIG_DM_DEBUG_BLOCK_STACK_TRACING=y CONFIG_DM_BIO_PRISON=m CONFIG_DM_PERSISTENT_DATA=m CONFIG_DM_UNSTRIPED=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m CONFIG_DM_THIN_PROVISIONING=m CONFIG_DM_CACHE=m CONFIG_DM_CACHE_SMQ=m CONFIG_DM_WRITECACHE=m CONFIG_DM_EBS=m CONFIG_DM_ERA=m CONFIG_DM_CLONE=m CONFIG_DM_MIRROR=m CONFIG_DM_LOG_USERSPACE=m CONFIG_DM_RAID=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_MULTIPATH_QL=m CONFIG_DM_MULTIPATH_ST=m CONFIG_DM_MULTIPATH_HST=m CONFIG_DM_MULTIPATH_IOA=m CONFIG_DM_DELAY=m CONFIG_DM_DUST=m CONFIG_DM_UEVENT=y CONFIG_DM_FLAKEY=m CONFIG_DM_VERITY=m CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_FEC=y CONFIG_DM_SWITCH=m CONFIG_DM_LOG_WRITES=m CONFIG_DM_INTEGRITY=m CONFIG_DM_ZONED=m CONFIG_DM_AUDIT=y CONFIG_TARGET_CORE=m CONFIG_TCM_IBLOCK=m CONFIG_TCM_FILEIO=m CONFIG_TCM_PSCSI=m CONFIG_TCM_USER2=m CONFIG_LOOPBACK_TARGET=m CONFIG_TCM_FC=m CONFIG_ISCSI_TARGET=m CONFIG_ISCSI_TARGET_CXGB4=m CONFIG_SBP_TARGET=m CONFIG_FUSION=y CONFIG_FUSION_SPI=m CONFIG_FUSION_FC=m CONFIG_FUSION_SAS=m CONFIG_FUSION_MAX_SGE=128 CONFIG_FUSION_CTL=m CONFIG_FUSION_LAN=m CONFIG_FUSION_LOGGING=y # # IEEE 1394 (FireWire) support # CONFIG_FIREWIRE=m CONFIG_FIREWIRE_OHCI=m CONFIG_FIREWIRE_SBP2=m CONFIG_FIREWIRE_NET=m CONFIG_FIREWIRE_NOSY=m # end of IEEE 1394 (FireWire) support CONFIG_NETDEVICES=y CONFIG_MII=m CONFIG_NET_CORE=y CONFIG_BONDING=m CONFIG_DUMMY=m CONFIG_WIREGUARD=m CONFIG_WIREGUARD_DEBUG=y CONFIG_EQUALIZER=m CONFIG_NET_FC=y CONFIG_IFB=m CONFIG_NET_TEAM=m CONFIG_NET_TEAM_MODE_BROADCAST=m CONFIG_NET_TEAM_MODE_ROUNDROBIN=m CONFIG_NET_TEAM_MODE_RANDOM=m CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m CONFIG_NET_TEAM_MODE_LOADBALANCE=m CONFIG_MACVLAN=m CONFIG_MACVTAP=m CONFIG_IPVLAN_L3S=y CONFIG_IPVLAN=m CONFIG_IPVTAP=m CONFIG_VXLAN=m CONFIG_GENEVE=m CONFIG_BAREUDP=m CONFIG_GTP=m CONFIG_AMT=m CONFIG_MACSEC=m CONFIG_NETCONSOLE=m CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_NETPOLL=y CONFIG_NET_POLL_CONTROLLER=y CONFIG_NTB_NETDEV=m CONFIG_RIONET=m CONFIG_RIONET_TX_SIZE=128 CONFIG_RIONET_RX_SIZE=128 CONFIG_TUN=m CONFIG_TAP=m CONFIG_TUN_VNET_CROSS_LE=y CONFIG_VETH=m CONFIG_VIRTIO_NET=m CONFIG_NLMON=m CONFIG_NET_VRF=m CONFIG_VSOCKMON=m CONFIG_MHI_NET=m CONFIG_SUNGEM_PHY=m CONFIG_ARCNET=m CONFIG_ARCNET_1201=m CONFIG_ARCNET_1051=m CONFIG_ARCNET_RAW=m CONFIG_ARCNET_CAP=m CONFIG_ARCNET_COM90xx=m CONFIG_ARCNET_COM90xxIO=m CONFIG_ARCNET_RIM_I=m CONFIG_ARCNET_COM20020=m CONFIG_ARCNET_COM20020_PCI=m CONFIG_ARCNET_COM20020_CS=m CONFIG_ATM_DRIVERS=y CONFIG_ATM_DUMMY=m CONFIG_ATM_TCP=m CONFIG_ATM_LANAI=m CONFIG_ATM_ENI=m CONFIG_ATM_ENI_DEBUG=y CONFIG_ATM_ENI_TUNE_BURST=y CONFIG_ATM_ENI_BURST_TX_16W=y CONFIG_ATM_ENI_BURST_TX_8W=y CONFIG_ATM_ENI_BURST_TX_4W=y CONFIG_ATM_ENI_BURST_TX_2W=y CONFIG_ATM_ENI_BURST_RX_16W=y CONFIG_ATM_ENI_BURST_RX_8W=y CONFIG_ATM_ENI_BURST_RX_4W=y CONFIG_ATM_ENI_BURST_RX_2W=y CONFIG_ATM_NICSTAR=m CONFIG_ATM_NICSTAR_USE_SUNI=y CONFIG_ATM_NICSTAR_USE_IDT77105=y CONFIG_ATM_IDT77252=m CONFIG_ATM_IDT77252_DEBUG=y CONFIG_ATM_IDT77252_RCV_ALL=y CONFIG_ATM_IDT77252_USE_SUNI=y CONFIG_ATM_IA=m CONFIG_ATM_IA_DEBUG=y CONFIG_ATM_FORE200E=m CONFIG_ATM_FORE200E_USE_TASKLET=y CONFIG_ATM_FORE200E_TX_RETRY=16 CONFIG_ATM_FORE200E_DEBUG=0 CONFIG_ATM_HE=m CONFIG_ATM_HE_USE_SUNI=y CONFIG_ATM_SOLOS=m CONFIG_CAIF_DRIVERS=y CONFIG_CAIF_TTY=m CONFIG_CAIF_VIRTIO=m # # Distributed Switch Architecture drivers # CONFIG_B53=m CONFIG_B53_SPI_DRIVER=m CONFIG_B53_MDIO_DRIVER=m CONFIG_B53_MMAP_DRIVER=m CONFIG_B53_SRAB_DRIVER=m CONFIG_B53_SERDES=m CONFIG_NET_DSA_BCM_SF2=m CONFIG_NET_DSA_LOOP=m CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m CONFIG_NET_DSA_LANTIQ_GSWIP=m CONFIG_NET_DSA_MT7530=m CONFIG_NET_DSA_MV88E6060=m CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m CONFIG_NET_DSA_MV88E6XXX=m CONFIG_NET_DSA_MV88E6XXX_PTP=y CONFIG_NET_DSA_MSCC_FELIX=m CONFIG_NET_DSA_MSCC_SEVILLE=m CONFIG_NET_DSA_AR9331=m CONFIG_NET_DSA_QCA8K=m CONFIG_NET_DSA_SJA1105=m CONFIG_NET_DSA_SJA1105_PTP=y CONFIG_NET_DSA_SJA1105_TAS=y CONFIG_NET_DSA_SJA1105_VL=y CONFIG_NET_DSA_XRS700X=m CONFIG_NET_DSA_XRS700X_I2C=m CONFIG_NET_DSA_XRS700X_MDIO=m CONFIG_NET_DSA_REALTEK=m CONFIG_NET_DSA_REALTEK_MDIO=m CONFIG_NET_DSA_REALTEK_SMI=m CONFIG_NET_DSA_REALTEK_RTL8365MB=m CONFIG_NET_DSA_REALTEK_RTL8366RB=m CONFIG_NET_DSA_SMSC_LAN9303=m CONFIG_NET_DSA_SMSC_LAN9303_I2C=m CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m CONFIG_NET_DSA_VITESSE_VSC73XX=m CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m # end of Distributed Switch Architecture drivers CONFIG_ETHERNET=y CONFIG_MDIO=m CONFIG_NET_VENDOR_3COM=y CONFIG_PCMCIA_3C574=m CONFIG_PCMCIA_3C589=m CONFIG_VORTEX=m CONFIG_TYPHOON=m CONFIG_NET_VENDOR_ACTIONS=y CONFIG_OWL_EMAC=m CONFIG_NET_VENDOR_ADAPTEC=y CONFIG_ADAPTEC_STARFIRE=m CONFIG_NET_VENDOR_AGERE=y CONFIG_ET131X=m CONFIG_NET_VENDOR_ALACRITECH=y CONFIG_SLICOSS=m CONFIG_NET_VENDOR_ALTEON=y CONFIG_ACENIC=m CONFIG_ACENIC_OMIT_TIGON_I=y CONFIG_ALTERA_TSE=m CONFIG_NET_VENDOR_AMAZON=y CONFIG_ENA_ETHERNET=m CONFIG_NET_VENDOR_AMD=y CONFIG_AMD8111_ETH=m CONFIG_PCNET32=m CONFIG_PCMCIA_NMCLAN=m CONFIG_AMD_XGBE=m CONFIG_AMD_XGBE_DCB=y CONFIG_NET_XGENE=m CONFIG_NET_XGENE_V2=m CONFIG_NET_VENDOR_AQUANTIA=y CONFIG_AQTION=m CONFIG_NET_VENDOR_ARC=y CONFIG_ARC_EMAC_CORE=m CONFIG_ARC_EMAC=m CONFIG_EMAC_ROCKCHIP=m CONFIG_NET_VENDOR_ASIX=y CONFIG_SPI_AX88796C=m CONFIG_SPI_AX88796C_COMPRESSION=y CONFIG_NET_VENDOR_ATHEROS=y CONFIG_ATL2=m CONFIG_ATL1=m CONFIG_ATL1E=m CONFIG_ATL1C=m CONFIG_ALX=m CONFIG_CX_ECAT=m CONFIG_NET_VENDOR_BROADCOM=y CONFIG_B44=m CONFIG_B44_PCI_AUTOSELECT=y CONFIG_B44_PCICORE_AUTOSELECT=y CONFIG_B44_PCI=y CONFIG_BCM4908_ENET=m CONFIG_BCMGENET=m CONFIG_BNX2=m CONFIG_CNIC=m CONFIG_TIGON3=m CONFIG_TIGON3_HWMON=y CONFIG_BNX2X=m CONFIG_BNX2X_SRIOV=y CONFIG_BGMAC=m CONFIG_BGMAC_BCMA=m CONFIG_BGMAC_PLATFORM=m CONFIG_SYSTEMPORT=m CONFIG_BNXT=m CONFIG_BNXT_SRIOV=y CONFIG_BNXT_FLOWER_OFFLOAD=y CONFIG_BNXT_DCB=y CONFIG_BNXT_HWMON=y CONFIG_NET_VENDOR_CADENCE=y CONFIG_MACB=m CONFIG_MACB_USE_HWSTAMP=y CONFIG_MACB_PCI=m CONFIG_NET_CALXEDA_XGMAC=m CONFIG_NET_VENDOR_CAVIUM=y CONFIG_THUNDER_NIC_PF=m CONFIG_THUNDER_NIC_VF=m CONFIG_THUNDER_NIC_BGX=m CONFIG_THUNDER_NIC_RGX=m CONFIG_CAVIUM_PTP=m CONFIG_LIQUIDIO=m CONFIG_LIQUIDIO_VF=m CONFIG_NET_VENDOR_CHELSIO=y CONFIG_CHELSIO_T1=m CONFIG_CHELSIO_T1_1G=y CONFIG_CHELSIO_T3=m CONFIG_CHELSIO_T4=m CONFIG_CHELSIO_T4_DCB=y CONFIG_CHELSIO_T4_FCOE=y CONFIG_CHELSIO_T4VF=m CONFIG_CHELSIO_LIB=m CONFIG_CHELSIO_INLINE_CRYPTO=y CONFIG_CRYPTO_DEV_CHELSIO_TLS=m CONFIG_CHELSIO_IPSEC_INLINE=m CONFIG_CHELSIO_TLS_DEVICE=m CONFIG_NET_VENDOR_CIRRUS=y CONFIG_CS89x0=m CONFIG_CS89x0_PLATFORM=m CONFIG_EP93XX_ETH=m CONFIG_NET_VENDOR_CISCO=y CONFIG_ENIC=m CONFIG_NET_VENDOR_CORTINA=y CONFIG_GEMINI_ETHERNET=m CONFIG_NET_VENDOR_DAVICOM=y CONFIG_DM9000=m CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y CONFIG_DM9051=m CONFIG_DNET=m CONFIG_NET_VENDOR_DEC=y CONFIG_NET_TULIP=y CONFIG_DE2104X=m CONFIG_DE2104X_DSL=0 CONFIG_TULIP=m CONFIG_TULIP_MWI=y CONFIG_TULIP_MMIO=y CONFIG_TULIP_NAPI=y CONFIG_TULIP_NAPI_HW_MITIGATION=y CONFIG_WINBOND_840=m CONFIG_DM9102=m CONFIG_ULI526X=m CONFIG_PCMCIA_XIRCOM=m CONFIG_NET_VENDOR_DLINK=y CONFIG_DL2K=m CONFIG_SUNDANCE=m CONFIG_SUNDANCE_MMIO=y CONFIG_NET_VENDOR_EMULEX=y CONFIG_BE2NET=m CONFIG_BE2NET_HWMON=y CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y CONFIG_BE2NET_LANCER=y CONFIG_BE2NET_SKYHAWK=y CONFIG_NET_VENDOR_ENGLEDER=y CONFIG_TSNEP=m CONFIG_TSNEP_SELFTESTS=y CONFIG_NET_VENDOR_EZCHIP=y CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=m CONFIG_NET_VENDOR_FARADAY=y CONFIG_NET_VENDOR_FREESCALE=y CONFIG_FEC=m CONFIG_FSL_FMAN=m CONFIG_FSL_PQ_MDIO=m CONFIG_FSL_XGMAC_MDIO=m CONFIG_GIANFAR=m CONFIG_FSL_DPAA2_SWITCH=m CONFIG_FSL_ENETC=m CONFIG_FSL_ENETC_VF=m CONFIG_FSL_ENETC_IERB=m CONFIG_FSL_ENETC_MDIO=m CONFIG_FSL_ENETC_PTP_CLOCK=m CONFIG_FSL_ENETC_QOS=y CONFIG_NET_VENDOR_FUJITSU=y CONFIG_PCMCIA_FMVJ18X=m CONFIG_NET_VENDOR_FUNGIBLE=y CONFIG_FUN_CORE=m CONFIG_FUN_ETH=m CONFIG_NET_VENDOR_GOOGLE=y CONFIG_NET_VENDOR_HISILICON=y CONFIG_HIX5HD2_GMAC=m CONFIG_HISI_FEMAC=m CONFIG_HIP04_ETH=m CONFIG_HI13X1_GMAC=y CONFIG_HNS_MDIO=m CONFIG_HNS=m CONFIG_HNS_DSAF=m CONFIG_HNS_ENET=m CONFIG_HNS3=m CONFIG_HNS3_HCLGE=m CONFIG_HNS3_DCB=y CONFIG_HNS3_HCLGEVF=m CONFIG_HNS3_ENET=m CONFIG_NET_VENDOR_HUAWEI=y CONFIG_NET_VENDOR_I825XX=y CONFIG_NET_VENDOR_INTEL=y CONFIG_E100=m CONFIG_E1000=m CONFIG_E1000E=m CONFIG_IGB=m CONFIG_IGB_HWMON=y CONFIG_IGBVF=m CONFIG_IXGB=m CONFIG_IXGBE=m CONFIG_IXGBE_HWMON=y CONFIG_IXGBE_DCB=y CONFIG_IXGBE_IPSEC=y CONFIG_IXGBEVF=m CONFIG_IXGBEVF_IPSEC=y CONFIG_I40E=m CONFIG_I40E_DCB=y CONFIG_IAVF=m CONFIG_I40EVF=m CONFIG_ICE=m CONFIG_ICE_SWITCHDEV=y CONFIG_FM10K=m CONFIG_IGC=m CONFIG_NET_VENDOR_WANGXUN=y CONFIG_NGBE=m CONFIG_TXGBE=m CONFIG_JME=m CONFIG_KORINA=m CONFIG_NET_VENDOR_ADI=y CONFIG_ADIN1110=m CONFIG_NET_VENDOR_LITEX=y CONFIG_LITEX_LITEETH=m CONFIG_NET_VENDOR_MARVELL=y CONFIG_MV643XX_ETH=m CONFIG_MVMDIO=m CONFIG_MVNETA=m CONFIG_MVPP2=m CONFIG_MVPP2_PTP=y CONFIG_PXA168_ETH=m CONFIG_SKGE=m CONFIG_SKGE_DEBUG=y CONFIG_SKGE_GENESIS=y CONFIG_SKY2=m CONFIG_SKY2_DEBUG=y CONFIG_OCTEONTX2_MBOX=m CONFIG_OCTEONTX2_AF=m CONFIG_NDC_DIS_DYNAMIC_CACHING=y CONFIG_OCTEONTX2_PF=m CONFIG_OCTEONTX2_VF=m CONFIG_OCTEON_EP=m CONFIG_PRESTERA=m CONFIG_PRESTERA_PCI=m CONFIG_NET_VENDOR_MEDIATEK=y CONFIG_NET_MEDIATEK_SOC_WED=y CONFIG_NET_MEDIATEK_SOC=m CONFIG_NET_MEDIATEK_STAR_EMAC=m CONFIG_NET_VENDOR_MELLANOX=y CONFIG_MLX4_EN=m CONFIG_MLX4_EN_DCB=y CONFIG_MLX4_CORE=m CONFIG_MLX4_DEBUG=y CONFIG_MLX4_CORE_GEN2=y CONFIG_MLX5_CORE=m CONFIG_MLX5_FPGA=y CONFIG_MLX5_CORE_EN=y CONFIG_MLX5_EN_ARFS=y CONFIG_MLX5_EN_RXNFC=y CONFIG_MLX5_MPFS=y CONFIG_MLX5_ESWITCH=y CONFIG_MLX5_BRIDGE=y CONFIG_MLX5_CLS_ACT=y CONFIG_MLX5_TC_CT=y CONFIG_MLX5_TC_SAMPLE=y CONFIG_MLX5_CORE_EN_DCB=y CONFIG_MLX5_CORE_IPOIB=y CONFIG_MLX5_EN_MACSEC=y CONFIG_MLX5_EN_IPSEC=y CONFIG_MLX5_EN_TLS=y CONFIG_MLX5_SW_STEERING=y CONFIG_MLX5_SF=y CONFIG_MLX5_SF_MANAGER=y CONFIG_MLXSW_CORE=m CONFIG_MLXSW_CORE_HWMON=y CONFIG_MLXSW_CORE_THERMAL=y CONFIG_MLXSW_PCI=m CONFIG_MLXSW_I2C=m CONFIG_MLXSW_SPECTRUM=m CONFIG_MLXSW_SPECTRUM_DCB=y CONFIG_MLXSW_MINIMAL=m CONFIG_MLXFW=m CONFIG_MLXBF_GIGE=m CONFIG_NET_VENDOR_MICREL=y CONFIG_KS8842=m CONFIG_KS8851=m CONFIG_KS8851_MLL=m CONFIG_KSZ884X_PCI=m CONFIG_NET_VENDOR_MICROCHIP=y CONFIG_ENC28J60=m CONFIG_ENC28J60_WRITEVERIFY=y CONFIG_ENCX24J600=m CONFIG_LAN743X=m CONFIG_LAN966X_SWITCH=m CONFIG_SPARX5_SWITCH=m CONFIG_NET_VENDOR_MICROSEMI=y CONFIG_MSCC_OCELOT_SWITCH_LIB=m CONFIG_MSCC_OCELOT_SWITCH=m CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y CONFIG_MYRI10GE=m # CONFIG_FEALNX is not set CONFIG_NET_VENDOR_NI=y CONFIG_NI_XGE_MANAGEMENT_ENET=m CONFIG_NET_VENDOR_NATSEMI=y CONFIG_NATSEMI=m CONFIG_NS83820=m CONFIG_NET_VENDOR_NETERION=y CONFIG_S2IO=m CONFIG_NET_VENDOR_NETRONOME=y CONFIG_NFP=m CONFIG_NFP_APP_FLOWER=y CONFIG_NFP_APP_ABM_NIC=y CONFIG_NFP_DEBUG=y CONFIG_NET_VENDOR_8390=y CONFIG_PCMCIA_AXNET=m CONFIG_AX88796=m CONFIG_AX88796_93CX6=y CONFIG_NE2K_PCI=m CONFIG_PCMCIA_PCNET=m CONFIG_NET_VENDOR_NVIDIA=y CONFIG_FORCEDETH=m CONFIG_LPC_ENET=m CONFIG_NET_VENDOR_OKI=y CONFIG_PCH_GBE=m CONFIG_ETHOC=m CONFIG_NET_VENDOR_PACKET_ENGINES=y CONFIG_HAMACHI=m CONFIG_YELLOWFIN=m CONFIG_NET_VENDOR_PENSANDO=y CONFIG_IONIC=m CONFIG_NET_VENDOR_QLOGIC=y CONFIG_QLA3XXX=m CONFIG_QLCNIC=m CONFIG_QLCNIC_SRIOV=y CONFIG_QLCNIC_DCB=y CONFIG_QLCNIC_HWMON=y CONFIG_NETXEN_NIC=m CONFIG_QED=m CONFIG_QED_LL2=y CONFIG_QED_SRIOV=y CONFIG_QEDE=m CONFIG_QED_RDMA=y CONFIG_QED_ISCSI=y CONFIG_QED_FCOE=y CONFIG_QED_OOO=y CONFIG_NET_VENDOR_BROCADE=y CONFIG_BNA=m CONFIG_NET_VENDOR_QUALCOMM=y CONFIG_QCA7000=m CONFIG_QCA7000_SPI=m CONFIG_QCA7000_UART=m CONFIG_QCOM_EMAC=m CONFIG_RMNET=m CONFIG_NET_VENDOR_RDC=y CONFIG_R6040=m CONFIG_NET_VENDOR_REALTEK=y CONFIG_8139CP=m CONFIG_8139TOO=m CONFIG_8139TOO_PIO=y CONFIG_8139TOO_TUNE_TWISTER=y CONFIG_8139TOO_8129=y CONFIG_8139_OLD_RX_RESET=y CONFIG_R8169=m CONFIG_NET_VENDOR_RENESAS=y CONFIG_SH_ETH=m CONFIG_RAVB=m CONFIG_NET_VENDOR_ROCKER=y CONFIG_ROCKER=m CONFIG_NET_VENDOR_SAMSUNG=y CONFIG_SXGBE_ETH=m CONFIG_NET_VENDOR_SEEQ=y CONFIG_NET_VENDOR_SILAN=y CONFIG_SC92031=m CONFIG_NET_VENDOR_SIS=y CONFIG_SIS900=m CONFIG_SIS190=m CONFIG_NET_VENDOR_SOLARFLARE=y CONFIG_SFC=m CONFIG_SFC_MTD=y CONFIG_SFC_MCDI_MON=y CONFIG_SFC_SRIOV=y CONFIG_SFC_MCDI_LOGGING=y CONFIG_SFC_FALCON=m CONFIG_SFC_FALCON_MTD=y CONFIG_SFC_SIENA=m CONFIG_SFC_SIENA_MTD=y CONFIG_SFC_SIENA_MCDI_MON=y CONFIG_SFC_SIENA_SRIOV=y CONFIG_SFC_SIENA_MCDI_LOGGING=y CONFIG_NET_VENDOR_SMSC=y CONFIG_SMC91X=m CONFIG_PCMCIA_SMC91C92=m CONFIG_EPIC100=m # CONFIG_SMC911X is not set CONFIG_SMSC911X=m CONFIG_SMSC9420=m CONFIG_NET_VENDOR_SOCIONEXT=y CONFIG_SNI_AVE=m CONFIG_SNI_NETSEC=m CONFIG_NET_VENDOR_STMICRO=y CONFIG_STMMAC_ETH=m CONFIG_STMMAC_SELFTESTS=y CONFIG_STMMAC_PLATFORM=m CONFIG_DWMAC_DWC_QOS_ETH=m CONFIG_DWMAC_GENERIC=m CONFIG_DWMAC_ANARION=m CONFIG_DWMAC_INGENIC=m CONFIG_DWMAC_IPQ806X=m CONFIG_DWMAC_LPC18XX=m CONFIG_DWMAC_MEDIATEK=m CONFIG_DWMAC_MESON=m CONFIG_DWMAC_OXNAS=m CONFIG_DWMAC_QCOM_ETHQOS=m CONFIG_DWMAC_ROCKCHIP=m CONFIG_DWMAC_SOCFPGA=m CONFIG_DWMAC_STI=m CONFIG_DWMAC_STM32=m CONFIG_DWMAC_SUNXI=m CONFIG_DWMAC_SUN8I=m CONFIG_DWMAC_IMX8=m CONFIG_DWMAC_INTEL_PLAT=m CONFIG_DWMAC_VISCONTI=m CONFIG_DWMAC_LOONGSON=m CONFIG_STMMAC_PCI=m CONFIG_NET_VENDOR_SUN=y CONFIG_HAPPYMEAL=m CONFIG_SUNGEM=m CONFIG_CASSINI=m CONFIG_NIU=m CONFIG_NET_VENDOR_SUNPLUS=y CONFIG_SP7021_EMAC=m CONFIG_NET_VENDOR_SYNOPSYS=y CONFIG_DWC_XLGMAC=m CONFIG_DWC_XLGMAC_PCI=m CONFIG_NET_VENDOR_TEHUTI=y CONFIG_TEHUTI=m CONFIG_NET_VENDOR_TI=y CONFIG_TI_DAVINCI_EMAC=m CONFIG_TI_DAVINCI_MDIO=m CONFIG_TI_CPSW_PHY_SEL=y CONFIG_TI_CPSW=m CONFIG_TI_CPSW_SWITCHDEV=m CONFIG_TI_CPTS=m CONFIG_TLAN=m CONFIG_NET_VENDOR_VERTEXCOM=y CONFIG_MSE102X=m CONFIG_NET_VENDOR_VIA=y CONFIG_VIA_RHINE=m CONFIG_VIA_RHINE_MMIO=y CONFIG_VIA_VELOCITY=m CONFIG_NET_VENDOR_WIZNET=y CONFIG_WIZNET_W5100=m CONFIG_WIZNET_W5300=m # CONFIG_WIZNET_BUS_DIRECT is not set # CONFIG_WIZNET_BUS_INDIRECT is not set CONFIG_WIZNET_BUS_ANY=y CONFIG_WIZNET_W5100_SPI=m CONFIG_NET_VENDOR_XILINX=y CONFIG_XILINX_EMACLITE=m CONFIG_XILINX_AXI_EMAC=m CONFIG_XILINX_LL_TEMAC=m CONFIG_NET_VENDOR_XIRCOM=y CONFIG_PCMCIA_XIRC2PS=m CONFIG_FDDI=m CONFIG_DEFXX=m CONFIG_SKFP=m CONFIG_HIPPI=y CONFIG_ROADRUNNER=m CONFIG_ROADRUNNER_LARGE_RINGS=y CONFIG_QCOM_IPA=m CONFIG_NET_SB1000=m CONFIG_PHYLINK=m CONFIG_PHYLIB=m CONFIG_SWPHY=y CONFIG_LED_TRIGGER_PHY=y CONFIG_FIXED_PHY=m CONFIG_SFP=m # # MII PHY device drivers # CONFIG_AMD_PHY=m CONFIG_MESON_GXL_PHY=m CONFIG_ADIN_PHY=m CONFIG_ADIN1100_PHY=m CONFIG_AQUANTIA_PHY=m CONFIG_AX88796B_PHY=m CONFIG_BROADCOM_PHY=m CONFIG_BCM54140_PHY=m CONFIG_BCM63XX_PHY=m CONFIG_BCM7XXX_PHY=m CONFIG_BCM84881_PHY=m CONFIG_BCM87XX_PHY=m CONFIG_BCM_CYGNUS_PHY=m CONFIG_BCM_NET_PHYLIB=m CONFIG_BCM_NET_PHYPTP=m CONFIG_CICADA_PHY=m CONFIG_CORTINA_PHY=m CONFIG_DAVICOM_PHY=m CONFIG_ICPLUS_PHY=m CONFIG_LXT_PHY=m CONFIG_INTEL_XWAY_PHY=m CONFIG_LSI_ET1011C_PHY=m CONFIG_MARVELL_PHY=m CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88X2222_PHY=m CONFIG_MAXLINEAR_GPHY=m CONFIG_MEDIATEK_GE_PHY=m CONFIG_MICREL_PHY=m CONFIG_MICROCHIP_PHY=m CONFIG_MICROCHIP_T1_PHY=m CONFIG_MICROSEMI_PHY=m CONFIG_MOTORCOMM_PHY=m CONFIG_NATIONAL_PHY=m CONFIG_NXP_C45_TJA11XX_PHY=m CONFIG_NXP_TJA11XX_PHY=m CONFIG_AT803X_PHY=m CONFIG_QSEMI_PHY=m CONFIG_REALTEK_PHY=m CONFIG_RENESAS_PHY=m CONFIG_ROCKCHIP_PHY=m CONFIG_SMSC_PHY=m CONFIG_STE10XP=m CONFIG_TERANETICS_PHY=m CONFIG_DP83822_PHY=m CONFIG_DP83TC811_PHY=m CONFIG_DP83848_PHY=m CONFIG_DP83867_PHY=m CONFIG_DP83869_PHY=m CONFIG_DP83TD510_PHY=m CONFIG_VITESSE_PHY=m CONFIG_XILINX_GMII2RGMII=m CONFIG_MICREL_KS8995MA=m CONFIG_PSE_CONTROLLER=y CONFIG_PSE_REGULATOR=m CONFIG_CAN_DEV=m CONFIG_CAN_VCAN=m CONFIG_CAN_VXCAN=m CONFIG_CAN_NETLINK=y CONFIG_CAN_CALC_BITTIMING=y CONFIG_CAN_RX_OFFLOAD=y CONFIG_CAN_AT91=m CONFIG_CAN_CAN327=m CONFIG_CAN_FLEXCAN=m CONFIG_CAN_GRCAN=m CONFIG_CAN_JANZ_ICAN3=m CONFIG_CAN_KVASER_PCIEFD=m CONFIG_CAN_SLCAN=m CONFIG_CAN_SUN4I=m CONFIG_CAN_XILINXCAN=m # CONFIG_PCH_CAN is not set CONFIG_CAN_C_CAN=m CONFIG_CAN_C_CAN_PLATFORM=m CONFIG_CAN_C_CAN_PCI=m CONFIG_CAN_CC770=m CONFIG_CAN_CC770_ISA=m CONFIG_CAN_CC770_PLATFORM=m CONFIG_CAN_CTUCANFD=m CONFIG_CAN_CTUCANFD_PCI=m CONFIG_CAN_CTUCANFD_PLATFORM=m CONFIG_CAN_IFI_CANFD=m CONFIG_CAN_M_CAN=m CONFIG_CAN_M_CAN_PCI=m CONFIG_CAN_M_CAN_PLATFORM=m CONFIG_CAN_M_CAN_TCAN4X5X=m CONFIG_CAN_PEAK_PCIEFD=m CONFIG_CAN_RCAR=m CONFIG_CAN_RCAR_CANFD=m CONFIG_CAN_SJA1000=m CONFIG_CAN_EMS_PCI=m CONFIG_CAN_EMS_PCMCIA=m CONFIG_CAN_F81601=m CONFIG_CAN_KVASER_PCI=m CONFIG_CAN_PEAK_PCI=m CONFIG_CAN_PEAK_PCIEC=y CONFIG_CAN_PEAK_PCMCIA=m CONFIG_CAN_PLX_PCI=m CONFIG_CAN_SJA1000_ISA=m CONFIG_CAN_SJA1000_PLATFORM=m CONFIG_CAN_SOFTING=m CONFIG_CAN_SOFTING_CS=m # # CAN SPI interfaces # CONFIG_CAN_HI311X=m CONFIG_CAN_MCP251X=m CONFIG_CAN_MCP251XFD=m CONFIG_CAN_MCP251XFD_SANITY=y # end of CAN SPI interfaces # # CAN USB interfaces # CONFIG_CAN_8DEV_USB=m CONFIG_CAN_EMS_USB=m CONFIG_CAN_ESD_USB=m CONFIG_CAN_ETAS_ES58X=m CONFIG_CAN_GS_USB=m CONFIG_CAN_KVASER_USB=m CONFIG_CAN_MCBA_USB=m CONFIG_CAN_PEAK_USB=m CONFIG_CAN_UCAN=m # end of CAN USB interfaces CONFIG_CAN_DEBUG_DEVICES=y # # MCTP Device Drivers # CONFIG_MCTP_SERIAL=m CONFIG_MCTP_TRANSPORT_I2C=m # end of MCTP Device Drivers CONFIG_MDIO_DEVICE=m CONFIG_MDIO_BUS=m CONFIG_FWNODE_MDIO=m CONFIG_OF_MDIO=m CONFIG_ACPI_MDIO=m CONFIG_MDIO_DEVRES=m CONFIG_MDIO_SUN4I=m CONFIG_MDIO_XGENE=m CONFIG_MDIO_ASPEED=m CONFIG_MDIO_BITBANG=m CONFIG_MDIO_BCM_IPROC=m CONFIG_MDIO_BCM_UNIMAC=m CONFIG_MDIO_CAVIUM=m CONFIG_MDIO_GPIO=m CONFIG_MDIO_HISI_FEMAC=m CONFIG_MDIO_I2C=m CONFIG_MDIO_MVUSB=m CONFIG_MDIO_MSCC_MIIM=m CONFIG_MDIO_MOXART=m CONFIG_MDIO_OCTEON=m CONFIG_MDIO_IPQ4019=m CONFIG_MDIO_IPQ8064=m CONFIG_MDIO_THUNDER=m # # MDIO Multiplexers # CONFIG_MDIO_BUS_MUX=m CONFIG_MDIO_BUS_MUX_MESON_G12A=m CONFIG_MDIO_BUS_MUX_BCM6368=m CONFIG_MDIO_BUS_MUX_BCM_IPROC=m CONFIG_MDIO_BUS_MUX_GPIO=m CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m CONFIG_MDIO_BUS_MUX_MMIOREG=m # # PCS device drivers # CONFIG_PCS_XPCS=m CONFIG_PCS_LYNX=m CONFIG_PCS_RZN1_MIIC=m CONFIG_PCS_ALTERA_TSE=m # end of PCS device drivers CONFIG_PLIP=m CONFIG_PPP=m CONFIG_PPP_BSDCOMP=m CONFIG_PPP_DEFLATE=m CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=m CONFIG_PPP_MULTILINK=y CONFIG_PPPOATM=m CONFIG_PPPOE=m CONFIG_PPTP=m CONFIG_PPPOL2TP=m CONFIG_PPP_ASYNC=m CONFIG_PPP_SYNC_TTY=m CONFIG_SLIP=m CONFIG_SLHC=m CONFIG_SLIP_COMPRESSED=y CONFIG_SLIP_SMART=y CONFIG_SLIP_MODE_SLIP6=y # # Host-side USB support is needed for USB Network Adapter support # CONFIG_USB_NET_DRIVERS=m CONFIG_USB_CATC=m CONFIG_USB_KAWETH=m CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m CONFIG_USB_RTL8152=m CONFIG_USB_LAN78XX=m CONFIG_USB_USBNET=m CONFIG_USB_NET_AX8817X=m CONFIG_USB_NET_AX88179_178A=m CONFIG_USB_NET_CDCETHER=m CONFIG_USB_NET_CDC_EEM=m CONFIG_USB_NET_CDC_NCM=m CONFIG_USB_NET_HUAWEI_CDC_NCM=m CONFIG_USB_NET_CDC_MBIM=m CONFIG_USB_NET_DM9601=m CONFIG_USB_NET_SR9700=m CONFIG_USB_NET_SR9800=m CONFIG_USB_NET_SMSC75XX=m CONFIG_USB_NET_SMSC95XX=m CONFIG_USB_NET_GL620A=m CONFIG_USB_NET_NET1080=m CONFIG_USB_NET_PLUSB=m CONFIG_USB_NET_MCS7830=m CONFIG_USB_NET_RNDIS_HOST=m CONFIG_USB_NET_CDC_SUBSET_ENABLE=m CONFIG_USB_NET_CDC_SUBSET=m CONFIG_USB_ALI_M5632=y CONFIG_USB_AN2720=y CONFIG_USB_BELKIN=y CONFIG_USB_ARMLINUX=y CONFIG_USB_EPSON2888=y CONFIG_USB_KC2190=y CONFIG_USB_NET_ZAURUS=m CONFIG_USB_NET_CX82310_ETH=m CONFIG_USB_NET_KALMIA=m CONFIG_USB_NET_QMI_WWAN=m CONFIG_USB_HSO=m CONFIG_USB_NET_INT51X1=m CONFIG_USB_CDC_PHONET=m CONFIG_USB_IPHETH=m CONFIG_USB_SIERRA_NET=m CONFIG_USB_VL600=m CONFIG_USB_NET_CH9200=m CONFIG_USB_NET_AQC111=m CONFIG_USB_RTL8153_ECM=m CONFIG_WLAN=y CONFIG_WLAN_VENDOR_ADMTEK=y CONFIG_ADM8211=m CONFIG_ATH_COMMON=m CONFIG_WLAN_VENDOR_ATH=y CONFIG_ATH_DEBUG=y CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING=y CONFIG_ATH5K=m CONFIG_ATH5K_DEBUG=y CONFIG_ATH5K_PCI=y CONFIG_ATH5K_TEST_CHANNELS=y CONFIG_ATH9K_HW=m CONFIG_ATH9K_COMMON=m CONFIG_ATH9K_COMMON_DEBUG=y CONFIG_ATH9K_DFS_DEBUGFS=y CONFIG_ATH9K_BTCOEX_SUPPORT=y CONFIG_ATH9K=m CONFIG_ATH9K_PCI=y CONFIG_ATH9K_AHB=y CONFIG_ATH9K_DEBUGFS=y CONFIG_ATH9K_STATION_STATISTICS=y CONFIG_ATH9K_TX99=y CONFIG_ATH9K_DFS_CERTIFIED=y CONFIG_ATH9K_DYNACK=y CONFIG_ATH9K_WOW=y CONFIG_ATH9K_RFKILL=y CONFIG_ATH9K_CHANNEL_CONTEXT=y CONFIG_ATH9K_PCOEM=y CONFIG_ATH9K_PCI_NO_EEPROM=m CONFIG_ATH9K_HTC=m CONFIG_ATH9K_HTC_DEBUGFS=y CONFIG_ATH9K_HWRNG=y CONFIG_ATH9K_COMMON_SPECTRAL=y CONFIG_CARL9170=m CONFIG_CARL9170_LEDS=y CONFIG_CARL9170_DEBUGFS=y CONFIG_CARL9170_WPC=y CONFIG_CARL9170_HWRNG=y CONFIG_ATH6KL=m CONFIG_ATH6KL_SDIO=m CONFIG_ATH6KL_USB=m CONFIG_ATH6KL_DEBUG=y CONFIG_ATH6KL_REGDOMAIN=y CONFIG_AR5523=m CONFIG_WIL6210=m CONFIG_WIL6210_ISR_COR=y CONFIG_WIL6210_DEBUGFS=y CONFIG_ATH10K=m CONFIG_ATH10K_CE=y CONFIG_ATH10K_PCI=m CONFIG_ATH10K_AHB=y CONFIG_ATH10K_SDIO=m CONFIG_ATH10K_USB=m CONFIG_ATH10K_SNOC=m CONFIG_ATH10K_DEBUG=y CONFIG_ATH10K_DEBUGFS=y CONFIG_ATH10K_SPECTRAL=y CONFIG_ATH10K_DFS_CERTIFIED=y CONFIG_WCN36XX=m CONFIG_WCN36XX_DEBUGFS=y CONFIG_ATH11K=m CONFIG_ATH11K_AHB=m CONFIG_ATH11K_PCI=m CONFIG_ATH11K_DEBUG=y CONFIG_ATH11K_DEBUGFS=y CONFIG_ATH11K_SPECTRAL=y CONFIG_WLAN_VENDOR_ATMEL=y CONFIG_ATMEL=m CONFIG_PCI_ATMEL=m CONFIG_PCMCIA_ATMEL=m CONFIG_AT76C50X_USB=m CONFIG_WLAN_VENDOR_BROADCOM=y CONFIG_B43=m CONFIG_B43_BCMA=y CONFIG_B43_SSB=y CONFIG_B43_BUSES_BCMA_AND_SSB=y # CONFIG_B43_BUSES_BCMA is not set # CONFIG_B43_BUSES_SSB is not set CONFIG_B43_PCI_AUTOSELECT=y CONFIG_B43_PCICORE_AUTOSELECT=y CONFIG_B43_SDIO=y CONFIG_B43_BCMA_PIO=y CONFIG_B43_PIO=y CONFIG_B43_PHY_G=y CONFIG_B43_PHY_N=y CONFIG_B43_PHY_LP=y CONFIG_B43_PHY_HT=y CONFIG_B43_LEDS=y CONFIG_B43_HWRNG=y CONFIG_B43_DEBUG=y CONFIG_B43LEGACY=m CONFIG_B43LEGACY_PCI_AUTOSELECT=y CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y CONFIG_B43LEGACY_LEDS=y CONFIG_B43LEGACY_HWRNG=y CONFIG_B43LEGACY_DEBUG=y CONFIG_B43LEGACY_DMA=y CONFIG_B43LEGACY_PIO=y CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y # CONFIG_B43LEGACY_DMA_MODE is not set # CONFIG_B43LEGACY_PIO_MODE is not set CONFIG_BRCMUTIL=m CONFIG_BRCMSMAC=m CONFIG_BRCMSMAC_LEDS=y CONFIG_BRCMFMAC=m CONFIG_BRCMFMAC_PROTO_BCDC=y CONFIG_BRCMFMAC_PROTO_MSGBUF=y CONFIG_BRCMFMAC_SDIO=y CONFIG_BRCMFMAC_USB=y CONFIG_BRCMFMAC_PCIE=y CONFIG_BRCM_TRACING=y CONFIG_BRCMDBG=y CONFIG_WLAN_VENDOR_CISCO=y CONFIG_AIRO_CS=m CONFIG_WLAN_VENDOR_INTEL=y CONFIG_IPW2100=m CONFIG_IPW2100_MONITOR=y CONFIG_IPW2100_DEBUG=y CONFIG_IPW2200=m CONFIG_IPW2200_MONITOR=y CONFIG_IPW2200_RADIOTAP=y CONFIG_IPW2200_PROMISCUOUS=y CONFIG_IPW2200_QOS=y CONFIG_IPW2200_DEBUG=y CONFIG_LIBIPW=m CONFIG_LIBIPW_DEBUG=y CONFIG_IWLEGACY=m CONFIG_IWL4965=m CONFIG_IWL3945=m # # iwl3945 / iwl4965 Debugging Options # CONFIG_IWLEGACY_DEBUG=y CONFIG_IWLEGACY_DEBUGFS=y # end of iwl3945 / iwl4965 Debugging Options CONFIG_IWLWIFI=m CONFIG_IWLWIFI_LEDS=y CONFIG_IWLDVM=m CONFIG_IWLMVM=m CONFIG_IWLWIFI_OPMODE_MODULAR=y # # Debugging Options # CONFIG_IWLWIFI_DEBUG=y CONFIG_IWLWIFI_DEBUGFS=y # end of Debugging Options CONFIG_WLAN_VENDOR_INTERSIL=y CONFIG_HOSTAP=m CONFIG_HOSTAP_FIRMWARE=y CONFIG_HOSTAP_FIRMWARE_NVRAM=y CONFIG_HOSTAP_PLX=m CONFIG_HOSTAP_PCI=m CONFIG_HOSTAP_CS=m CONFIG_HERMES=m CONFIG_HERMES_PRISM=y CONFIG_HERMES_CACHE_FW_ON_INIT=y CONFIG_PLX_HERMES=m CONFIG_TMD_HERMES=m CONFIG_NORTEL_HERMES=m CONFIG_PCI_HERMES=m CONFIG_PCMCIA_HERMES=m CONFIG_PCMCIA_SPECTRUM=m CONFIG_ORINOCO_USB=m CONFIG_P54_COMMON=m CONFIG_P54_USB=m CONFIG_P54_PCI=m CONFIG_P54_SPI=m CONFIG_P54_SPI_DEFAULT_EEPROM=y CONFIG_P54_LEDS=y CONFIG_WLAN_VENDOR_MARVELL=y CONFIG_LIBERTAS=m CONFIG_LIBERTAS_USB=m CONFIG_LIBERTAS_CS=m CONFIG_LIBERTAS_SDIO=m CONFIG_LIBERTAS_SPI=m CONFIG_LIBERTAS_DEBUG=y CONFIG_LIBERTAS_MESH=y CONFIG_LIBERTAS_THINFIRM=m CONFIG_LIBERTAS_THINFIRM_DEBUG=y CONFIG_LIBERTAS_THINFIRM_USB=m CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m CONFIG_MWIFIEX_PCIE=m CONFIG_MWIFIEX_USB=m CONFIG_MWL8K=m CONFIG_WLAN_VENDOR_MEDIATEK=y CONFIG_MT7601U=m CONFIG_MT76_CORE=m CONFIG_MT76_LEDS=y CONFIG_MT76_USB=m CONFIG_MT76_SDIO=m CONFIG_MT76x02_LIB=m CONFIG_MT76x02_USB=m CONFIG_MT76_CONNAC_LIB=m CONFIG_MT76x0_COMMON=m CONFIG_MT76x0U=m CONFIG_MT76x0E=m CONFIG_MT76x2_COMMON=m CONFIG_MT76x2E=m CONFIG_MT76x2U=m CONFIG_MT7603E=m CONFIG_MT7615_COMMON=m CONFIG_MT7615E=m CONFIG_MT7622_WMAC=y CONFIG_MT7663_USB_SDIO_COMMON=m CONFIG_MT7663U=m CONFIG_MT7663S=m CONFIG_MT7915E=m CONFIG_MT7986_WMAC=y CONFIG_MT7921_COMMON=m CONFIG_MT7921E=m CONFIG_MT7921S=m CONFIG_MT7921U=m CONFIG_WLAN_VENDOR_MICROCHIP=y CONFIG_WILC1000=m CONFIG_WILC1000_SDIO=m CONFIG_WILC1000_SPI=m CONFIG_WILC1000_HW_OOB_INTR=y CONFIG_WLAN_VENDOR_PURELIFI=y CONFIG_PLFXLC=m CONFIG_WLAN_VENDOR_RALINK=y CONFIG_RT2X00=m CONFIG_RT2400PCI=m CONFIG_RT2500PCI=m CONFIG_RT61PCI=m CONFIG_RT2800PCI=m CONFIG_RT2800PCI_RT33XX=y CONFIG_RT2800PCI_RT35XX=y CONFIG_RT2800PCI_RT53XX=y CONFIG_RT2800PCI_RT3290=y CONFIG_RT2500USB=m CONFIG_RT73USB=m CONFIG_RT2800USB=m CONFIG_RT2800USB_RT33XX=y CONFIG_RT2800USB_RT35XX=y CONFIG_RT2800USB_RT3573=y CONFIG_RT2800USB_RT53XX=y CONFIG_RT2800USB_RT55XX=y CONFIG_RT2800USB_UNKNOWN=y CONFIG_RT2800_LIB=m CONFIG_RT2800_LIB_MMIO=m CONFIG_RT2X00_LIB_MMIO=m CONFIG_RT2X00_LIB_PCI=m CONFIG_RT2X00_LIB_USB=m CONFIG_RT2X00_LIB=m CONFIG_RT2X00_LIB_FIRMWARE=y CONFIG_RT2X00_LIB_CRYPTO=y CONFIG_RT2X00_LIB_LEDS=y CONFIG_RT2X00_LIB_DEBUGFS=y CONFIG_RT2X00_DEBUG=y CONFIG_WLAN_VENDOR_REALTEK=y CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8187_LEDS=y CONFIG_RTL_CARDS=m CONFIG_RTL8192CE=m CONFIG_RTL8192SE=m CONFIG_RTL8192DE=m CONFIG_RTL8723AE=m CONFIG_RTL8723BE=m CONFIG_RTL8188EE=m CONFIG_RTL8192EE=m CONFIG_RTL8821AE=m CONFIG_RTL8192CU=m CONFIG_RTLWIFI=m CONFIG_RTLWIFI_PCI=m CONFIG_RTLWIFI_USB=m CONFIG_RTLWIFI_DEBUG=y CONFIG_RTL8192C_COMMON=m CONFIG_RTL8723_COMMON=m CONFIG_RTLBTCOEXIST=m CONFIG_RTL8XXXU=m CONFIG_RTL8XXXU_UNTESTED=y CONFIG_RTW88=m CONFIG_RTW88_CORE=m CONFIG_RTW88_PCI=m CONFIG_RTW88_8822B=m CONFIG_RTW88_8822C=m CONFIG_RTW88_8723D=m CONFIG_RTW88_8821C=m CONFIG_RTW88_8822BE=m CONFIG_RTW88_8822CE=m CONFIG_RTW88_8723DE=m CONFIG_RTW88_8821CE=m CONFIG_RTW88_DEBUG=y CONFIG_RTW88_DEBUGFS=y CONFIG_RTW89=m CONFIG_RTW89_CORE=m CONFIG_RTW89_PCI=m CONFIG_RTW89_8852A=m CONFIG_RTW89_8852C=m CONFIG_RTW89_8852AE=m CONFIG_RTW89_8852CE=m CONFIG_RTW89_DEBUG=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89_DEBUGFS=y CONFIG_WLAN_VENDOR_RSI=y CONFIG_RSI_91X=m CONFIG_RSI_DEBUGFS=y CONFIG_RSI_SDIO=m CONFIG_RSI_USB=m CONFIG_RSI_COEX=y CONFIG_WLAN_VENDOR_SILABS=y CONFIG_WFX=m CONFIG_WLAN_VENDOR_ST=y CONFIG_CW1200=m CONFIG_CW1200_WLAN_SDIO=m CONFIG_CW1200_WLAN_SPI=m CONFIG_WLAN_VENDOR_TI=y CONFIG_WL1251=m CONFIG_WL1251_SPI=m CONFIG_WL1251_SDIO=m CONFIG_WL12XX=m CONFIG_WL18XX=m CONFIG_WLCORE=m CONFIG_WLCORE_SPI=m CONFIG_WLCORE_SDIO=m CONFIG_WILINK_PLATFORM_DATA=y CONFIG_WLAN_VENDOR_ZYDAS=y CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m CONFIG_ZD1211RW_DEBUG=y CONFIG_WLAN_VENDOR_QUANTENNA=y CONFIG_QTNFMAC=m CONFIG_QTNFMAC_PCIE=m CONFIG_PCMCIA_RAYCS=m CONFIG_PCMCIA_WL3501=m CONFIG_MAC80211_HWSIM=m CONFIG_USB_NET_RNDIS_WLAN=m CONFIG_VIRT_WIFI=m CONFIG_WAN=y CONFIG_HDLC=m CONFIG_HDLC_RAW=m CONFIG_HDLC_RAW_ETH=m CONFIG_HDLC_CISCO=m CONFIG_HDLC_FR=m CONFIG_HDLC_PPP=m CONFIG_HDLC_X25=m CONFIG_PCI200SYN=m CONFIG_WANXL=m CONFIG_PC300TOO=m CONFIG_FARSYNC=m CONFIG_FSL_UCC_HDLC=m CONFIG_SLIC_DS26522=m CONFIG_LAPBETHER=m CONFIG_IEEE802154_DRIVERS=m CONFIG_IEEE802154_FAKELB=m CONFIG_IEEE802154_AT86RF230=m CONFIG_IEEE802154_MRF24J40=m CONFIG_IEEE802154_CC2520=m CONFIG_IEEE802154_ATUSB=m CONFIG_IEEE802154_ADF7242=m CONFIG_IEEE802154_CA8210=m CONFIG_IEEE802154_CA8210_DEBUGFS=y CONFIG_IEEE802154_MCR20A=m CONFIG_IEEE802154_HWSIM=m # # Wireless WAN # CONFIG_WWAN=m CONFIG_WWAN_DEBUGFS=y CONFIG_WWAN_HWSIM=m CONFIG_MHI_WWAN_CTRL=m CONFIG_MHI_WWAN_MBIM=m CONFIG_QCOM_BAM_DMUX=m CONFIG_RPMSG_WWAN_CTRL=m CONFIG_IOSM=m CONFIG_MTK_T7XX=m # end of Wireless WAN CONFIG_VMXNET3=m CONFIG_FUJITSU_ES=m CONFIG_USB4_NET=m CONFIG_NETDEVSIM=m CONFIG_NET_FAILOVER=m CONFIG_ISDN=y CONFIG_ISDN_CAPI=y CONFIG_CAPI_TRACE=y CONFIG_ISDN_CAPI_MIDDLEWARE=y CONFIG_MISDN=m CONFIG_MISDN_DSP=m CONFIG_MISDN_L1OIP=m # # mISDN hardware drivers # CONFIG_MISDN_HFCPCI=m CONFIG_MISDN_HFCMULTI=m CONFIG_MISDN_HFCUSB=m CONFIG_MISDN_AVMFRITZ=m CONFIG_MISDN_SPEEDFAX=m CONFIG_MISDN_INFINEON=m CONFIG_MISDN_W6692=m CONFIG_MISDN_NETJET=m CONFIG_MISDN_HDLC=m CONFIG_MISDN_IPAC=m CONFIG_MISDN_ISAR=m # # Input device support # CONFIG_INPUT=y CONFIG_INPUT_LEDS=m CONFIG_INPUT_FF_MEMLESS=m CONFIG_INPUT_SPARSEKMAP=m CONFIG_INPUT_MATRIXKMAP=m CONFIG_INPUT_VIVALDIFMAP=m # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=m CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 CONFIG_INPUT_JOYDEV=m CONFIG_INPUT_EVDEV=m CONFIG_INPUT_EVBUG=m # # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ADC=m CONFIG_KEYBOARD_ADP5588=m CONFIG_KEYBOARD_ADP5589=m CONFIG_KEYBOARD_APPLESPI=m CONFIG_KEYBOARD_ATKBD=m CONFIG_KEYBOARD_QT1050=m CONFIG_KEYBOARD_QT1070=m CONFIG_KEYBOARD_QT2160=m CONFIG_KEYBOARD_CLPS711X=m CONFIG_KEYBOARD_DLINK_DIR685=m CONFIG_KEYBOARD_LKKBD=m CONFIG_KEYBOARD_EP93XX=m CONFIG_KEYBOARD_GPIO=m CONFIG_KEYBOARD_GPIO_POLLED=m CONFIG_KEYBOARD_TCA6416=m CONFIG_KEYBOARD_TCA8418=m CONFIG_KEYBOARD_MATRIX=m CONFIG_KEYBOARD_LM8323=m CONFIG_KEYBOARD_LM8333=m CONFIG_KEYBOARD_MAX7359=m CONFIG_KEYBOARD_MCS=m CONFIG_KEYBOARD_MPR121=m CONFIG_KEYBOARD_SNVS_PWRKEY=m CONFIG_KEYBOARD_IMX=m CONFIG_KEYBOARD_IMX_SC_KEY=m CONFIG_KEYBOARD_NEWTON=m CONFIG_KEYBOARD_OPENCORES=m CONFIG_KEYBOARD_PINEPHONE=m CONFIG_KEYBOARD_PMIC8XXX=m CONFIG_KEYBOARD_SAMSUNG=m CONFIG_KEYBOARD_GOLDFISH_EVENTS=m CONFIG_KEYBOARD_STOWAWAY=m CONFIG_KEYBOARD_ST_KEYSCAN=m CONFIG_KEYBOARD_SUNKBD=m CONFIG_KEYBOARD_SH_KEYSC=m CONFIG_KEYBOARD_STMPE=m CONFIG_KEYBOARD_IQS62X=m CONFIG_KEYBOARD_OMAP4=m CONFIG_KEYBOARD_TM2_TOUCHKEY=m CONFIG_KEYBOARD_XTKBD=m CONFIG_KEYBOARD_CROS_EC=m CONFIG_KEYBOARD_CAP11XX=m CONFIG_KEYBOARD_BCM=m CONFIG_KEYBOARD_MT6779=m CONFIG_KEYBOARD_MTK_PMIC=m CONFIG_KEYBOARD_CYPRESS_SF=m CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=m CONFIG_MOUSE_PS2_ALPS=y CONFIG_MOUSE_PS2_BYD=y CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y CONFIG_MOUSE_PS2_CYPRESS=y CONFIG_MOUSE_PS2_TRACKPOINT=y CONFIG_MOUSE_PS2_ELANTECH=y CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y CONFIG_MOUSE_PS2_SENTELIC=y CONFIG_MOUSE_PS2_TOUCHKIT=y CONFIG_MOUSE_PS2_FOCALTECH=y CONFIG_MOUSE_PS2_SMBUS=y CONFIG_MOUSE_SERIAL=m CONFIG_MOUSE_APPLETOUCH=m CONFIG_MOUSE_BCM5974=m CONFIG_MOUSE_CYAPA=m CONFIG_MOUSE_ELAN_I2C=m CONFIG_MOUSE_ELAN_I2C_I2C=y CONFIG_MOUSE_ELAN_I2C_SMBUS=y CONFIG_MOUSE_VSXXXAA=m CONFIG_MOUSE_GPIO=m CONFIG_MOUSE_SYNAPTICS_I2C=m CONFIG_MOUSE_SYNAPTICS_USB=m CONFIG_INPUT_JOYSTICK=y CONFIG_JOYSTICK_ANALOG=m CONFIG_JOYSTICK_A3D=m CONFIG_JOYSTICK_ADC=m CONFIG_JOYSTICK_ADI=m CONFIG_JOYSTICK_COBRA=m CONFIG_JOYSTICK_GF2K=m CONFIG_JOYSTICK_GRIP=m CONFIG_JOYSTICK_GRIP_MP=m CONFIG_JOYSTICK_GUILLEMOT=m CONFIG_JOYSTICK_INTERACT=m CONFIG_JOYSTICK_SIDEWINDER=m CONFIG_JOYSTICK_TMDC=m CONFIG_JOYSTICK_IFORCE=m CONFIG_JOYSTICK_IFORCE_USB=m CONFIG_JOYSTICK_IFORCE_232=m CONFIG_JOYSTICK_WARRIOR=m CONFIG_JOYSTICK_MAGELLAN=m CONFIG_JOYSTICK_SPACEORB=m CONFIG_JOYSTICK_SPACEBALL=m CONFIG_JOYSTICK_STINGER=m CONFIG_JOYSTICK_TWIDJOY=m CONFIG_JOYSTICK_ZHENHUA=m CONFIG_JOYSTICK_DB9=m CONFIG_JOYSTICK_GAMECON=m CONFIG_JOYSTICK_TURBOGRAFX=m CONFIG_JOYSTICK_AS5011=m CONFIG_JOYSTICK_JOYDUMP=m CONFIG_JOYSTICK_XPAD=m CONFIG_JOYSTICK_XPAD_FF=y CONFIG_JOYSTICK_XPAD_LEDS=y CONFIG_JOYSTICK_PSXPAD_SPI=m CONFIG_JOYSTICK_PSXPAD_SPI_FF=y CONFIG_JOYSTICK_PXRC=m CONFIG_JOYSTICK_QWIIC=m CONFIG_JOYSTICK_FSIA6B=m CONFIG_JOYSTICK_SENSEHAT=m CONFIG_INPUT_TABLET=y CONFIG_TABLET_USB_ACECAD=m CONFIG_TABLET_USB_AIPTEK=m CONFIG_TABLET_USB_HANWANG=m CONFIG_TABLET_USB_KBTAB=m CONFIG_TABLET_USB_PEGASUS=m CONFIG_TABLET_SERIAL_WACOM4=m CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=m CONFIG_TOUCHSCREEN_AD7877=m CONFIG_TOUCHSCREEN_AD7879=m CONFIG_TOUCHSCREEN_AD7879_I2C=m CONFIG_TOUCHSCREEN_AD7879_SPI=m CONFIG_TOUCHSCREEN_ADC=m CONFIG_TOUCHSCREEN_AR1021_I2C=m CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y CONFIG_TOUCHSCREEN_AUO_PIXCIR=m CONFIG_TOUCHSCREEN_BU21013=m CONFIG_TOUCHSCREEN_BU21029=m CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m CONFIG_TOUCHSCREEN_CHIPONE_ICN8505=m CONFIG_TOUCHSCREEN_CY8CTMA140=m CONFIG_TOUCHSCREEN_CY8CTMG110=m CONFIG_TOUCHSCREEN_CYTTSP_CORE=m CONFIG_TOUCHSCREEN_CYTTSP_I2C=m CONFIG_TOUCHSCREEN_CYTTSP_SPI=m CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m CONFIG_TOUCHSCREEN_DA9052=m CONFIG_TOUCHSCREEN_DYNAPRO=m CONFIG_TOUCHSCREEN_HAMPSHIRE=m CONFIG_TOUCHSCREEN_EETI=m CONFIG_TOUCHSCREEN_EGALAX=m CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m CONFIG_TOUCHSCREEN_EXC3000=m CONFIG_TOUCHSCREEN_FUJITSU=m CONFIG_TOUCHSCREEN_GOODIX=m CONFIG_TOUCHSCREEN_HIDEEP=m CONFIG_TOUCHSCREEN_HYCON_HY46XX=m CONFIG_TOUCHSCREEN_ILI210X=m CONFIG_TOUCHSCREEN_ILITEK=m CONFIG_TOUCHSCREEN_IPROC=m CONFIG_TOUCHSCREEN_S6SY761=m CONFIG_TOUCHSCREEN_GUNZE=m CONFIG_TOUCHSCREEN_EKTF2127=m CONFIG_TOUCHSCREEN_ELAN=m CONFIG_TOUCHSCREEN_ELO=m CONFIG_TOUCHSCREEN_WACOM_W8001=m CONFIG_TOUCHSCREEN_WACOM_I2C=m CONFIG_TOUCHSCREEN_MAX11801=m CONFIG_TOUCHSCREEN_MCS5000=m CONFIG_TOUCHSCREEN_MMS114=m CONFIG_TOUCHSCREEN_MELFAS_MIP4=m CONFIG_TOUCHSCREEN_MSG2638=m CONFIG_TOUCHSCREEN_MTOUCH=m CONFIG_TOUCHSCREEN_IMAGIS=m CONFIG_TOUCHSCREEN_IMX6UL_TSC=m CONFIG_TOUCHSCREEN_INEXIO=m CONFIG_TOUCHSCREEN_MK712=m CONFIG_TOUCHSCREEN_PENMOUNT=m CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m CONFIG_TOUCHSCREEN_MIGOR=m CONFIG_TOUCHSCREEN_TOUCHRIGHT=m CONFIG_TOUCHSCREEN_TOUCHWIN=m CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m CONFIG_TOUCHSCREEN_PIXCIR=m CONFIG_TOUCHSCREEN_WDT87XX_I2C=m CONFIG_TOUCHSCREEN_WM831X=m CONFIG_TOUCHSCREEN_USB_COMPOSITE=m CONFIG_TOUCHSCREEN_MXS_LRADC=m CONFIG_TOUCHSCREEN_MX25=m CONFIG_TOUCHSCREEN_MC13783=m CONFIG_TOUCHSCREEN_USB_EGALAX=y CONFIG_TOUCHSCREEN_USB_PANJIT=y CONFIG_TOUCHSCREEN_USB_3M=y CONFIG_TOUCHSCREEN_USB_ITM=y CONFIG_TOUCHSCREEN_USB_ETURBO=y CONFIG_TOUCHSCREEN_USB_GUNZE=y CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y CONFIG_TOUCHSCREEN_USB_IRTOUCH=y CONFIG_TOUCHSCREEN_USB_IDEALTEK=y CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y CONFIG_TOUCHSCREEN_USB_GOTOP=y CONFIG_TOUCHSCREEN_USB_JASTEC=y CONFIG_TOUCHSCREEN_USB_ELO=y CONFIG_TOUCHSCREEN_USB_E2I=y CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y CONFIG_TOUCHSCREEN_USB_NEXIO=y CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y CONFIG_TOUCHSCREEN_TOUCHIT213=m CONFIG_TOUCHSCREEN_TS4800=m CONFIG_TOUCHSCREEN_TSC_SERIO=m CONFIG_TOUCHSCREEN_TSC200X_CORE=m CONFIG_TOUCHSCREEN_TSC2004=m CONFIG_TOUCHSCREEN_TSC2005=m CONFIG_TOUCHSCREEN_TSC2007=m CONFIG_TOUCHSCREEN_TSC2007_IIO=y CONFIG_TOUCHSCREEN_PCAP=m CONFIG_TOUCHSCREEN_RM_TS=m CONFIG_TOUCHSCREEN_SILEAD=m CONFIG_TOUCHSCREEN_SIS_I2C=m CONFIG_TOUCHSCREEN_ST1232=m CONFIG_TOUCHSCREEN_STMFTS=m CONFIG_TOUCHSCREEN_STMPE=m CONFIG_TOUCHSCREEN_SUN4I=m CONFIG_TOUCHSCREEN_SUR40=m CONFIG_TOUCHSCREEN_SURFACE3_SPI=m CONFIG_TOUCHSCREEN_SX8654=m CONFIG_TOUCHSCREEN_TPS6507X=m CONFIG_TOUCHSCREEN_ZET6223=m CONFIG_TOUCHSCREEN_ZFORCE=m CONFIG_TOUCHSCREEN_COLIBRI_VF50=m CONFIG_TOUCHSCREEN_ROHM_BU21023=m CONFIG_TOUCHSCREEN_IQS5XX=m CONFIG_TOUCHSCREEN_ZINITIX=m CONFIG_INPUT_MISC=y CONFIG_INPUT_88PM80X_ONKEY=m CONFIG_INPUT_AD714X=m CONFIG_INPUT_AD714X_I2C=m CONFIG_INPUT_AD714X_SPI=m CONFIG_INPUT_ARIEL_PWRBUTTON=m CONFIG_INPUT_ATC260X_ONKEY=m CONFIG_INPUT_ATMEL_CAPTOUCH=m CONFIG_INPUT_BMA150=m CONFIG_INPUT_E3X0_BUTTON=m CONFIG_INPUT_PM8941_PWRKEY=m CONFIG_INPUT_PM8XXX_VIBRATOR=m CONFIG_INPUT_PMIC8XXX_PWRKEY=m CONFIG_INPUT_MAX77650_ONKEY=m CONFIG_INPUT_MAX77693_HAPTIC=m CONFIG_INPUT_MC13783_PWRBUTTON=m CONFIG_INPUT_MMA8450=m CONFIG_INPUT_GPIO_BEEPER=m CONFIG_INPUT_GPIO_DECODER=m CONFIG_INPUT_GPIO_VIBRA=m CONFIG_INPUT_CPCAP_PWRBUTTON=m CONFIG_INPUT_ATI_REMOTE2=m CONFIG_INPUT_KEYSPAN_REMOTE=m CONFIG_INPUT_KXTJ9=m CONFIG_INPUT_POWERMATE=m CONFIG_INPUT_YEALINK=m CONFIG_INPUT_CM109=m CONFIG_INPUT_REGULATOR_HAPTIC=m CONFIG_INPUT_RETU_PWRBUTTON=m CONFIG_INPUT_TPS65218_PWRBUTTON=m CONFIG_INPUT_AXP20X_PEK=m CONFIG_INPUT_UINPUT=m CONFIG_INPUT_PCF50633_PMU=m CONFIG_INPUT_PCF8574=m CONFIG_INPUT_PWM_BEEPER=m CONFIG_INPUT_PWM_VIBRA=m CONFIG_INPUT_RK805_PWRKEY=m CONFIG_INPUT_GPIO_ROTARY_ENCODER=m CONFIG_INPUT_DA7280_HAPTICS=m CONFIG_INPUT_DA9052_ONKEY=m CONFIG_INPUT_DA9063_ONKEY=m CONFIG_INPUT_WM831X_ON=m CONFIG_INPUT_PCAP=m CONFIG_INPUT_ADXL34X=m CONFIG_INPUT_ADXL34X_I2C=m CONFIG_INPUT_ADXL34X_SPI=m CONFIG_INPUT_IBM_PANEL=m CONFIG_INPUT_IMS_PCU=m CONFIG_INPUT_IQS269A=m CONFIG_INPUT_IQS626A=m CONFIG_INPUT_IQS7222=m CONFIG_INPUT_CMA3000=m CONFIG_INPUT_CMA3000_I2C=m CONFIG_INPUT_IDEAPAD_SLIDEBAR=m CONFIG_INPUT_SOC_BUTTON_ARRAY=m CONFIG_INPUT_DRV260X_HAPTICS=m CONFIG_INPUT_DRV2665_HAPTICS=m CONFIG_INPUT_DRV2667_HAPTICS=m CONFIG_INPUT_HISI_POWERKEY=m CONFIG_INPUT_RAVE_SP_PWRBUTTON=m CONFIG_INPUT_SC27XX_VIBRA=m CONFIG_INPUT_RT5120_PWRKEY=m CONFIG_RMI4_CORE=m CONFIG_RMI4_I2C=m CONFIG_RMI4_SPI=m CONFIG_RMI4_SMB=m CONFIG_RMI4_F03=y CONFIG_RMI4_F03_SERIO=m CONFIG_RMI4_2D_SENSOR=y CONFIG_RMI4_F11=y CONFIG_RMI4_F12=y CONFIG_RMI4_F30=y CONFIG_RMI4_F34=y CONFIG_RMI4_F3A=y CONFIG_RMI4_F54=y CONFIG_RMI4_F55=y # # Hardware I/O ports # CONFIG_SERIO=m CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y CONFIG_SERIO_I8042=m CONFIG_SERIO_SERPORT=m CONFIG_SERIO_PARKBD=m CONFIG_SERIO_PCIPS2=m CONFIG_SERIO_LIBPS2=m CONFIG_SERIO_RAW=m CONFIG_SERIO_ALTERA_PS2=m CONFIG_SERIO_PS2MULT=m CONFIG_SERIO_ARC_PS2=m CONFIG_SERIO_APBPS2=m CONFIG_SERIO_OLPC_APSP=m CONFIG_SERIO_SUN4I_PS2=m CONFIG_SERIO_GPIO_PS2=m CONFIG_USERIO=m CONFIG_GAMEPORT=m CONFIG_GAMEPORT_NS558=m CONFIG_GAMEPORT_L4=m CONFIG_GAMEPORT_EMU10K1=m CONFIG_GAMEPORT_FM801=m # end of Hardware I/O ports # end of Input device support # # Character devices # CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 CONFIG_LDISC_AUTOLOAD=y # # Serial drivers # CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=m CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_PNP=y CONFIG_SERIAL_8250_16550A_VARIANTS=y CONFIG_SERIAL_8250_FINTEK=y CONFIG_SERIAL_8250_DMA=y CONFIG_SERIAL_8250_PCI=m CONFIG_SERIAL_8250_EXAR=m CONFIG_SERIAL_8250_CS=m CONFIG_SERIAL_8250_MEN_MCB=m CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_ASPEED_VUART=m CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_BCM2835AUX=m CONFIG_SERIAL_8250_DW=m CONFIG_SERIAL_8250_EM=m CONFIG_SERIAL_8250_IOC3=m CONFIG_SERIAL_8250_RT288X=y CONFIG_SERIAL_8250_OMAP=m CONFIG_SERIAL_8250_LPC18XX=m CONFIG_SERIAL_8250_MT6577=m CONFIG_SERIAL_8250_UNIPHIER=m CONFIG_SERIAL_8250_INGENIC=m CONFIG_SERIAL_8250_LPSS=m CONFIG_SERIAL_8250_MID=m CONFIG_SERIAL_8250_PERICOM=m CONFIG_SERIAL_8250_PXA=m CONFIG_SERIAL_8250_TEGRA=m CONFIG_SERIAL_8250_BCM7271=m CONFIG_SERIAL_OF_PLATFORM=m # # Non-8250 serial port support # CONFIG_SERIAL_AMBA_PL010=m CONFIG_SERIAL_ATMEL=y CONFIG_SERIAL_ATMEL_CONSOLE=y CONFIG_SERIAL_ATMEL_PDC=y CONFIG_SERIAL_ATMEL_TTYAT=y CONFIG_SERIAL_MESON=m CONFIG_SERIAL_MESON_CONSOLE=y CONFIG_SERIAL_CLPS711X=m CONFIG_SERIAL_SAMSUNG=m CONFIG_SERIAL_SAMSUNG_UARTS_4=y CONFIG_SERIAL_SAMSUNG_UARTS=4 CONFIG_SERIAL_SAMSUNG_CONSOLE=y CONFIG_SERIAL_TEGRA=m CONFIG_SERIAL_TEGRA_TCU=m CONFIG_SERIAL_MAX3100=m CONFIG_SERIAL_MAX310X=m CONFIG_SERIAL_IMX=m CONFIG_SERIAL_IMX_CONSOLE=m CONFIG_SERIAL_IMX_EARLYCON=y CONFIG_SERIAL_UARTLITE=m CONFIG_SERIAL_UARTLITE_NR_UARTS=1 CONFIG_SERIAL_SH_SCI=m CONFIG_SERIAL_SH_SCI_NR_UARTS=2 CONFIG_SERIAL_SH_SCI_DMA=y CONFIG_SERIAL_HS_LPC32XX=m CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_SERIAL_ICOM=m CONFIG_SERIAL_JSM=m CONFIG_SERIAL_MSM=m CONFIG_SERIAL_QCOM_GENI=m CONFIG_SERIAL_QCOM_GENI_CONSOLE=y CONFIG_SERIAL_VT8500=y CONFIG_SERIAL_VT8500_CONSOLE=y CONFIG_SERIAL_OMAP=m CONFIG_SERIAL_SIFIVE=m CONFIG_SERIAL_LANTIQ=m CONFIG_SERIAL_QE=m CONFIG_SERIAL_SCCNXP=m CONFIG_SERIAL_SC16IS7XX_CORE=m CONFIG_SERIAL_SC16IS7XX=m CONFIG_SERIAL_SC16IS7XX_I2C=y CONFIG_SERIAL_SC16IS7XX_SPI=y CONFIG_SERIAL_TIMBERDALE=m CONFIG_SERIAL_BCM63XX=m CONFIG_SERIAL_ALTERA_JTAGUART=m CONFIG_SERIAL_ALTERA_UART=m CONFIG_SERIAL_ALTERA_UART_MAXPORTS=4 CONFIG_SERIAL_ALTERA_UART_BAUDRATE=115200 CONFIG_SERIAL_PCH_UART=m CONFIG_SERIAL_MXS_AUART=m CONFIG_SERIAL_XILINX_PS_UART=m CONFIG_SERIAL_MPS2_UART_CONSOLE=y CONFIG_SERIAL_MPS2_UART=y CONFIG_SERIAL_ARC=m CONFIG_SERIAL_ARC_NR_PORTS=1 CONFIG_SERIAL_RP2=m CONFIG_SERIAL_RP2_NR_UARTS=32 CONFIG_SERIAL_FSL_LPUART=m CONFIG_SERIAL_FSL_LPUART_CONSOLE=y CONFIG_SERIAL_FSL_LINFLEXUART=m CONFIG_SERIAL_CONEXANT_DIGICOLOR=m CONFIG_SERIAL_ST_ASC=m CONFIG_SERIAL_MEN_Z135=m CONFIG_SERIAL_SPRD=m CONFIG_SERIAL_STM32=m CONFIG_SERIAL_MVEBU_UART=y CONFIG_SERIAL_MVEBU_CONSOLE=y CONFIG_SERIAL_OWL=m CONFIG_SERIAL_RDA=y CONFIG_SERIAL_RDA_CONSOLE=y CONFIG_SERIAL_MILBEAUT_USIO=m CONFIG_SERIAL_MILBEAUT_USIO_PORTS=4 CONFIG_SERIAL_LITEUART=m CONFIG_SERIAL_LITEUART_MAX_PORTS=1 CONFIG_SERIAL_SUNPLUS=m CONFIG_SERIAL_SUNPLUS_CONSOLE=y # end of Serial drivers CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_NONSTANDARD=y CONFIG_MOXA_INTELLIO=m CONFIG_MOXA_SMARTIO=m CONFIG_SYNCLINK_GT=m CONFIG_N_HDLC=m CONFIG_GOLDFISH_TTY=m CONFIG_N_GSM=m CONFIG_NOZOMI=m CONFIG_NULL_TTY=m CONFIG_HVC_DRIVER=y CONFIG_RPMSG_TTY=m CONFIG_SERIAL_DEV_BUS=m CONFIG_TTY_PRINTK=m CONFIG_TTY_PRINTK_LEVEL=6 CONFIG_PRINTER=m CONFIG_LP_CONSOLE=y CONFIG_PPDEV=m CONFIG_VIRTIO_CONSOLE=m CONFIG_IPMI_HANDLER=m CONFIG_IPMI_DMI_DECODE=y CONFIG_IPMI_PLAT_DATA=y CONFIG_IPMI_PANIC_EVENT=y CONFIG_IPMI_PANIC_STRING=y CONFIG_IPMI_DEVICE_INTERFACE=m CONFIG_IPMI_SI=m CONFIG_IPMI_SSIF=m CONFIG_IPMI_IPMB=m CONFIG_IPMI_WATCHDOG=m CONFIG_IPMI_POWEROFF=m CONFIG_IPMI_KCS_BMC=m CONFIG_ASPEED_KCS_IPMI_BMC=m CONFIG_NPCM7XX_KCS_IPMI_BMC=m CONFIG_IPMI_KCS_BMC_CDEV_IPMI=m CONFIG_IPMI_KCS_BMC_SERIO=m CONFIG_ASPEED_BT_IPMI_BMC=m CONFIG_IPMB_DEVICE_INTERFACE=m CONFIG_HW_RANDOM=m CONFIG_HW_RANDOM_TIMERIOMEM=m CONFIG_HW_RANDOM_INTEL=m CONFIG_HW_RANDOM_ATMEL=m CONFIG_HW_RANDOM_BA431=m CONFIG_HW_RANDOM_BCM2835=m CONFIG_HW_RANDOM_IPROC_RNG200=m CONFIG_HW_RANDOM_IXP4XX=m CONFIG_HW_RANDOM_OMAP=m CONFIG_HW_RANDOM_OMAP3_ROM=m CONFIG_HW_RANDOM_VIRTIO=m CONFIG_HW_RANDOM_IMX_RNGC=m CONFIG_HW_RANDOM_NOMADIK=m CONFIG_HW_RANDOM_STM32=m CONFIG_HW_RANDOM_POLARFIRE_SOC=m CONFIG_HW_RANDOM_MESON=m CONFIG_HW_RANDOM_MTK=m CONFIG_HW_RANDOM_EXYNOS=m CONFIG_HW_RANDOM_NPCM=m CONFIG_HW_RANDOM_KEYSTONE=m CONFIG_HW_RANDOM_CCTRNG=m CONFIG_HW_RANDOM_XIPHERA=m CONFIG_HW_RANDOM_CN10K=m CONFIG_APPLICOM=m # # PCMCIA character devices # CONFIG_SYNCLINK_CS=m CONFIG_CARDMAN_4000=m CONFIG_CARDMAN_4040=m CONFIG_SCR24X=m CONFIG_IPWIRELESS=m # end of PCMCIA character devices CONFIG_DEVMEM=y CONFIG_DEVPORT=y CONFIG_HPET=y CONFIG_HPET_MMAP=y CONFIG_HPET_MMAP_DEFAULT=y CONFIG_HANGCHECK_TIMER=m CONFIG_TCG_TPM=y CONFIG_TCG_TIS_CORE=m CONFIG_TCG_TIS=m CONFIG_TCG_TIS_SPI=m CONFIG_TCG_TIS_SPI_CR50=y CONFIG_TCG_TIS_I2C=m CONFIG_TCG_TIS_SYNQUACER=m CONFIG_TCG_TIS_I2C_CR50=m CONFIG_TCG_TIS_I2C_ATMEL=m CONFIG_TCG_TIS_I2C_INFINEON=m CONFIG_TCG_TIS_I2C_NUVOTON=m CONFIG_TCG_ATMEL=m CONFIG_TCG_INFINEON=m CONFIG_TCG_CRB=y CONFIG_TCG_VTPM_PROXY=m CONFIG_TCG_TIS_ST33ZP24=m CONFIG_TCG_TIS_ST33ZP24_I2C=m CONFIG_TCG_TIS_ST33ZP24_SPI=m CONFIG_XILLYBUS_CLASS=m CONFIG_XILLYBUS=m CONFIG_XILLYBUS_PCIE=m CONFIG_XILLYBUS_OF=m CONFIG_XILLYUSB=m CONFIG_RANDOM_TRUST_CPU=y CONFIG_RANDOM_TRUST_BOOTLOADER=y # end of Character devices # # I2C support # CONFIG_I2C=m CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=m CONFIG_I2C_MUX=m # # Multiplexer I2C Chip support # CONFIG_I2C_ARB_GPIO_CHALLENGE=m CONFIG_I2C_MUX_GPIO=m CONFIG_I2C_MUX_GPMUX=m CONFIG_I2C_MUX_LTC4306=m CONFIG_I2C_MUX_PCA9541=m CONFIG_I2C_MUX_PCA954x=m CONFIG_I2C_MUX_PINCTRL=m CONFIG_I2C_MUX_REG=m CONFIG_I2C_DEMUX_PINCTRL=m CONFIG_I2C_MUX_MLXCPLD=m # end of Multiplexer I2C Chip support CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_SMBUS=m CONFIG_I2C_ALGOBIT=m CONFIG_I2C_ALGOPCA=m # # I2C Hardware Bus support # # # PC SMBus host controller drivers # CONFIG_I2C_CCGX_UCSI=m CONFIG_I2C_ALI1535=m CONFIG_I2C_ALI1563=m CONFIG_I2C_ALI15X3=m CONFIG_I2C_AMD756=m CONFIG_I2C_AMD8111=m CONFIG_I2C_AMD_MP2=m CONFIG_I2C_HIX5HD2=m CONFIG_I2C_I801=m CONFIG_I2C_ISCH=m CONFIG_I2C_PIIX4=m CONFIG_I2C_NFORCE2=m CONFIG_I2C_NVIDIA_GPU=m CONFIG_I2C_SIS5595=m CONFIG_I2C_SIS630=m CONFIG_I2C_SIS96X=m CONFIG_I2C_VIA=m CONFIG_I2C_VIAPRO=m # # ACPI drivers # CONFIG_I2C_SCMI=m # # I2C system bus drivers (mostly embedded / system-on-chip) # CONFIG_I2C_ALTERA=m CONFIG_I2C_ASPEED=m CONFIG_I2C_AT91=m CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL=m CONFIG_I2C_AXXIA=m CONFIG_I2C_BCM2835=m CONFIG_I2C_BCM_IPROC=m CONFIG_I2C_BCM_KONA=m CONFIG_I2C_BRCMSTB=m CONFIG_I2C_CADENCE=m CONFIG_I2C_CBUS_GPIO=m CONFIG_I2C_DAVINCI=m CONFIG_I2C_DESIGNWARE_CORE=m CONFIG_I2C_DESIGNWARE_SLAVE=y CONFIG_I2C_DESIGNWARE_PLATFORM=m CONFIG_I2C_DESIGNWARE_PCI=m CONFIG_I2C_DIGICOLOR=m CONFIG_I2C_EG20T=m CONFIG_I2C_EMEV2=m CONFIG_I2C_EXYNOS5=m CONFIG_I2C_GPIO=m CONFIG_I2C_GPIO_FAULT_INJECTOR=y CONFIG_I2C_HIGHLANDER=m CONFIG_I2C_HISI=m CONFIG_I2C_IMG=m CONFIG_I2C_IMX=m CONFIG_I2C_IMX_LPI2C=m CONFIG_I2C_IOP3XX=m CONFIG_I2C_JZ4780=m CONFIG_I2C_KEMPLD=m CONFIG_I2C_LPC2K=m CONFIG_I2C_MESON=m CONFIG_I2C_MICROCHIP_CORE=m CONFIG_I2C_MT65XX=m CONFIG_I2C_MT7621=m CONFIG_I2C_MV64XXX=m CONFIG_I2C_MXS=m CONFIG_I2C_NPCM=m CONFIG_I2C_OCORES=m CONFIG_I2C_OMAP=m CONFIG_I2C_OWL=m CONFIG_I2C_APPLE=m CONFIG_I2C_PCA_PLATFORM=m CONFIG_I2C_PNX=m CONFIG_I2C_PXA=m CONFIG_I2C_PXA_SLAVE=y CONFIG_I2C_QCOM_CCI=m CONFIG_I2C_QCOM_GENI=m CONFIG_I2C_QUP=m CONFIG_I2C_RIIC=m CONFIG_I2C_RK3X=m CONFIG_I2C_RZV2M=m CONFIG_I2C_S3C2410=m CONFIG_I2C_SH_MOBILE=m CONFIG_I2C_SIMTEC=m CONFIG_I2C_ST=m CONFIG_I2C_STM32F4=m CONFIG_I2C_STM32F7=m CONFIG_I2C_SUN6I_P2WI=m CONFIG_I2C_SYNQUACER=m CONFIG_I2C_TEGRA_BPMP=m CONFIG_I2C_UNIPHIER=m CONFIG_I2C_UNIPHIER_F=m CONFIG_I2C_VERSATILE=m CONFIG_I2C_WMT=m CONFIG_I2C_THUNDERX=m CONFIG_I2C_XILINX=m CONFIG_I2C_XLP9XX=m CONFIG_I2C_RCAR=m # # External I2C/SMBus adapter drivers # CONFIG_I2C_DIOLAN_U2C=m CONFIG_I2C_DLN2=m CONFIG_I2C_CP2615=m CONFIG_I2C_PARPORT=m CONFIG_I2C_PCI1XXXX=m CONFIG_I2C_ROBOTFUZZ_OSIF=m CONFIG_I2C_TAOS_EVM=m CONFIG_I2C_TINY_USB=m CONFIG_I2C_VIPERBOARD=m # # Other I2C/SMBus bus drivers # CONFIG_I2C_MLXCPLD=m CONFIG_I2C_CROS_EC_TUNNEL=m CONFIG_I2C_FSI=m CONFIG_I2C_VIRTIO=m # end of I2C Hardware Bus support CONFIG_I2C_STUB=m CONFIG_I2C_SLAVE=y CONFIG_I2C_SLAVE_EEPROM=m CONFIG_I2C_SLAVE_TESTUNIT=m CONFIG_I2C_DEBUG_CORE=y CONFIG_I2C_DEBUG_ALGO=y CONFIG_I2C_DEBUG_BUS=y # end of I2C support CONFIG_I3C=m CONFIG_CDNS_I3C_MASTER=m CONFIG_DW_I3C_MASTER=m CONFIG_SVC_I3C_MASTER=m CONFIG_MIPI_I3C_HCI=m CONFIG_SPI=y CONFIG_SPI_DEBUG=y CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y # # SPI Master Controller Drivers # CONFIG_SPI_ALTERA=m CONFIG_SPI_ALTERA_CORE=m CONFIG_SPI_ALTERA_DFL=m CONFIG_SPI_AR934X=m CONFIG_SPI_ATH79=m CONFIG_SPI_ARMADA_3700=m CONFIG_SPI_ASPEED_SMC=m CONFIG_SPI_ATMEL=m CONFIG_SPI_AT91_USART=m CONFIG_SPI_ATMEL_QUADSPI=m CONFIG_SPI_AXI_SPI_ENGINE=m CONFIG_SPI_BCM2835=m CONFIG_SPI_BCM2835AUX=m CONFIG_SPI_BCM63XX=m CONFIG_SPI_BCM63XX_HSSPI=m CONFIG_SPI_BCM_QSPI=m CONFIG_SPI_BITBANG=m CONFIG_SPI_BUTTERFLY=m CONFIG_SPI_CADENCE=m CONFIG_SPI_CADENCE_QUADSPI=m CONFIG_SPI_CADENCE_XSPI=m CONFIG_SPI_CLPS711X=m CONFIG_SPI_DESIGNWARE=m CONFIG_SPI_DW_DMA=y CONFIG_SPI_DW_PCI=m CONFIG_SPI_DW_MMIO=m CONFIG_SPI_DW_BT1=m CONFIG_SPI_DW_BT1_DIRMAP=y CONFIG_SPI_DLN2=m CONFIG_SPI_EP93XX=m CONFIG_SPI_FSI=m CONFIG_SPI_FSL_LPSPI=m CONFIG_SPI_FSL_QUADSPI=m CONFIG_SPI_GXP=m CONFIG_SPI_HISI_KUNPENG=m CONFIG_SPI_HISI_SFC_V3XX=m CONFIG_SPI_NXP_FLEXSPI=m CONFIG_SPI_GPIO=m CONFIG_SPI_IMG_SPFI=m CONFIG_SPI_IMX=m CONFIG_SPI_INGENIC=m CONFIG_SPI_INTEL=m CONFIG_SPI_INTEL_PCI=m CONFIG_SPI_INTEL_PLATFORM=m CONFIG_SPI_JCORE=m CONFIG_SPI_LM70_LLP=m CONFIG_SPI_LP8841_RTC=m CONFIG_SPI_FSL_LIB=m CONFIG_SPI_FSL_SPI=m CONFIG_SPI_FSL_DSPI=m CONFIG_SPI_MESON_SPICC=m CONFIG_SPI_MESON_SPIFC=m CONFIG_SPI_MICROCHIP_CORE=m CONFIG_SPI_MICROCHIP_CORE_QSPI=m CONFIG_SPI_MT65XX=m CONFIG_SPI_MT7621=m CONFIG_SPI_MTK_NOR=m CONFIG_SPI_MTK_SNFI=m CONFIG_SPI_NPCM_FIU=m CONFIG_SPI_NPCM_PSPI=m CONFIG_SPI_LANTIQ_SSC=m CONFIG_SPI_OC_TINY=m CONFIG_SPI_OMAP24XX=m CONFIG_SPI_TI_QSPI=m CONFIG_SPI_OMAP_100K=m CONFIG_SPI_ORION=m CONFIG_SPI_PIC32=m CONFIG_SPI_PIC32_SQI=m CONFIG_SPI_PXA2XX=m CONFIG_SPI_PXA2XX_PCI=m CONFIG_SPI_ROCKCHIP=m CONFIG_SPI_ROCKCHIP_SFC=m CONFIG_SPI_RPCIF=m CONFIG_SPI_RSPI=m CONFIG_SPI_QUP=m CONFIG_SPI_QCOM_GENI=m CONFIG_SPI_S3C64XX=m CONFIG_SPI_SC18IS602=m CONFIG_SPI_SH_MSIOF=m CONFIG_SPI_SH=m CONFIG_SPI_SH_HSPI=m CONFIG_SPI_SIFIVE=m CONFIG_SPI_SLAVE_MT27XX=m CONFIG_SPI_SPRD=m CONFIG_SPI_SPRD_ADI=m CONFIG_SPI_STM32=m CONFIG_SPI_STM32_QSPI=m CONFIG_SPI_ST_SSC4=m CONFIG_SPI_SUN4I=m CONFIG_SPI_SUN6I=m CONFIG_SPI_SUNPLUS_SP7021=m CONFIG_SPI_SYNQUACER=m CONFIG_SPI_MXIC=m CONFIG_SPI_TEGRA210_QUAD=m CONFIG_SPI_TEGRA114=m CONFIG_SPI_TEGRA20_SFLASH=m CONFIG_SPI_TEGRA20_SLINK=m CONFIG_SPI_THUNDERX=m CONFIG_SPI_TOPCLIFF_PCH=m CONFIG_SPI_UNIPHIER=m CONFIG_SPI_XCOMM=m CONFIG_SPI_XILINX=m CONFIG_SPI_XLP=m CONFIG_SPI_XTENSA_XTFPGA=m CONFIG_SPI_ZYNQ_QSPI=m CONFIG_SPI_ZYNQMP_GQSPI=m CONFIG_SPI_AMD=m # # SPI Multiplexer support # CONFIG_SPI_MUX=m # # SPI Protocol Masters # CONFIG_SPI_SPIDEV=m CONFIG_SPI_LOOPBACK_TEST=m CONFIG_SPI_TLE62X0=m CONFIG_SPI_SLAVE=y CONFIG_SPI_SLAVE_TIME=m CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m CONFIG_SPI_DYNAMIC=y CONFIG_SPMI=m CONFIG_SPMI_HISI3670=m CONFIG_SPMI_MSM_PMIC_ARB=m CONFIG_SPMI_MTK_PMIF=m CONFIG_HSI=m CONFIG_HSI_BOARDINFO=y # # HSI controllers # # # HSI clients # CONFIG_HSI_CHAR=m CONFIG_PPS=m CONFIG_PPS_DEBUG=y CONFIG_NTP_PPS=y # # PPS clients support # CONFIG_PPS_CLIENT_KTIMER=m CONFIG_PPS_CLIENT_LDISC=m CONFIG_PPS_CLIENT_PARPORT=m CONFIG_PPS_CLIENT_GPIO=m # # PPS generators support # # # PTP clock support # CONFIG_PTP_1588_CLOCK=m CONFIG_PTP_1588_CLOCK_OPTIONAL=m CONFIG_PTP_1588_CLOCK_DTE=m CONFIG_PTP_1588_CLOCK_QORIQ=m CONFIG_DP83640_PHY=m CONFIG_PTP_1588_CLOCK_INES=m CONFIG_PTP_1588_CLOCK_PCH=m CONFIG_PTP_1588_CLOCK_IDT82P33=m CONFIG_PTP_1588_CLOCK_IDTCM=m CONFIG_PTP_1588_CLOCK_OCP=m # end of PTP clock support CONFIG_PINCTRL=y CONFIG_GENERIC_PINCTRL_GROUPS=y CONFIG_PINMUX=y CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y CONFIG_DEBUG_PINCTRL=y CONFIG_PINCTRL_AMD=y CONFIG_PINCTRL_AT91PIO4=y CONFIG_PINCTRL_AXP209=m CONFIG_PINCTRL_BM1880=y CONFIG_PINCTRL_CY8C95X0=m CONFIG_PINCTRL_DA850_PUPD=m CONFIG_PINCTRL_DA9062=m CONFIG_PINCTRL_EQUILIBRIUM=m CONFIG_PINCTRL_INGENIC=y CONFIG_PINCTRL_LPC18XX=y CONFIG_PINCTRL_MCP23S08_I2C=m CONFIG_PINCTRL_MCP23S08_SPI=m CONFIG_PINCTRL_MCP23S08=m CONFIG_PINCTRL_MICROCHIP_SGPIO=m CONFIG_PINCTRL_OCELOT=m CONFIG_PINCTRL_PISTACHIO=y CONFIG_PINCTRL_RK805=m CONFIG_PINCTRL_ROCKCHIP=m CONFIG_PINCTRL_SINGLE=m CONFIG_PINCTRL_STMFX=m CONFIG_PINCTRL_OWL=y CONFIG_PINCTRL_S500=y CONFIG_PINCTRL_S700=y CONFIG_PINCTRL_S900=y CONFIG_PINCTRL_ASPEED=y CONFIG_PINCTRL_ASPEED_G4=y CONFIG_PINCTRL_ASPEED_G5=y CONFIG_PINCTRL_ASPEED_G6=y CONFIG_PINCTRL_BCM281XX=y CONFIG_PINCTRL_BCM2835=m CONFIG_PINCTRL_BCM4908=m CONFIG_PINCTRL_BCM63XX=y CONFIG_PINCTRL_BCM6318=y CONFIG_PINCTRL_BCM6328=y CONFIG_PINCTRL_BCM6358=y CONFIG_PINCTRL_BCM6362=y CONFIG_PINCTRL_BCM6368=y CONFIG_PINCTRL_BCM63268=y CONFIG_PINCTRL_IPROC_GPIO=y CONFIG_PINCTRL_CYGNUS_MUX=y CONFIG_PINCTRL_NS=y CONFIG_PINCTRL_NSP_GPIO=y CONFIG_PINCTRL_NS2_MUX=y CONFIG_PINCTRL_NSP_MUX=y CONFIG_PINCTRL_BERLIN=y CONFIG_PINCTRL_AS370=y CONFIG_PINCTRL_BERLIN_BG4CT=y CONFIG_PINCTRL_MADERA=m CONFIG_PINCTRL_CS47L15=y CONFIG_PINCTRL_CS47L35=y CONFIG_PINCTRL_CS47L85=y CONFIG_PINCTRL_CS47L90=y CONFIG_PINCTRL_CS47L92=y CONFIG_PINCTRL_IMX=m CONFIG_PINCTRL_IMX8MM=m CONFIG_PINCTRL_IMX8MN=m CONFIG_PINCTRL_IMX8MP=m CONFIG_PINCTRL_IMX8MQ=m # # Intel pinctrl drivers # CONFIG_PINCTRL_BAYTRAIL=y CONFIG_PINCTRL_CHERRYVIEW=m CONFIG_PINCTRL_LYNXPOINT=m CONFIG_PINCTRL_INTEL=y CONFIG_PINCTRL_ALDERLAKE=m CONFIG_PINCTRL_BROXTON=m CONFIG_PINCTRL_CANNONLAKE=m CONFIG_PINCTRL_CEDARFORK=m CONFIG_PINCTRL_DENVERTON=m CONFIG_PINCTRL_ELKHARTLAKE=m CONFIG_PINCTRL_EMMITSBURG=m CONFIG_PINCTRL_GEMINILAKE=m CONFIG_PINCTRL_ICELAKE=m CONFIG_PINCTRL_JASPERLAKE=m CONFIG_PINCTRL_LAKEFIELD=m CONFIG_PINCTRL_LEWISBURG=m CONFIG_PINCTRL_METEORLAKE=m CONFIG_PINCTRL_SUNRISEPOINT=m CONFIG_PINCTRL_TIGERLAKE=m # end of Intel pinctrl drivers # # MediaTek pinctrl drivers # CONFIG_EINT_MTK=y CONFIG_PINCTRL_MTK=y CONFIG_PINCTRL_MTK_V2=y CONFIG_PINCTRL_MTK_MOORE=y CONFIG_PINCTRL_MTK_PARIS=y CONFIG_PINCTRL_MT2701=y CONFIG_PINCTRL_MT7623=y CONFIG_PINCTRL_MT7629=y CONFIG_PINCTRL_MT8135=y CONFIG_PINCTRL_MT8127=y CONFIG_PINCTRL_MT2712=y CONFIG_PINCTRL_MT6765=m CONFIG_PINCTRL_MT6779=m CONFIG_PINCTRL_MT6795=y CONFIG_PINCTRL_MT6797=y CONFIG_PINCTRL_MT7622=y CONFIG_PINCTRL_MT7986=y CONFIG_PINCTRL_MT8167=y CONFIG_PINCTRL_MT8173=y CONFIG_PINCTRL_MT8183=y CONFIG_PINCTRL_MT8186=y CONFIG_PINCTRL_MT8188=y CONFIG_PINCTRL_MT8192=y CONFIG_PINCTRL_MT8195=y CONFIG_PINCTRL_MT8365=y CONFIG_PINCTRL_MT8516=y CONFIG_PINCTRL_MT6397=y # end of MediaTek pinctrl drivers CONFIG_PINCTRL_MESON=m CONFIG_PINCTRL_WPCM450=m CONFIG_PINCTRL_NPCM7XX=y CONFIG_PINCTRL_PXA=y CONFIG_PINCTRL_PXA25X=m CONFIG_PINCTRL_PXA27X=m CONFIG_PINCTRL_MSM=m CONFIG_PINCTRL_APQ8064=m CONFIG_PINCTRL_APQ8084=m CONFIG_PINCTRL_IPQ4019=m CONFIG_PINCTRL_IPQ8064=m CONFIG_PINCTRL_IPQ8074=m CONFIG_PINCTRL_IPQ6018=m CONFIG_PINCTRL_MSM8226=m CONFIG_PINCTRL_MSM8660=m CONFIG_PINCTRL_MSM8960=m CONFIG_PINCTRL_MDM9607=m CONFIG_PINCTRL_MDM9615=m CONFIG_PINCTRL_MSM8X74=m CONFIG_PINCTRL_MSM8909=m CONFIG_PINCTRL_MSM8916=m CONFIG_PINCTRL_MSM8953=m CONFIG_PINCTRL_MSM8976=m CONFIG_PINCTRL_MSM8994=m CONFIG_PINCTRL_MSM8996=m CONFIG_PINCTRL_MSM8998=m CONFIG_PINCTRL_QCM2290=m CONFIG_PINCTRL_QCS404=m CONFIG_PINCTRL_QDF2XXX=m CONFIG_PINCTRL_QCOM_SPMI_PMIC=m CONFIG_PINCTRL_QCOM_SSBI_PMIC=m CONFIG_PINCTRL_SC7180=m CONFIG_PINCTRL_SC7280=m CONFIG_PINCTRL_SC7280_LPASS_LPI=m CONFIG_PINCTRL_SC8180X=m CONFIG_PINCTRL_SC8280XP=m CONFIG_PINCTRL_SDM660=m CONFIG_PINCTRL_SDM845=m CONFIG_PINCTRL_SDX55=m CONFIG_PINCTRL_SM6115=m CONFIG_PINCTRL_SM6125=m CONFIG_PINCTRL_SM6350=m CONFIG_PINCTRL_SM6375=m CONFIG_PINCTRL_SDX65=m CONFIG_PINCTRL_SM8150=m CONFIG_PINCTRL_SM8250=m CONFIG_PINCTRL_SM8250_LPASS_LPI=m CONFIG_PINCTRL_SM8350=m CONFIG_PINCTRL_SM8450=m CONFIG_PINCTRL_SM8450_LPASS_LPI=m CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m CONFIG_PINCTRL_LPASS_LPI=m # # Renesas pinctrl drivers # CONFIG_PINCTRL_RENESAS=y CONFIG_PINCTRL_SH_PFC=y CONFIG_PINCTRL_SH_PFC_GPIO=y CONFIG_PINCTRL_SH_FUNC_GPIO=y CONFIG_PINCTRL_PFC_EMEV2=y CONFIG_PINCTRL_PFC_R8A77995=y CONFIG_PINCTRL_PFC_R8A7794=y CONFIG_PINCTRL_PFC_R8A77990=y CONFIG_PINCTRL_PFC_R8A7779=y CONFIG_PINCTRL_PFC_R8A7790=y CONFIG_PINCTRL_PFC_R8A77950=y CONFIG_PINCTRL_PFC_R8A77951=y CONFIG_PINCTRL_PFC_R8A7778=y CONFIG_PINCTRL_PFC_R8A7793=y CONFIG_PINCTRL_PFC_R8A7791=y CONFIG_PINCTRL_PFC_R8A77965=y CONFIG_PINCTRL_PFC_R8A77960=y CONFIG_PINCTRL_PFC_R8A77961=y CONFIG_PINCTRL_PFC_R8A779F0=y CONFIG_PINCTRL_PFC_R8A7792=y CONFIG_PINCTRL_PFC_R8A77980=y CONFIG_PINCTRL_PFC_R8A77970=y CONFIG_PINCTRL_PFC_R8A779A0=y CONFIG_PINCTRL_PFC_R8A779G0=y CONFIG_PINCTRL_PFC_R8A7740=y CONFIG_PINCTRL_PFC_R8A73A4=y CONFIG_PINCTRL_RZA1=y CONFIG_PINCTRL_RZA2=y CONFIG_PINCTRL_RZG2L=y CONFIG_PINCTRL_PFC_R8A77470=y CONFIG_PINCTRL_PFC_R8A7745=y CONFIG_PINCTRL_PFC_R8A7742=y CONFIG_PINCTRL_PFC_R8A7743=y CONFIG_PINCTRL_PFC_R8A7744=y CONFIG_PINCTRL_PFC_R8A774C0=y CONFIG_PINCTRL_PFC_R8A774E1=y CONFIG_PINCTRL_PFC_R8A774A1=y CONFIG_PINCTRL_PFC_R8A774B1=y CONFIG_PINCTRL_RZN1=y CONFIG_PINCTRL_RZV2M=y CONFIG_PINCTRL_PFC_SH7203=y CONFIG_PINCTRL_PFC_SH7264=y CONFIG_PINCTRL_PFC_SH7269=y CONFIG_PINCTRL_PFC_SH7720=y CONFIG_PINCTRL_PFC_SH7722=y CONFIG_PINCTRL_PFC_SH7734=y CONFIG_PINCTRL_PFC_SH7757=y CONFIG_PINCTRL_PFC_SH7785=y CONFIG_PINCTRL_PFC_SH7786=y CONFIG_PINCTRL_PFC_SH73A0=y CONFIG_PINCTRL_PFC_SH7723=y CONFIG_PINCTRL_PFC_SH7724=y CONFIG_PINCTRL_PFC_SHX3=y # end of Renesas pinctrl drivers CONFIG_PINCTRL_SAMSUNG=y CONFIG_PINCTRL_EXYNOS=y CONFIG_PINCTRL_EXYNOS_ARM=y CONFIG_PINCTRL_EXYNOS_ARM64=y CONFIG_PINCTRL_S3C24XX=y CONFIG_PINCTRL_S3C64XX=y CONFIG_PINCTRL_SPRD=m CONFIG_PINCTRL_SPRD_SC9860=m CONFIG_PINCTRL_STARFIVE_JH7100=m CONFIG_PINCTRL_STM32=y CONFIG_PINCTRL_STM32F429=y CONFIG_PINCTRL_STM32F469=y CONFIG_PINCTRL_STM32F746=y CONFIG_PINCTRL_STM32F769=y CONFIG_PINCTRL_STM32H743=y CONFIG_PINCTRL_STM32MP135=y CONFIG_PINCTRL_STM32MP157=y CONFIG_PINCTRL_TI_IODELAY=m CONFIG_PINCTRL_UNIPHIER=y CONFIG_PINCTRL_UNIPHIER_LD4=y CONFIG_PINCTRL_UNIPHIER_PRO4=y CONFIG_PINCTRL_UNIPHIER_SLD8=y CONFIG_PINCTRL_UNIPHIER_PRO5=y CONFIG_PINCTRL_UNIPHIER_PXS2=y CONFIG_PINCTRL_UNIPHIER_LD6B=y CONFIG_PINCTRL_UNIPHIER_LD11=y CONFIG_PINCTRL_UNIPHIER_LD20=y CONFIG_PINCTRL_UNIPHIER_PXS3=y CONFIG_PINCTRL_UNIPHIER_NX1=y CONFIG_PINCTRL_VISCONTI=y CONFIG_PINCTRL_TMPV7700=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIO_ACPI=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_DEBUG_GPIO=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y CONFIG_GPIO_REGMAP=y CONFIG_GPIO_MAX730X=m # # Memory mapped GPIO drivers # CONFIG_GPIO_74XX_MMIO=m CONFIG_GPIO_ALTERA=m CONFIG_GPIO_AMDPT=m CONFIG_GPIO_ASPEED=m CONFIG_GPIO_ASPEED_SGPIO=y CONFIG_GPIO_ATH79=m CONFIG_GPIO_RASPBERRYPI_EXP=m CONFIG_GPIO_BCM_KONA=y CONFIG_GPIO_BCM_XGS_IPROC=m CONFIG_GPIO_BRCMSTB=m CONFIG_GPIO_CADENCE=m CONFIG_GPIO_CLPS711X=m CONFIG_GPIO_DWAPB=m CONFIG_GPIO_EIC_SPRD=m CONFIG_GPIO_EM=m CONFIG_GPIO_EXAR=m CONFIG_GPIO_FTGPIO010=y CONFIG_GPIO_GENERIC_PLATFORM=m CONFIG_GPIO_GRGPIO=m CONFIG_GPIO_HISI=m CONFIG_GPIO_HLWD=m CONFIG_GPIO_IMX_SCU=y CONFIG_GPIO_IOP=m CONFIG_GPIO_LOGICVC=m CONFIG_GPIO_LPC18XX=m CONFIG_GPIO_LPC32XX=m CONFIG_GPIO_MB86S7X=m CONFIG_GPIO_MENZ127=m CONFIG_GPIO_MPC8XXX=y CONFIG_GPIO_MT7621=y CONFIG_GPIO_MXC=m CONFIG_GPIO_MXS=y CONFIG_GPIO_PMIC_EIC_SPRD=m CONFIG_GPIO_PXA=y CONFIG_GPIO_RCAR=m CONFIG_GPIO_RDA=y CONFIG_GPIO_ROCKCHIP=m CONFIG_GPIO_SAMA5D2_PIOBU=m CONFIG_GPIO_SIFIVE=y CONFIG_GPIO_SIOX=m CONFIG_GPIO_SNPS_CREG=y CONFIG_GPIO_SPRD=m CONFIG_GPIO_STP_XWAY=y CONFIG_GPIO_SYSCON=m CONFIG_GPIO_TEGRA=m CONFIG_GPIO_TEGRA186=m CONFIG_GPIO_TS4800=m CONFIG_GPIO_THUNDERX=m CONFIG_GPIO_UNIPHIER=m CONFIG_GPIO_VISCONTI=m CONFIG_GPIO_VX855=m CONFIG_GPIO_WCD934X=m CONFIG_GPIO_XGENE_SB=m CONFIG_GPIO_XILINX=m CONFIG_GPIO_XLP=m CONFIG_GPIO_AMD_FCH=m CONFIG_GPIO_IDT3243X=m # end of Memory mapped GPIO drivers # # I2C GPIO expanders # CONFIG_GPIO_ADNP=m CONFIG_GPIO_GW_PLD=m CONFIG_GPIO_MAX7300=m CONFIG_GPIO_MAX732X=m CONFIG_GPIO_PCA953X=m CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_PCA9570=m CONFIG_GPIO_PCF857X=m CONFIG_GPIO_TPIC2810=m CONFIG_GPIO_TS4900=m # end of I2C GPIO expanders # # MFD GPIO expanders # CONFIG_GPIO_ARIZONA=m CONFIG_GPIO_BD9571MWV=m CONFIG_GPIO_DA9052=m CONFIG_GPIO_DLN2=m CONFIG_GPIO_JANZ_TTL=m CONFIG_GPIO_KEMPLD=m CONFIG_GPIO_LP3943=m CONFIG_GPIO_LP873X=m CONFIG_GPIO_LP87565=m CONFIG_GPIO_MADERA=m CONFIG_GPIO_MAX77650=m CONFIG_GPIO_SL28CPLD=m CONFIG_GPIO_STMPE=y CONFIG_GPIO_TIMBERDALE=y CONFIG_GPIO_TPS65086=m CONFIG_GPIO_TPS65218=m CONFIG_GPIO_TPS65912=m CONFIG_GPIO_TQMX86=m CONFIG_GPIO_WM831X=m CONFIG_GPIO_WM8994=m # end of MFD GPIO expanders # # PCI GPIO expanders # CONFIG_GPIO_AMD8111=m CONFIG_GPIO_MLXBF=m CONFIG_GPIO_MLXBF2=m CONFIG_GPIO_ML_IOH=m CONFIG_GPIO_PCH=m CONFIG_GPIO_PCI_IDIO_16=m CONFIG_GPIO_PCIE_IDIO_24=m CONFIG_GPIO_RDC321X=m # end of PCI GPIO expanders # # SPI GPIO expanders # CONFIG_GPIO_74X164=m CONFIG_GPIO_MAX3191X=m CONFIG_GPIO_MAX7301=m CONFIG_GPIO_MC33880=m CONFIG_GPIO_PISOSR=m CONFIG_GPIO_XRA1403=m CONFIG_GPIO_MOXTET=m # end of SPI GPIO expanders # # USB GPIO expanders # CONFIG_GPIO_VIPERBOARD=m # end of USB GPIO expanders # # Virtual GPIO drivers # CONFIG_GPIO_AGGREGATOR=m CONFIG_GPIO_MOCKUP=m CONFIG_GPIO_VIRTIO=m CONFIG_GPIO_SIM=m # end of Virtual GPIO drivers CONFIG_W1=m CONFIG_W1_CON=y # # 1-wire Bus Masters # CONFIG_W1_MASTER_MATROX=m CONFIG_W1_MASTER_DS2490=m CONFIG_W1_MASTER_DS2482=m CONFIG_W1_MASTER_MXC=m CONFIG_W1_MASTER_DS1WM=m CONFIG_W1_MASTER_GPIO=m CONFIG_W1_MASTER_SGI=m # end of 1-wire Bus Masters # # 1-wire Slaves # CONFIG_W1_SLAVE_THERM=m CONFIG_W1_SLAVE_SMEM=m CONFIG_W1_SLAVE_DS2405=m CONFIG_W1_SLAVE_DS2408=m CONFIG_W1_SLAVE_DS2408_READBACK=y CONFIG_W1_SLAVE_DS2413=m CONFIG_W1_SLAVE_DS2406=m CONFIG_W1_SLAVE_DS2423=m CONFIG_W1_SLAVE_DS2805=m CONFIG_W1_SLAVE_DS2430=m CONFIG_W1_SLAVE_DS2431=m CONFIG_W1_SLAVE_DS2433=m CONFIG_W1_SLAVE_DS2433_CRC=y CONFIG_W1_SLAVE_DS2438=m CONFIG_W1_SLAVE_DS250X=m CONFIG_W1_SLAVE_DS2780=m CONFIG_W1_SLAVE_DS2781=m CONFIG_W1_SLAVE_DS28E04=m CONFIG_W1_SLAVE_DS28E17=m # end of 1-wire Slaves CONFIG_POWER_RESET=y CONFIG_POWER_RESET_ATC260X=m CONFIG_POWER_RESET_BRCMKONA=y CONFIG_POWER_RESET_BRCMSTB=y CONFIG_POWER_RESET_GEMINI_POWEROFF=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_POWER_RESET_LINKSTATION=m CONFIG_POWER_RESET_OCELOT_RESET=y CONFIG_POWER_RESET_PIIX4_POWEROFF=m CONFIG_POWER_RESET_LTC2952=y CONFIG_POWER_RESET_MT6323=y CONFIG_POWER_RESET_REGULATOR=y CONFIG_POWER_RESET_RESTART=y CONFIG_POWER_RESET_TPS65086=y CONFIG_POWER_RESET_KEYSTONE=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y CONFIG_POWER_RESET_RMOBILE=m CONFIG_REBOOT_MODE=m CONFIG_SYSCON_REBOOT_MODE=m CONFIG_POWER_RESET_SC27XX=m CONFIG_NVMEM_REBOOT_MODE=m CONFIG_POWER_MLXBF=m CONFIG_POWER_SUPPLY=y CONFIG_POWER_SUPPLY_DEBUG=y CONFIG_PDA_POWER=m CONFIG_GENERIC_ADC_BATTERY=m CONFIG_IP5XXX_POWER=m CONFIG_WM831X_BACKUP=m CONFIG_WM831X_POWER=m CONFIG_TEST_POWER=m CONFIG_CHARGER_ADP5061=m CONFIG_BATTERY_ACT8945A=m CONFIG_BATTERY_CPCAP=m CONFIG_BATTERY_CW2015=m CONFIG_BATTERY_DS2760=m CONFIG_BATTERY_DS2780=m CONFIG_BATTERY_DS2781=m CONFIG_BATTERY_DS2782=m CONFIG_BATTERY_LEGO_EV3=m CONFIG_BATTERY_OLPC=m CONFIG_BATTERY_SAMSUNG_SDI=y CONFIG_BATTERY_INGENIC=m CONFIG_BATTERY_SBS=m CONFIG_CHARGER_SBS=m CONFIG_MANAGER_SBS=m CONFIG_BATTERY_BQ27XXX=m CONFIG_BATTERY_BQ27XXX_I2C=m CONFIG_BATTERY_BQ27XXX_HDQ=m CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM=y CONFIG_BATTERY_DA9052=m CONFIG_CHARGER_DA9150=m CONFIG_BATTERY_DA9150=m CONFIG_CHARGER_AXP20X=m CONFIG_BATTERY_AXP20X=m CONFIG_AXP20X_POWER=m CONFIG_BATTERY_MAX17040=m CONFIG_BATTERY_MAX17042=m CONFIG_BATTERY_MAX1721X=m CONFIG_CHARGER_PCF50633=m CONFIG_CHARGER_CPCAP=m CONFIG_CHARGER_ISP1704=m CONFIG_CHARGER_MAX8903=m CONFIG_CHARGER_LP8727=m CONFIG_CHARGER_GPIO=m CONFIG_CHARGER_MANAGER=m CONFIG_CHARGER_LT3651=m CONFIG_CHARGER_LTC4162L=m CONFIG_CHARGER_MAX14577=m CONFIG_CHARGER_DETECTOR_MAX14656=m CONFIG_CHARGER_MAX77650=m CONFIG_CHARGER_MAX77693=m CONFIG_CHARGER_MAX77976=m CONFIG_CHARGER_MP2629=m CONFIG_CHARGER_MT6360=m CONFIG_CHARGER_MT6370=m CONFIG_CHARGER_QCOM_SMBB=m CONFIG_CHARGER_BQ2415X=m CONFIG_CHARGER_BQ24190=m CONFIG_CHARGER_BQ24257=m CONFIG_CHARGER_BQ24735=m CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ25890=m CONFIG_CHARGER_BQ25980=m CONFIG_CHARGER_BQ256XX=m CONFIG_CHARGER_RK817=m CONFIG_CHARGER_SMB347=m CONFIG_CHARGER_TPS65217=m CONFIG_BATTERY_GAUGE_LTC2941=m CONFIG_BATTERY_GOLDFISH=m CONFIG_BATTERY_RT5033=m CONFIG_CHARGER_RT9455=m CONFIG_CHARGER_CROS_USBPD=m CONFIG_CHARGER_CROS_PCHG=m CONFIG_CHARGER_SC2731=m CONFIG_FUEL_GAUGE_SC27XX=m CONFIG_CHARGER_UCS1002=m CONFIG_CHARGER_BD99954=m CONFIG_CHARGER_WILCO=m CONFIG_RN5T618_POWER=m CONFIG_BATTERY_ACER_A500=m CONFIG_BATTERY_SURFACE=m CONFIG_CHARGER_SURFACE=m CONFIG_BATTERY_UG3105=m CONFIG_HWMON=m CONFIG_HWMON_VID=m CONFIG_HWMON_DEBUG_CHIP=y # # Native drivers # CONFIG_SENSORS_AD7314=m CONFIG_SENSORS_AD7414=m CONFIG_SENSORS_AD7418=m CONFIG_SENSORS_ADM1025=m CONFIG_SENSORS_ADM1026=m CONFIG_SENSORS_ADM1029=m CONFIG_SENSORS_ADM1031=m CONFIG_SENSORS_ADM1177=m CONFIG_SENSORS_ADM9240=m CONFIG_SENSORS_ADT7X10=m CONFIG_SENSORS_ADT7310=m CONFIG_SENSORS_ADT7410=m CONFIG_SENSORS_ADT7411=m CONFIG_SENSORS_ADT7462=m CONFIG_SENSORS_ADT7470=m CONFIG_SENSORS_ADT7475=m CONFIG_SENSORS_AHT10=m CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m CONFIG_SENSORS_AS370=m CONFIG_SENSORS_ASC7621=m CONFIG_SENSORS_AXI_FAN_CONTROL=m CONFIG_SENSORS_ARM_SCMI=m CONFIG_SENSORS_ARM_SCPI=m CONFIG_SENSORS_ASB100=m CONFIG_SENSORS_ASPEED=m CONFIG_SENSORS_ATXP1=m CONFIG_SENSORS_BT1_PVT=m CONFIG_SENSORS_BT1_PVT_ALARMS=y CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m CONFIG_SENSORS_DRIVETEMP=m CONFIG_SENSORS_DS620=m CONFIG_SENSORS_DS1621=m CONFIG_SENSORS_DA9052_ADC=m CONFIG_SENSORS_I5K_AMB=m CONFIG_SENSORS_SPARX5=m CONFIG_SENSORS_F71805F=m CONFIG_SENSORS_F71882FG=m CONFIG_SENSORS_F75375S=m CONFIG_SENSORS_GSC=m CONFIG_SENSORS_MC13783_ADC=m CONFIG_SENSORS_FSCHMD=m CONFIG_SENSORS_FTSTEUTATES=m CONFIG_SENSORS_GL518SM=m CONFIG_SENSORS_GL520SM=m CONFIG_SENSORS_G760A=m CONFIG_SENSORS_G762=m CONFIG_SENSORS_GPIO_FAN=m CONFIG_SENSORS_HIH6130=m CONFIG_SENSORS_IBMAEM=m CONFIG_SENSORS_IBMPEX=m CONFIG_SENSORS_IIO_HWMON=m CONFIG_SENSORS_IT87=m CONFIG_SENSORS_JC42=m CONFIG_SENSORS_POWR1220=m CONFIG_SENSORS_LAN966X=m CONFIG_SENSORS_LINEAGE=m CONFIG_SENSORS_LTC2945=m CONFIG_SENSORS_LTC2947=m CONFIG_SENSORS_LTC2947_I2C=m CONFIG_SENSORS_LTC2947_SPI=m CONFIG_SENSORS_LTC2990=m CONFIG_SENSORS_LTC2992=m CONFIG_SENSORS_LTC4151=m CONFIG_SENSORS_LTC4215=m CONFIG_SENSORS_LTC4222=m CONFIG_SENSORS_LTC4245=m CONFIG_SENSORS_LTC4260=m CONFIG_SENSORS_LTC4261=m CONFIG_SENSORS_MAX1111=m CONFIG_SENSORS_MAX127=m CONFIG_SENSORS_MAX16065=m CONFIG_SENSORS_MAX1619=m CONFIG_SENSORS_MAX1668=m CONFIG_SENSORS_MAX197=m CONFIG_SENSORS_MAX31722=m CONFIG_SENSORS_MAX31730=m CONFIG_SENSORS_MAX31760=m CONFIG_SENSORS_MAX6620=m CONFIG_SENSORS_MAX6621=m CONFIG_SENSORS_MAX6639=m CONFIG_SENSORS_MAX6650=m CONFIG_SENSORS_MAX6697=m CONFIG_SENSORS_MAX31790=m CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m CONFIG_SENSORS_TC654=m CONFIG_SENSORS_TPS23861=m CONFIG_SENSORS_MENF21BMC_HWMON=m CONFIG_SENSORS_MR75203=m CONFIG_SENSORS_ADCXX=m CONFIG_SENSORS_LM63=m CONFIG_SENSORS_LM70=m CONFIG_SENSORS_LM73=m CONFIG_SENSORS_LM75=m CONFIG_SENSORS_LM77=m CONFIG_SENSORS_LM78=m CONFIG_SENSORS_LM80=m CONFIG_SENSORS_LM83=m CONFIG_SENSORS_LM85=m CONFIG_SENSORS_LM87=m CONFIG_SENSORS_LM90=m CONFIG_SENSORS_LM92=m CONFIG_SENSORS_LM93=m CONFIG_SENSORS_LM95234=m CONFIG_SENSORS_LM95241=m CONFIG_SENSORS_LM95245=m CONFIG_SENSORS_PC87360=m CONFIG_SENSORS_PC87427=m CONFIG_SENSORS_NTC_THERMISTOR=m CONFIG_SENSORS_NCT6683=m CONFIG_SENSORS_NCT6775_CORE=m CONFIG_SENSORS_NCT6775=m CONFIG_SENSORS_NCT6775_I2C=m CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NCT7904=m CONFIG_SENSORS_NPCM7XX=m CONFIG_SENSORS_NSA320=m CONFIG_SENSORS_NZXT_KRAKEN2=m CONFIG_SENSORS_NZXT_SMART2=m CONFIG_SENSORS_OCC_P8_I2C=m CONFIG_SENSORS_OCC_P9_SBE=m CONFIG_SENSORS_OCC=m CONFIG_SENSORS_PCF8591=m CONFIG_SENSORS_PECI_CPUTEMP=m CONFIG_SENSORS_PECI_DIMMTEMP=m CONFIG_SENSORS_PECI=m CONFIG_PMBUS=m CONFIG_SENSORS_PMBUS=m CONFIG_SENSORS_ADM1266=m CONFIG_SENSORS_ADM1275=m CONFIG_SENSORS_BEL_PFE=m CONFIG_SENSORS_BPA_RS600=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_FSP_3Y=m CONFIG_SENSORS_IBM_CFFPS=m CONFIG_SENSORS_DPS920AB=m CONFIG_SENSORS_INSPUR_IPSPS=m CONFIG_SENSORS_IR35221=m CONFIG_SENSORS_IR36021=m CONFIG_SENSORS_IR38064=m CONFIG_SENSORS_IR38064_REGULATOR=y CONFIG_SENSORS_IRPS5401=m CONFIG_SENSORS_ISL68137=m CONFIG_SENSORS_LM25066=m CONFIG_SENSORS_LM25066_REGULATOR=y CONFIG_SENSORS_LT7182S=m CONFIG_SENSORS_LTC2978=m CONFIG_SENSORS_LTC2978_REGULATOR=y CONFIG_SENSORS_LTC3815=m CONFIG_SENSORS_MAX15301=m CONFIG_SENSORS_MAX16064=m CONFIG_SENSORS_MAX16601=m CONFIG_SENSORS_MAX20730=m CONFIG_SENSORS_MAX20751=m CONFIG_SENSORS_MAX31785=m CONFIG_SENSORS_MAX34440=m CONFIG_SENSORS_MAX8688=m CONFIG_SENSORS_MP2888=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP5023=m CONFIG_SENSORS_PIM4328=m CONFIG_SENSORS_PLI1209BC=m CONFIG_SENSORS_PLI1209BC_REGULATOR=y CONFIG_SENSORS_PM6764TR=m CONFIG_SENSORS_PXE1610=m CONFIG_SENSORS_Q54SJ108A2=m CONFIG_SENSORS_STPDDC60=m CONFIG_SENSORS_TPS40422=m CONFIG_SENSORS_TPS53679=m CONFIG_SENSORS_TPS546D24=m CONFIG_SENSORS_UCD9000=m CONFIG_SENSORS_UCD9200=m CONFIG_SENSORS_XDPE152=m CONFIG_SENSORS_XDPE122=m CONFIG_SENSORS_XDPE122_REGULATOR=y CONFIG_SENSORS_ZL6100=m CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_SENSORS_SL28CPLD=m CONFIG_SENSORS_SBTSI=m CONFIG_SENSORS_SBRMI=m CONFIG_SENSORS_SHT15=m CONFIG_SENSORS_SHT21=m CONFIG_SENSORS_SHT3x=m CONFIG_SENSORS_SHT4x=m CONFIG_SENSORS_SHTC1=m CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SY7636A=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_EMC1403=m CONFIG_SENSORS_EMC2103=m CONFIG_SENSORS_EMC2305=m CONFIG_SENSORS_EMC6W201=m CONFIG_SENSORS_SMSC47M1=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SCH56XX_COMMON=m CONFIG_SENSORS_SCH5627=m CONFIG_SENSORS_SCH5636=m CONFIG_SENSORS_STTS751=m CONFIG_SENSORS_SMM665=m CONFIG_SENSORS_ADC128D818=m CONFIG_SENSORS_ADS7828=m CONFIG_SENSORS_ADS7871=m CONFIG_SENSORS_AMC6821=m CONFIG_SENSORS_INA209=m CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA238=m CONFIG_SENSORS_INA3221=m CONFIG_SENSORS_TC74=m CONFIG_SENSORS_THMC50=m CONFIG_SENSORS_TMP102=m CONFIG_SENSORS_TMP103=m CONFIG_SENSORS_TMP108=m CONFIG_SENSORS_TMP401=m CONFIG_SENSORS_TMP421=m CONFIG_SENSORS_TMP464=m CONFIG_SENSORS_TMP513=m CONFIG_SENSORS_VIA686A=m CONFIG_SENSORS_VT1211=m CONFIG_SENSORS_VT8231=m CONFIG_SENSORS_W83773G=m CONFIG_SENSORS_W83781D=m CONFIG_SENSORS_W83791D=m CONFIG_SENSORS_W83792D=m CONFIG_SENSORS_W83793=m CONFIG_SENSORS_W83795=m CONFIG_SENSORS_W83795_FANCTRL=y CONFIG_SENSORS_W83L785TS=m CONFIG_SENSORS_W83L786NG=m CONFIG_SENSORS_W83627HF=m CONFIG_SENSORS_W83627EHF=m CONFIG_SENSORS_WM831X=m CONFIG_SENSORS_XGENE=m CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m # # ACPI drivers # CONFIG_SENSORS_ACPI_POWER=m CONFIG_THERMAL=y CONFIG_THERMAL_NETLINK=y CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_OF=y CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set # CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set CONFIG_THERMAL_GOV_FAIR_SHARE=y CONFIG_THERMAL_GOV_STEP_WISE=y CONFIG_THERMAL_GOV_BANG_BANG=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y CONFIG_CPU_FREQ_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_THERMAL_MMIO=m CONFIG_HISI_THERMAL=m CONFIG_IMX_THERMAL=m CONFIG_IMX_SC_THERMAL=m CONFIG_IMX8MM_THERMAL=m CONFIG_K3_THERMAL=m CONFIG_QORIQ_THERMAL=m CONFIG_SPEAR_THERMAL=m CONFIG_SUN8I_THERMAL=m CONFIG_ROCKCHIP_THERMAL=m CONFIG_RCAR_THERMAL=m CONFIG_RCAR_GEN3_THERMAL=m CONFIG_RZG2L_THERMAL=m CONFIG_KIRKWOOD_THERMAL=m CONFIG_DOVE_THERMAL=m CONFIG_ARMADA_THERMAL=m CONFIG_DA9062_THERMAL=m CONFIG_MTK_THERMAL=m # # Intel thermal drivers # # # ACPI INT340X thermal drivers # # end of ACPI INT340X thermal drivers CONFIG_INTEL_MENLOW=m # end of Intel thermal drivers # # Broadcom thermal drivers # CONFIG_BCM2711_THERMAL=m CONFIG_BCM2835_THERMAL=m CONFIG_BRCMSTB_THERMAL=m CONFIG_BCM_NS_THERMAL=m CONFIG_BCM_SR_THERMAL=m # end of Broadcom thermal drivers # # Texas Instruments thermal drivers # CONFIG_TI_SOC_THERMAL=m CONFIG_TI_THERMAL=y CONFIG_OMAP3_THERMAL=y CONFIG_OMAP4_THERMAL=y CONFIG_OMAP5_THERMAL=y CONFIG_DRA752_THERMAL=y # end of Texas Instruments thermal drivers # # Samsung thermal drivers # CONFIG_EXYNOS_THERMAL=m # end of Samsung thermal drivers # # NVIDIA Tegra thermal drivers # CONFIG_TEGRA_SOCTHERM=m CONFIG_TEGRA_BPMP_THERMAL=m CONFIG_TEGRA30_TSENSOR=m # end of NVIDIA Tegra thermal drivers CONFIG_GENERIC_ADC_THERMAL=m # # Qualcomm thermal drivers # CONFIG_QCOM_TSENS=m CONFIG_QCOM_SPMI_ADC_TM5=m CONFIG_QCOM_SPMI_TEMP_ALARM=m # end of Qualcomm thermal drivers CONFIG_UNIPHIER_THERMAL=m CONFIG_SPRD_THERMAL=m CONFIG_KHADAS_MCU_FAN_THERMAL=m CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y CONFIG_WATCHDOG_NOWAYOUT=y CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y CONFIG_WATCHDOG_OPEN_TIMEOUT=0 CONFIG_WATCHDOG_SYSFS=y CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT=y # # Watchdog Pretimeout Governors # CONFIG_WATCHDOG_PRETIMEOUT_GOV=y CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=m CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=m # CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP is not set CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y # # Watchdog Device Drivers # CONFIG_SOFT_WATCHDOG=m CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y CONFIG_DA9052_WATCHDOG=m CONFIG_DA9055_WATCHDOG=m CONFIG_DA9063_WATCHDOG=m CONFIG_DA9062_WATCHDOG=m CONFIG_GPIO_WATCHDOG=m CONFIG_MENF21BMC_WATCHDOG=m CONFIG_MENZ069_WATCHDOG=m CONFIG_WDAT_WDT=m CONFIG_WM831X_WATCHDOG=m CONFIG_XILINX_WATCHDOG=m CONFIG_ZIIRAVE_WATCHDOG=m CONFIG_RAVE_SP_WATCHDOG=m CONFIG_MLX_WDT=m CONFIG_SL28CPLD_WATCHDOG=m CONFIG_ARMADA_37XX_WATCHDOG=m CONFIG_ASM9260_WATCHDOG=m CONFIG_AT91RM9200_WATCHDOG=m CONFIG_AT91SAM9X_WATCHDOG=m CONFIG_SAMA5D4_WATCHDOG=m CONFIG_CADENCE_WATCHDOG=m CONFIG_FTWDT010_WATCHDOG=m CONFIG_S3C2410_WATCHDOG=m CONFIG_DW_WATCHDOG=m CONFIG_EP93XX_WATCHDOG=m CONFIG_OMAP_WATCHDOG=m CONFIG_PNX4008_WATCHDOG=m CONFIG_DAVINCI_WATCHDOG=m CONFIG_K3_RTI_WATCHDOG=m CONFIG_RN5T618_WATCHDOG=m CONFIG_SUNXI_WATCHDOG=m CONFIG_NPCM7XX_WATCHDOG=m CONFIG_STMP3XXX_RTC_WATCHDOG=m CONFIG_TS4800_WATCHDOG=m CONFIG_TS72XX_WATCHDOG=m CONFIG_MAX63XX_WATCHDOG=m CONFIG_MAX77620_WATCHDOG=m CONFIG_IMX2_WDT=m CONFIG_IMX7ULP_WDT=m CONFIG_RETU_WATCHDOG=m CONFIG_MOXART_WDT=m CONFIG_ST_LPC_WATCHDOG=m CONFIG_TEGRA_WATCHDOG=m CONFIG_QCOM_WDT=m CONFIG_MESON_GXBB_WATCHDOG=m CONFIG_MESON_WATCHDOG=m CONFIG_MEDIATEK_WATCHDOG=m CONFIG_DIGICOLOR_WATCHDOG=m CONFIG_LPC18XX_WATCHDOG=m CONFIG_RENESAS_WDT=m CONFIG_RENESAS_RZAWDT=m CONFIG_RENESAS_RZN1WDT=m CONFIG_RENESAS_RZG2LWDT=m CONFIG_ASPEED_WATCHDOG=m CONFIG_UNIPHIER_WATCHDOG=m CONFIG_RTD119X_WATCHDOG=y CONFIG_REALTEK_OTTO_WDT=m CONFIG_SPRD_WATCHDOG=m CONFIG_PM8916_WATCHDOG=m CONFIG_VISCONTI_WATCHDOG=m CONFIG_MSC313E_WATCHDOG=m CONFIG_APPLE_WATCHDOG=m CONFIG_SUNPLUS_WATCHDOG=m CONFIG_ALIM7101_WDT=m CONFIG_SC520_WDT=m CONFIG_I6300ESB_WDT=m CONFIG_ITCO_WDT=m CONFIG_ITCO_VENDOR_SUPPORT=y CONFIG_KEMPLD_WDT=m CONFIG_RDC321X_WDT=m CONFIG_BCM47XX_WDT=m CONFIG_BCM2835_WDT=m CONFIG_BCM_KONA_WDT=m CONFIG_BCM_KONA_WDT_DEBUG=y CONFIG_BCM7038_WDT=m CONFIG_IMGPDC_WDT=m CONFIG_MPC5200_WDT=y CONFIG_MEN_A21_WDT=m CONFIG_UML_WATCHDOG=m # # PCI-based Watchdog Cards # CONFIG_PCIPCWATCHDOG=m CONFIG_WDTPCI=m # # USB-based Watchdog Cards # CONFIG_USBPCWATCHDOG=m CONFIG_SSB_POSSIBLE=y CONFIG_SSB=m CONFIG_SSB_SPROM=y CONFIG_SSB_BLOCKIO=y CONFIG_SSB_PCIHOST_POSSIBLE=y CONFIG_SSB_PCIHOST=y CONFIG_SSB_B43_PCI_BRIDGE=y CONFIG_SSB_PCMCIAHOST_POSSIBLE=y CONFIG_SSB_PCMCIAHOST=y CONFIG_SSB_SDIOHOST_POSSIBLE=y CONFIG_SSB_SDIOHOST=y CONFIG_SSB_HOST_SOC=y CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y CONFIG_SSB_DRIVER_PCICORE=y CONFIG_SSB_DRIVER_GPIO=y CONFIG_BCMA_POSSIBLE=y CONFIG_BCMA=m CONFIG_BCMA_BLOCKIO=y CONFIG_BCMA_HOST_PCI_POSSIBLE=y CONFIG_BCMA_HOST_PCI=y CONFIG_BCMA_HOST_SOC=y CONFIG_BCMA_DRIVER_PCI=y CONFIG_BCMA_DRIVER_MIPS=y CONFIG_BCMA_PFLASH=y CONFIG_BCMA_SFLASH=y CONFIG_BCMA_NFLASH=y CONFIG_BCMA_DRIVER_GMAC_CMN=y CONFIG_BCMA_DRIVER_GPIO=y CONFIG_BCMA_DEBUG=y # # Multifunction device drivers # CONFIG_MFD_CORE=y CONFIG_MFD_ACT8945A=m CONFIG_MFD_SUN4I_GPADC=m CONFIG_MFD_AT91_USART=y CONFIG_MFD_ATMEL_FLEXCOM=m CONFIG_MFD_ATMEL_HLCDC=m CONFIG_MFD_ATMEL_SMC=y CONFIG_MFD_BCM590XX=m CONFIG_MFD_BD9571MWV=m CONFIG_MFD_AXP20X=m CONFIG_MFD_AXP20X_I2C=m CONFIG_MFD_CROS_EC_DEV=m CONFIG_MFD_MADERA=m CONFIG_MFD_MADERA_I2C=m CONFIG_MFD_MADERA_SPI=m CONFIG_MFD_CS47L15=y CONFIG_MFD_CS47L35=y CONFIG_MFD_CS47L85=y CONFIG_MFD_CS47L90=y CONFIG_MFD_CS47L92=y CONFIG_MFD_ASIC3=y CONFIG_PMIC_DA9052=y CONFIG_MFD_DA9052_SPI=y CONFIG_MFD_DA9062=m CONFIG_MFD_DA9063=m CONFIG_MFD_DA9150=m CONFIG_MFD_DLN2=m CONFIG_MFD_ENE_KB3930=m CONFIG_MFD_EXYNOS_LPASS=m CONFIG_MFD_GATEWORKS_GSC=m CONFIG_MFD_MC13XXX=m CONFIG_MFD_MC13XXX_SPI=m CONFIG_MFD_MC13XXX_I2C=m CONFIG_MFD_MP2629=m CONFIG_MFD_MXS_LRADC=m CONFIG_MFD_MX25_TSADC=m CONFIG_MFD_HI6421_PMIC=m CONFIG_MFD_HI6421_SPMI=m CONFIG_MFD_HI655X_PMIC=m CONFIG_HTC_PASIC3=m CONFIG_LPC_ICH=m CONFIG_LPC_SCH=m CONFIG_MFD_IQS62X=m CONFIG_MFD_JANZ_CMODIO=m CONFIG_MFD_KEMPLD=m CONFIG_MFD_88PM800=m CONFIG_MFD_88PM805=m CONFIG_MFD_MAX14577=m CONFIG_MFD_MAX77650=m CONFIG_MFD_MAX77686=m CONFIG_MFD_MAX77693=m CONFIG_MFD_MAX77714=m CONFIG_MFD_MAX8907=m CONFIG_MFD_MT6360=m CONFIG_MFD_MT6370=m CONFIG_MFD_MT6397=m CONFIG_MFD_MENF21BMC=m CONFIG_MFD_OCELOT=m CONFIG_EZX_PCAP=y CONFIG_MFD_CPCAP=m CONFIG_MFD_VIPERBOARD=m CONFIG_MFD_NTXEC=m CONFIG_MFD_RETU=m CONFIG_MFD_PCF50633=m CONFIG_PCF50633_ADC=m CONFIG_PCF50633_GPIO=m CONFIG_MFD_PM8XXX=m CONFIG_MFD_SPMI_PMIC=m CONFIG_MFD_SY7636A=m CONFIG_MFD_RDC321X=m CONFIG_MFD_RT4831=m CONFIG_MFD_RT5033=m CONFIG_MFD_RT5120=m CONFIG_MFD_RK808=m CONFIG_MFD_RN5T618=m CONFIG_MFD_SI476X_CORE=m CONFIG_MFD_SIMPLE_MFD_I2C=m CONFIG_MFD_SL28CPLD=m CONFIG_MFD_SM501=m CONFIG_MFD_SM501_GPIO=y CONFIG_MFD_SKY81452=m CONFIG_MFD_SC27XX_PMIC=m CONFIG_ABX500_CORE=y CONFIG_MFD_STMPE=y # # STMicroelectronics STMPE Interface Drivers # CONFIG_STMPE_SPI=y # end of STMicroelectronics STMPE Interface Drivers CONFIG_MFD_SUN6I_PRCM=y CONFIG_MFD_SYSCON=y CONFIG_MFD_TI_AM335X_TSCADC=m CONFIG_MFD_LP3943=m CONFIG_MFD_TI_LMU=m CONFIG_MFD_OMAP_USB_HOST=y CONFIG_TPS6105X=m CONFIG_TPS65010=m CONFIG_TPS6507X=m CONFIG_MFD_TPS65086=m CONFIG_MFD_TPS65217=m CONFIG_MFD_TI_LP873X=m CONFIG_MFD_TI_LP87565=m CONFIG_MFD_TPS65218=m CONFIG_MFD_TPS65912=m CONFIG_MFD_TPS65912_I2C=m CONFIG_MFD_TPS65912_SPI=m CONFIG_MFD_WL1273_CORE=m CONFIG_MFD_LM3533=m CONFIG_MFD_TIMBERDALE=m CONFIG_MFD_TQMX86=m CONFIG_MFD_VX855=m CONFIG_MFD_ARIZONA=m CONFIG_MFD_ARIZONA_I2C=m CONFIG_MFD_ARIZONA_SPI=m CONFIG_MFD_CS47L24=y CONFIG_MFD_WM5102=y CONFIG_MFD_WM5110=y CONFIG_MFD_WM8997=y CONFIG_MFD_WM8998=y CONFIG_MFD_WM831X=y CONFIG_MFD_WM831X_SPI=y CONFIG_MFD_WM8994=m CONFIG_MFD_STW481X=m CONFIG_MFD_STM32_LPTIMER=m CONFIG_MFD_STM32_TIMERS=m CONFIG_MFD_STMFX=m CONFIG_MFD_WCD934X=m CONFIG_MFD_ATC260X=m CONFIG_MFD_ATC260X_I2C=m CONFIG_MFD_KHADAS_MCU=m CONFIG_MFD_ACER_A500_EC=m CONFIG_MFD_QCOM_PM8008=m CONFIG_RAVE_SP_CORE=m CONFIG_MFD_INTEL_M10_BMC=m CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m # end of Multifunction device drivers CONFIG_REGULATOR=y CONFIG_REGULATOR_DEBUG=y CONFIG_REGULATOR_FIXED_VOLTAGE=m CONFIG_REGULATOR_VIRTUAL_CONSUMER=m CONFIG_REGULATOR_USERSPACE_CONSUMER=m CONFIG_REGULATOR_88PG86X=m CONFIG_REGULATOR_88PM800=m CONFIG_REGULATOR_ACT8865=m CONFIG_REGULATOR_ACT8945A=m CONFIG_REGULATOR_AD5398=m CONFIG_REGULATOR_ANATOP=m CONFIG_REGULATOR_ARM_SCMI=m CONFIG_REGULATOR_ATC260X=m CONFIG_REGULATOR_AXP20X=m CONFIG_REGULATOR_BCM590XX=m CONFIG_REGULATOR_BD9571MWV=m CONFIG_REGULATOR_CPCAP=m CONFIG_REGULATOR_CROS_EC=m CONFIG_REGULATOR_DA9052=m CONFIG_REGULATOR_DA9062=m CONFIG_REGULATOR_DA9063=m CONFIG_REGULATOR_DA9121=m CONFIG_REGULATOR_DA9210=m CONFIG_REGULATOR_DA9211=m CONFIG_REGULATOR_FAN53555=m CONFIG_REGULATOR_FAN53880=m CONFIG_REGULATOR_GPIO=m CONFIG_REGULATOR_HI6421=m CONFIG_REGULATOR_HI6421V530=m CONFIG_REGULATOR_HI655X=m CONFIG_REGULATOR_HI6421V600=m CONFIG_REGULATOR_ISL9305=m CONFIG_REGULATOR_ISL6271A=m CONFIG_REGULATOR_LM363X=m CONFIG_REGULATOR_LP3971=m CONFIG_REGULATOR_LP3972=m CONFIG_REGULATOR_LP872X=m CONFIG_REGULATOR_LP873X=m CONFIG_REGULATOR_LP8755=m CONFIG_REGULATOR_LP87565=m CONFIG_REGULATOR_LTC3589=m CONFIG_REGULATOR_LTC3676=m CONFIG_REGULATOR_MAX14577=m CONFIG_REGULATOR_MAX1586=m CONFIG_REGULATOR_MAX77620=m CONFIG_REGULATOR_MAX77650=m CONFIG_REGULATOR_MAX8649=m CONFIG_REGULATOR_MAX8660=m CONFIG_REGULATOR_MAX8893=m CONFIG_REGULATOR_MAX8907=m CONFIG_REGULATOR_MAX8952=m CONFIG_REGULATOR_MAX8973=m CONFIG_REGULATOR_MAX20086=m CONFIG_REGULATOR_MAX77686=m CONFIG_REGULATOR_MAX77693=m CONFIG_REGULATOR_MAX77802=m CONFIG_REGULATOR_MAX77826=m CONFIG_REGULATOR_MC13XXX_CORE=m CONFIG_REGULATOR_MC13783=m CONFIG_REGULATOR_MC13892=m CONFIG_REGULATOR_MCP16502=m CONFIG_REGULATOR_MP5416=m CONFIG_REGULATOR_MP8859=m CONFIG_REGULATOR_MP886X=m CONFIG_REGULATOR_MPQ7920=m CONFIG_REGULATOR_MT6311=m CONFIG_REGULATOR_MT6315=m CONFIG_REGULATOR_MT6323=m CONFIG_REGULATOR_MT6331=m CONFIG_REGULATOR_MT6332=m CONFIG_REGULATOR_MT6358=m CONFIG_REGULATOR_MT6359=m CONFIG_REGULATOR_MT6360=m CONFIG_REGULATOR_MT6370=m CONFIG_REGULATOR_MT6380=m CONFIG_REGULATOR_MT6397=m CONFIG_REGULATOR_PBIAS=m CONFIG_REGULATOR_PCA9450=m CONFIG_REGULATOR_PCAP=m CONFIG_REGULATOR_PCF50633=m CONFIG_REGULATOR_PF8X00=m CONFIG_REGULATOR_PFUZE100=m CONFIG_REGULATOR_PV88060=m CONFIG_REGULATOR_PV88080=m CONFIG_REGULATOR_PV88090=m CONFIG_REGULATOR_PWM=m CONFIG_REGULATOR_QCOM_RPMH=m CONFIG_REGULATOR_QCOM_SMD_RPM=m CONFIG_REGULATOR_QCOM_SPMI=m CONFIG_REGULATOR_QCOM_USB_VBUS=m CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m CONFIG_REGULATOR_RK808=m CONFIG_REGULATOR_RN5T618=m CONFIG_REGULATOR_RT4801=m CONFIG_REGULATOR_RT4831=m CONFIG_REGULATOR_RT5033=m CONFIG_REGULATOR_RT5120=m CONFIG_REGULATOR_RT5190A=m CONFIG_REGULATOR_RT5759=m CONFIG_REGULATOR_RT6160=m CONFIG_REGULATOR_RT6245=m CONFIG_REGULATOR_RTQ2134=m CONFIG_REGULATOR_RTMV20=m CONFIG_REGULATOR_RTQ6752=m CONFIG_REGULATOR_S2MPA01=m CONFIG_REGULATOR_S2MPS11=m CONFIG_REGULATOR_S5M8767=m CONFIG_REGULATOR_SC2731=m CONFIG_REGULATOR_SKY81452=m CONFIG_REGULATOR_SLG51000=m CONFIG_REGULATOR_STM32_BOOSTER=m CONFIG_REGULATOR_STM32_VREFBUF=m CONFIG_REGULATOR_STM32_PWR=y CONFIG_REGULATOR_TI_ABB=m CONFIG_REGULATOR_STW481X_VMMC=y CONFIG_REGULATOR_SY7636A=m CONFIG_REGULATOR_SY8106A=m CONFIG_REGULATOR_SY8824X=m CONFIG_REGULATOR_SY8827N=m CONFIG_REGULATOR_TPS51632=m CONFIG_REGULATOR_TPS6105X=m CONFIG_REGULATOR_TPS62360=m CONFIG_REGULATOR_TPS6286X=m CONFIG_REGULATOR_TPS65023=m CONFIG_REGULATOR_TPS6507X=m CONFIG_REGULATOR_TPS65086=m CONFIG_REGULATOR_TPS65132=m CONFIG_REGULATOR_TPS65217=m CONFIG_REGULATOR_TPS65218=m CONFIG_REGULATOR_TPS6524X=m CONFIG_REGULATOR_TPS65912=m CONFIG_REGULATOR_TPS68470=m CONFIG_REGULATOR_UNIPHIER=m CONFIG_REGULATOR_VCTRL=m CONFIG_REGULATOR_WM831X=m CONFIG_REGULATOR_WM8994=m CONFIG_REGULATOR_QCOM_LABIBB=m CONFIG_RC_CORE=m CONFIG_LIRC=y CONFIG_RC_MAP=m CONFIG_RC_DECODERS=y CONFIG_IR_IMON_DECODER=m CONFIG_IR_JVC_DECODER=m CONFIG_IR_MCE_KBD_DECODER=m CONFIG_IR_NEC_DECODER=m CONFIG_IR_RC5_DECODER=m CONFIG_IR_RC6_DECODER=m CONFIG_IR_RCMM_DECODER=m CONFIG_IR_SANYO_DECODER=m CONFIG_IR_SHARP_DECODER=m CONFIG_IR_SONY_DECODER=m CONFIG_IR_XMP_DECODER=m CONFIG_RC_DEVICES=y CONFIG_IR_ENE=m CONFIG_IR_FINTEK=m CONFIG_IR_GPIO_CIR=m CONFIG_IR_GPIO_TX=m CONFIG_IR_HIX5HD2=m CONFIG_IR_IGORPLUGUSB=m CONFIG_IR_IGUANA=m CONFIG_IR_IMON=m CONFIG_IR_IMON_RAW=m CONFIG_IR_ITE_CIR=m CONFIG_IR_MCEUSB=m CONFIG_IR_MESON=m CONFIG_IR_MESON_TX=m CONFIG_IR_MTK=m CONFIG_IR_NUVOTON=m CONFIG_IR_PWM_TX=m CONFIG_IR_REDRAT3=m CONFIG_IR_RX51=m CONFIG_IR_SERIAL=m CONFIG_IR_SERIAL_TRANSMITTER=y CONFIG_IR_SPI=m CONFIG_IR_STREAMZAP=m CONFIG_IR_SUNXI=m CONFIG_IR_TOY=m CONFIG_IR_TTUSBIR=m CONFIG_IR_WINBOND_CIR=m CONFIG_RC_ATI_REMOTE=m CONFIG_RC_LOOPBACK=m CONFIG_RC_ST=m CONFIG_RC_XBOX_DVD=m CONFIG_IR_IMG=m CONFIG_IR_IMG_RAW=y CONFIG_IR_IMG_HW=y CONFIG_IR_IMG_NEC=y CONFIG_IR_IMG_JVC=y CONFIG_IR_IMG_SONY=y CONFIG_IR_IMG_SHARP=y CONFIG_IR_IMG_SANYO=y CONFIG_IR_IMG_RC5=y CONFIG_IR_IMG_RC6=y CONFIG_CEC_CORE=m CONFIG_CEC_NOTIFIER=y CONFIG_CEC_PIN=y # # CEC support # CONFIG_MEDIA_CEC_RC=y CONFIG_CEC_PIN_ERROR_INJ=y CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_CEC_CH7322=m CONFIG_CEC_CROS_EC=m CONFIG_CEC_MESON_AO=m CONFIG_CEC_MESON_G12A_AO=m CONFIG_CEC_GPIO=m CONFIG_CEC_SAMSUNG_S5P=m CONFIG_CEC_STI=m CONFIG_CEC_STM32=m CONFIG_CEC_TEGRA=m CONFIG_CEC_SECO=m CONFIG_CEC_SECO_RC=y CONFIG_USB_PULSE8_CEC=m CONFIG_USB_RAINSHADOW_CEC=m # end of CEC support CONFIG_MEDIA_SUPPORT=m CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUBDRV_AUTOSELECT=y # # Media device types # CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_ANALOG_TV_SUPPORT=y CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y CONFIG_MEDIA_RADIO_SUPPORT=y CONFIG_MEDIA_SDR_SUPPORT=y CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_MEDIA_TEST_SUPPORT=y # end of Media device types CONFIG_VIDEO_DEV=m CONFIG_MEDIA_CONTROLLER=y CONFIG_DVB_CORE=m # # Video4Linux options # CONFIG_VIDEO_V4L2_I2C=y CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_ADV_DEBUG=y CONFIG_VIDEO_FIXED_MINOR_RANGES=y CONFIG_VIDEO_TUNER=m CONFIG_V4L2_JPEG_HELPER=m CONFIG_V4L2_H264=m CONFIG_V4L2_VP9=m CONFIG_V4L2_MEM2MEM_DEV=m CONFIG_V4L2_FLASH_LED_CLASS=m CONFIG_V4L2_FWNODE=m CONFIG_V4L2_ASYNC=m CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_DMA_SG=m CONFIG_VIDEOBUF_VMALLOC=m CONFIG_VIDEOBUF_DMA_CONTIG=m # end of Video4Linux options # # Media controller options # CONFIG_MEDIA_CONTROLLER_DVB=y CONFIG_MEDIA_CONTROLLER_REQUEST_API=y # end of Media controller options # # Digital TV options # CONFIG_DVB_MMAP=y CONFIG_DVB_NET=y CONFIG_DVB_MAX_ADAPTERS=16 CONFIG_DVB_DYNAMIC_MINORS=y CONFIG_DVB_DEMUX_SECTION_LOSS_LOG=y CONFIG_DVB_ULE_DEBUG=y # end of Digital TV options # # Media drivers # # # Drivers filtered as selected at 'Filter media drivers' # # # Media drivers # CONFIG_MEDIA_USB_SUPPORT=y # # Webcam devices # CONFIG_USB_GSPCA=m CONFIG_USB_GSPCA_BENQ=m CONFIG_USB_GSPCA_CONEX=m CONFIG_USB_GSPCA_CPIA1=m CONFIG_USB_GSPCA_DTCS033=m CONFIG_USB_GSPCA_ETOMS=m CONFIG_USB_GSPCA_FINEPIX=m CONFIG_USB_GSPCA_JEILINJ=m CONFIG_USB_GSPCA_JL2005BCD=m CONFIG_USB_GSPCA_KINECT=m CONFIG_USB_GSPCA_KONICA=m CONFIG_USB_GSPCA_MARS=m CONFIG_USB_GSPCA_MR97310A=m CONFIG_USB_GSPCA_NW80X=m CONFIG_USB_GSPCA_OV519=m CONFIG_USB_GSPCA_OV534=m CONFIG_USB_GSPCA_OV534_9=m CONFIG_USB_GSPCA_PAC207=m CONFIG_USB_GSPCA_PAC7302=m CONFIG_USB_GSPCA_PAC7311=m CONFIG_USB_GSPCA_SE401=m CONFIG_USB_GSPCA_SN9C2028=m CONFIG_USB_GSPCA_SN9C20X=m CONFIG_USB_GSPCA_SONIXB=m CONFIG_USB_GSPCA_SONIXJ=m CONFIG_USB_GSPCA_SPCA1528=m CONFIG_USB_GSPCA_SPCA500=m CONFIG_USB_GSPCA_SPCA501=m CONFIG_USB_GSPCA_SPCA505=m CONFIG_USB_GSPCA_SPCA506=m CONFIG_USB_GSPCA_SPCA508=m CONFIG_USB_GSPCA_SPCA561=m CONFIG_USB_GSPCA_SQ905=m CONFIG_USB_GSPCA_SQ905C=m CONFIG_USB_GSPCA_SQ930X=m CONFIG_USB_GSPCA_STK014=m CONFIG_USB_GSPCA_STK1135=m CONFIG_USB_GSPCA_STV0680=m CONFIG_USB_GSPCA_SUNPLUS=m CONFIG_USB_GSPCA_T613=m CONFIG_USB_GSPCA_TOPRO=m CONFIG_USB_GSPCA_TOUPTEK=m CONFIG_USB_GSPCA_TV8532=m CONFIG_USB_GSPCA_VC032X=m CONFIG_USB_GSPCA_VICAM=m CONFIG_USB_GSPCA_XIRLINK_CIT=m CONFIG_USB_GSPCA_ZC3XX=m CONFIG_USB_GL860=m CONFIG_USB_M5602=m CONFIG_USB_STV06XX=m CONFIG_USB_PWC=m CONFIG_USB_PWC_DEBUG=y CONFIG_USB_PWC_INPUT_EVDEV=y CONFIG_USB_S2255=m CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y # # Analog TV USB devices # CONFIG_VIDEO_HDPVR=m CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_PVRUSB2_DEBUGIFC=y CONFIG_VIDEO_STK1160_COMMON=m CONFIG_VIDEO_STK1160=m # # Analog/digital TV USB devices # CONFIG_VIDEO_AU0828=m CONFIG_VIDEO_AU0828_V4L2=y CONFIG_VIDEO_AU0828_RC=y CONFIG_VIDEO_CX231XX=m CONFIG_VIDEO_CX231XX_RC=y CONFIG_VIDEO_CX231XX_DVB=m # # Digital TV USB devices # CONFIG_DVB_AS102=m CONFIG_DVB_B2C2_FLEXCOP_USB=m CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG=y CONFIG_DVB_USB_V2=m CONFIG_DVB_USB_AF9015=m CONFIG_DVB_USB_AF9035=m CONFIG_DVB_USB_ANYSEE=m CONFIG_DVB_USB_AU6610=m CONFIG_DVB_USB_AZ6007=m CONFIG_DVB_USB_CE6230=m CONFIG_DVB_USB_DVBSKY=m CONFIG_DVB_USB_EC168=m CONFIG_DVB_USB_GL861=m CONFIG_DVB_USB_LME2510=m CONFIG_DVB_USB_MXL111SF=m CONFIG_DVB_USB_RTL28XXU=m CONFIG_DVB_USB_ZD1301=m CONFIG_DVB_USB=m CONFIG_DVB_USB_DEBUG=y CONFIG_DVB_USB_A800=m CONFIG_DVB_USB_AF9005=m CONFIG_DVB_USB_AF9005_REMOTE=m CONFIG_DVB_USB_AZ6027=m CONFIG_DVB_USB_CINERGY_T2=m CONFIG_DVB_USB_CXUSB=m CONFIG_DVB_USB_CXUSB_ANALOG=y CONFIG_DVB_USB_DIB0700=m CONFIG_DVB_USB_DIB3000MC=m CONFIG_DVB_USB_DIBUSB_MB=m CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y CONFIG_DVB_USB_DIBUSB_MC=m CONFIG_DVB_USB_DIGITV=m CONFIG_DVB_USB_DTT200U=m CONFIG_DVB_USB_DTV5100=m CONFIG_DVB_USB_DW2102=m CONFIG_DVB_USB_GP8PSK=m CONFIG_DVB_USB_M920X=m CONFIG_DVB_USB_NOVA_T_USB2=m CONFIG_DVB_USB_OPERA1=m CONFIG_DVB_USB_PCTV452E=m CONFIG_DVB_USB_TECHNISAT_USB2=m CONFIG_DVB_USB_TTUSB2=m CONFIG_DVB_USB_UMT_010=m CONFIG_DVB_USB_VP702X=m CONFIG_DVB_USB_VP7045=m CONFIG_SMS_USB_DRV=m CONFIG_DVB_TTUSB_BUDGET=m CONFIG_DVB_TTUSB_DEC=m # # Webcam, TV (analog/digital) USB devices # CONFIG_VIDEO_EM28XX=m CONFIG_VIDEO_EM28XX_V4L2=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX_RC=m # # Software defined radio USB devices # CONFIG_USB_AIRSPY=m CONFIG_USB_HACKRF=m CONFIG_USB_MSI2500=m CONFIG_MEDIA_PCI_SUPPORT=y # # Media capture support # CONFIG_STA2X11_VIP=m CONFIG_VIDEO_TW5864=m CONFIG_VIDEO_TW68=m CONFIG_VIDEO_ZORAN=m CONFIG_VIDEO_ZORAN_DC30=y CONFIG_VIDEO_ZORAN_ZR36060=y CONFIG_VIDEO_ZORAN_BUZ=y CONFIG_VIDEO_ZORAN_DC10=y CONFIG_VIDEO_ZORAN_LML33=y CONFIG_VIDEO_ZORAN_LML33R10=y CONFIG_VIDEO_ZORAN_AVS6EYES=y # # Media capture/analog TV support # CONFIG_VIDEO_DT3155=m CONFIG_VIDEO_IVTV=m CONFIG_VIDEO_FB_IVTV=m # # Media capture/analog/hybrid TV support # CONFIG_VIDEO_BT848=m CONFIG_DVB_BT8XX=m CONFIG_VIDEO_CX18=m CONFIG_VIDEO_CX25821=m CONFIG_VIDEO_CX88=m CONFIG_VIDEO_CX88_BLACKBIRD=m CONFIG_VIDEO_CX88_DVB=m CONFIG_VIDEO_CX88_ENABLE_VP3054=y CONFIG_VIDEO_CX88_VP3054=m CONFIG_VIDEO_CX88_MPEG=m CONFIG_VIDEO_SAA7134=m CONFIG_VIDEO_SAA7134_RC=y CONFIG_VIDEO_SAA7134_DVB=m CONFIG_VIDEO_SAA7164=m # # Media digital TV PCI Adapters # CONFIG_DVB_B2C2_FLEXCOP_PCI=m CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG=y CONFIG_DVB_DDBRIDGE=m CONFIG_DVB_DDBRIDGE_MSIENABLE=y CONFIG_DVB_DM1105=m CONFIG_MANTIS_CORE=m CONFIG_DVB_MANTIS=m CONFIG_DVB_HOPPER=m CONFIG_DVB_NETUP_UNIDVB=m CONFIG_DVB_NGENE=m CONFIG_DVB_PLUTO2=m CONFIG_DVB_PT1=m CONFIG_DVB_PT3=m CONFIG_DVB_SMIPCIE=m CONFIG_RADIO_ADAPTERS=m CONFIG_RADIO_MAXIRADIO=m CONFIG_RADIO_SAA7706H=m CONFIG_RADIO_SHARK=m CONFIG_RADIO_SHARK2=m CONFIG_RADIO_SI4713=m CONFIG_RADIO_TEA575X=m CONFIG_RADIO_TEA5764=m CONFIG_RADIO_TEF6862=m CONFIG_RADIO_TIMBERDALE=m CONFIG_RADIO_WL1273=m CONFIG_USB_DSBR=m CONFIG_USB_KEENE=m CONFIG_USB_MA901=m CONFIG_USB_MR800=m CONFIG_USB_RAREMONO=m CONFIG_RADIO_SI470X=m CONFIG_USB_SI470X=m CONFIG_I2C_SI470X=m CONFIG_USB_SI4713=m CONFIG_PLATFORM_SI4713=m CONFIG_I2C_SI4713=m CONFIG_RADIO_WL128X=m CONFIG_V4L_RADIO_ISA_DRIVERS=y CONFIG_RADIO_AZTECH=m CONFIG_RADIO_CADET=m CONFIG_RADIO_GEMTEK=m CONFIG_RADIO_ISA=m CONFIG_RADIO_RTRACK=m CONFIG_RADIO_RTRACK2=m CONFIG_RADIO_SF16FMI=m CONFIG_RADIO_SF16FMR2=m CONFIG_RADIO_TERRATEC=m CONFIG_RADIO_TRUST=m CONFIG_RADIO_TYPHOON=m CONFIG_RADIO_ZOLTRIX=m CONFIG_MEDIA_PLATFORM_DRIVERS=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_SDR_PLATFORM_DRIVERS=y CONFIG_DVB_PLATFORM_DRIVERS=y CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m CONFIG_VIDEO_MUX=m # # Allegro DVT media platform drivers # CONFIG_VIDEO_ALLEGRO_DVT=m # # Amlogic media platform drivers # CONFIG_VIDEO_MESON_GE2D=m # # Amphion drivers # CONFIG_VIDEO_AMPHION_VPU=m # # Aspeed media platform drivers # CONFIG_VIDEO_ASPEED=m # # Atmel media platform drivers # CONFIG_VIDEO_ATMEL_ISI=m # # Cadence media platform drivers # CONFIG_VIDEO_CADENCE_CSI2RX=m CONFIG_VIDEO_CADENCE_CSI2TX=m # # Chips&Media media platform drivers # CONFIG_VIDEO_CODA=m CONFIG_VIDEO_IMX_VDOA=m # # Intel media platform drivers # CONFIG_VIDEO_PXA27x=m # # Marvell media platform drivers # CONFIG_VIDEO_CAFE_CCIC=m CONFIG_VIDEO_MMP_CAMERA=m # # Mediatek media platform drivers # CONFIG_VIDEO_MEDIATEK_JPEG=m CONFIG_VIDEO_MEDIATEK_MDP=m CONFIG_VIDEO_MEDIATEK_VCODEC_SCP=y CONFIG_VIDEO_MEDIATEK_VCODEC_VPU=y CONFIG_VIDEO_MEDIATEK_VCODEC=m CONFIG_VIDEO_MEDIATEK_VPU=m CONFIG_VIDEO_MEDIATEK_MDP3=m # # Microchip Technology, Inc. media platform drivers # CONFIG_VIDEO_MICROCHIP_ISC=m CONFIG_VIDEO_MICROCHIP_XISC=m CONFIG_VIDEO_MICROCHIP_ISC_BASE=m CONFIG_VIDEO_MICROCHIP_CSI2DC=m # # NVidia media platform drivers # CONFIG_VIDEO_TEGRA_VDE=m # # NXP media platform drivers # CONFIG_VIDEO_IMX7_CSI=m CONFIG_VIDEO_IMX_MIPI_CSIS=m CONFIG_VIDEO_IMX_PXP=m CONFIG_VIDEO_MX2_EMMAPRP=m CONFIG_VIDEO_DW100=m CONFIG_VIDEO_IMX8_JPEG=m # # Qualcomm media platform drivers # CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_QCOM_VENUS=m # # Renesas media platform drivers # CONFIG_VIDEO_RENESAS_CEU=m CONFIG_VIDEO_RCAR_ISP=m CONFIG_VIDEO_SH_VOU=m CONFIG_VIDEO_RCAR_CSI2=m CONFIG_VIDEO_RCAR_VIN=m CONFIG_VIDEO_RZG2L_CSI2=m CONFIG_VIDEO_RZG2L_CRU=m CONFIG_VIDEO_RENESAS_FCP=m CONFIG_VIDEO_RENESAS_FDP1=m CONFIG_VIDEO_RENESAS_JPU=m CONFIG_VIDEO_RENESAS_VSP1=m CONFIG_VIDEO_RCAR_DRIF=m # # Rockchip media platform drivers # CONFIG_VIDEO_ROCKCHIP_RGA=m CONFIG_VIDEO_ROCKCHIP_ISP1=m # # Samsung media platform drivers # CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_VIDEO_SAMSUNG_EXYNOS4_IS=m CONFIG_VIDEO_EXYNOS4_IS_COMMON=m CONFIG_VIDEO_S5P_FIMC=m CONFIG_VIDEO_S5P_MIPI_CSIS=m CONFIG_VIDEO_EXYNOS_FIMC_LITE=m CONFIG_VIDEO_EXYNOS4_FIMC_IS=m CONFIG_VIDEO_EXYNOS4_ISP_DMA_CAPTURE=y CONFIG_VIDEO_S3C_CAMIF=m CONFIG_VIDEO_SAMSUNG_S5P_G2D=m CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m CONFIG_VIDEO_SAMSUNG_S5P_MFC=m # # STMicroelectronics media platform drivers # CONFIG_VIDEO_STI_BDISP=m CONFIG_DVB_C8SECTPFE=m CONFIG_VIDEO_STI_DELTA=m CONFIG_VIDEO_STI_DELTA_MJPEG=y CONFIG_VIDEO_STI_DELTA_DRIVER=m CONFIG_VIDEO_STI_HVA=m CONFIG_VIDEO_STI_HVA_DEBUGFS=y CONFIG_VIDEO_STM32_DCMI=m CONFIG_VIDEO_STM32_DMA2D=m # # Sunxi media platform drivers # CONFIG_VIDEO_SUN4I_CSI=m CONFIG_VIDEO_SUN6I_CSI=m CONFIG_VIDEO_SUN6I_MIPI_CSI2=m CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m CONFIG_VIDEO_SUN8I_DEINTERLACE=m CONFIG_VIDEO_SUN8I_ROTATE=m # # Texas Instruments drivers # CONFIG_VIDEO_TI_VPDMA=m CONFIG_VIDEO_TI_SC=m CONFIG_VIDEO_TI_CSC=m CONFIG_VIDEO_TI_CAL=m CONFIG_VIDEO_TI_CAL_MC=y CONFIG_VIDEO_TI_VPE=m CONFIG_VIDEO_TI_VPE_DEBUG=y CONFIG_VIDEO_AM437X_VPFE=m CONFIG_VIDEO_DAVINCI_VPIF_DISPLAY=m CONFIG_VIDEO_DAVINCI_VPIF_CAPTURE=m CONFIG_VIDEO_DAVINCI_VPBE_DISPLAY=m CONFIG_VIDEO_OMAP2_VOUT_VRFB=y CONFIG_VIDEO_OMAP2_VOUT=m CONFIG_VIDEO_OMAP3=m CONFIG_VIDEO_OMAP3_DEBUG=y # # Verisilicon media platform drivers # CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_IMX8M=y CONFIG_VIDEO_HANTRO_SAMA5D4=y CONFIG_VIDEO_HANTRO_ROCKCHIP=y CONFIG_VIDEO_HANTRO_SUNXI=y # # VIA media platform drivers # CONFIG_VIDEO_VIA_CAMERA=m # # Xilinx media platform drivers # CONFIG_VIDEO_XILINX=m CONFIG_VIDEO_XILINX_CSI2RXSS=m CONFIG_VIDEO_XILINX_TPG=m CONFIG_VIDEO_XILINX_VTC=m # # MMC/SDIO DVB adapters # CONFIG_SMS_SDIO_DRV=m CONFIG_V4L_TEST_DRIVERS=y CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIMC=m CONFIG_VIDEO_VIVID=m CONFIG_VIDEO_VIVID_CEC=y CONFIG_VIDEO_VIVID_MAX_DEVS=64 CONFIG_VIDEO_VISL=m CONFIG_VISL_DEBUGFS=y CONFIG_DVB_TEST_DRIVERS=y CONFIG_DVB_VIDTV=m # # FireWire (IEEE 1394) Adapters # CONFIG_DVB_FIREDTV=m CONFIG_DVB_FIREDTV_INPUT=y CONFIG_MEDIA_COMMON_OPTIONS=y # # common driver options # CONFIG_CYPRESS_FIRMWARE=m CONFIG_TTPCI_EEPROM=m CONFIG_VIDEO_CX2341X=m CONFIG_VIDEO_TVEEPROM=m CONFIG_DVB_B2C2_FLEXCOP=m CONFIG_DVB_B2C2_FLEXCOP_DEBUG=y CONFIG_SMS_SIANO_MDTV=m CONFIG_SMS_SIANO_RC=y CONFIG_SMS_SIANO_DEBUGFS=y CONFIG_VIDEO_V4L2_TPG=m CONFIG_VIDEOBUF2_CORE=m CONFIG_VIDEOBUF2_V4L2=m CONFIG_VIDEOBUF2_MEMOPS=m CONFIG_VIDEOBUF2_DMA_CONTIG=m CONFIG_VIDEOBUF2_VMALLOC=m CONFIG_VIDEOBUF2_DMA_SG=m CONFIG_VIDEOBUF2_DVB=m # end of Media drivers # # Media ancillary drivers # CONFIG_MEDIA_ATTACH=y # # IR I2C driver auto-selected by 'Autoselect ancillary drivers' # CONFIG_VIDEO_IR_I2C=m # # Camera sensor devices # CONFIG_VIDEO_APTINA_PLL=m CONFIG_VIDEO_CCS_PLL=m CONFIG_VIDEO_AR0521=m CONFIG_VIDEO_HI556=m CONFIG_VIDEO_HI846=m CONFIG_VIDEO_HI847=m CONFIG_VIDEO_IMX208=m CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX319=m CONFIG_VIDEO_IMX334=m CONFIG_VIDEO_IMX335=m CONFIG_VIDEO_IMX355=m CONFIG_VIDEO_IMX412=m CONFIG_VIDEO_MAX9271_LIB=m CONFIG_VIDEO_MT9M001=m CONFIG_VIDEO_MT9M032=m CONFIG_VIDEO_MT9M111=m CONFIG_VIDEO_MT9P031=m CONFIG_VIDEO_MT9T001=m CONFIG_VIDEO_MT9T112=m CONFIG_VIDEO_MT9V011=m CONFIG_VIDEO_MT9V032=m CONFIG_VIDEO_MT9V111=m CONFIG_VIDEO_NOON010PC30=m CONFIG_VIDEO_OG01A1B=m CONFIG_VIDEO_OV02A10=m CONFIG_VIDEO_OV08D10=m CONFIG_VIDEO_OV08X40=m CONFIG_VIDEO_OV13858=m CONFIG_VIDEO_OV13B10=m CONFIG_VIDEO_OV2640=m CONFIG_VIDEO_OV2659=m CONFIG_VIDEO_OV2680=m CONFIG_VIDEO_OV2685=m CONFIG_VIDEO_OV2740=m CONFIG_VIDEO_OV4689=m CONFIG_VIDEO_OV5640=m CONFIG_VIDEO_OV5645=m CONFIG_VIDEO_OV5647=m CONFIG_VIDEO_OV5648=m CONFIG_VIDEO_OV5670=m CONFIG_VIDEO_OV5675=m CONFIG_VIDEO_OV5693=m CONFIG_VIDEO_OV5695=m CONFIG_VIDEO_OV6650=m CONFIG_VIDEO_OV7251=m CONFIG_VIDEO_OV7640=m CONFIG_VIDEO_OV7670=m CONFIG_VIDEO_OV772X=m CONFIG_VIDEO_OV7740=m CONFIG_VIDEO_OV8856=m CONFIG_VIDEO_OV8865=m CONFIG_VIDEO_OV9282=m CONFIG_VIDEO_OV9640=m CONFIG_VIDEO_OV9650=m CONFIG_VIDEO_OV9734=m CONFIG_VIDEO_RDACM20=m CONFIG_VIDEO_RDACM21=m CONFIG_VIDEO_RJ54N1=m CONFIG_VIDEO_S5C73M3=m CONFIG_VIDEO_S5K4ECGX=m CONFIG_VIDEO_S5K5BAF=m CONFIG_VIDEO_S5K6A3=m CONFIG_VIDEO_S5K6AA=m CONFIG_VIDEO_SR030PC30=m CONFIG_VIDEO_ST_VGXY61=m CONFIG_VIDEO_VS6624=m CONFIG_VIDEO_CCS=m CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_M5MOLS=m # end of Camera sensor devices # # Lens drivers # CONFIG_VIDEO_AD5820=m CONFIG_VIDEO_AK7375=m CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m # end of Lens drivers # # Flash devices # CONFIG_VIDEO_ADP1653=m CONFIG_VIDEO_LM3560=m CONFIG_VIDEO_LM3646=m # end of Flash devices # # Audio decoders, processors and mixers # CONFIG_VIDEO_CS3308=m CONFIG_VIDEO_CS5345=m CONFIG_VIDEO_CS53L32A=m CONFIG_VIDEO_MSP3400=m CONFIG_VIDEO_SONY_BTF_MPX=m CONFIG_VIDEO_TDA7432=m CONFIG_VIDEO_TDA9840=m CONFIG_VIDEO_TEA6415C=m CONFIG_VIDEO_TEA6420=m CONFIG_VIDEO_TLV320AIC23B=m CONFIG_VIDEO_TVAUDIO=m CONFIG_VIDEO_UDA1342=m CONFIG_VIDEO_VP27SMPX=m CONFIG_VIDEO_WM8739=m CONFIG_VIDEO_WM8775=m # end of Audio decoders, processors and mixers # # RDS decoders # CONFIG_VIDEO_SAA6588=m # end of RDS decoders # # Video decoders # CONFIG_VIDEO_ADV7180=m CONFIG_VIDEO_ADV7183=m CONFIG_VIDEO_ADV748X=m CONFIG_VIDEO_ADV7604=m CONFIG_VIDEO_ADV7604_CEC=y CONFIG_VIDEO_ADV7842=m CONFIG_VIDEO_ADV7842_CEC=y CONFIG_VIDEO_BT819=m CONFIG_VIDEO_BT856=m CONFIG_VIDEO_BT866=m CONFIG_VIDEO_ISL7998X=m CONFIG_VIDEO_KS0127=m CONFIG_VIDEO_MAX9286=m CONFIG_VIDEO_ML86V7667=m CONFIG_VIDEO_SAA7110=m CONFIG_VIDEO_SAA711X=m CONFIG_VIDEO_TC358743=m CONFIG_VIDEO_TC358743_CEC=y CONFIG_VIDEO_TC358746=m CONFIG_VIDEO_TVP514X=m CONFIG_VIDEO_TVP5150=m CONFIG_VIDEO_TVP7002=m CONFIG_VIDEO_TW2804=m CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m CONFIG_VIDEO_TW9910=m CONFIG_VIDEO_VPX3220=m # # Video and audio decoders # CONFIG_VIDEO_SAA717X=m CONFIG_VIDEO_CX25840=m # end of Video decoders # # Video encoders # CONFIG_VIDEO_AD9389B=m CONFIG_VIDEO_ADV7170=m CONFIG_VIDEO_ADV7175=m CONFIG_VIDEO_ADV7343=m CONFIG_VIDEO_ADV7393=m CONFIG_VIDEO_ADV7511=m CONFIG_VIDEO_ADV7511_CEC=y CONFIG_VIDEO_AK881X=m CONFIG_VIDEO_SAA7127=m CONFIG_VIDEO_SAA7185=m CONFIG_VIDEO_THS8200=m # end of Video encoders # # Video improvement chips # CONFIG_VIDEO_UPD64031A=m CONFIG_VIDEO_UPD64083=m # end of Video improvement chips # # Audio/Video compression chips # CONFIG_VIDEO_SAA6752HS=m # end of Audio/Video compression chips # # SDR tuner chips # CONFIG_SDR_MAX2175=m # end of SDR tuner chips # # Miscellaneous helper chips # CONFIG_VIDEO_I2C=m CONFIG_VIDEO_M52790=m CONFIG_VIDEO_ST_MIPID02=m CONFIG_VIDEO_THS7303=m # end of Miscellaneous helper chips # # Media SPI Adapters # CONFIG_CXD2880_SPI_DRV=m CONFIG_VIDEO_GS1662=m # end of Media SPI Adapters CONFIG_MEDIA_TUNER=m # # Customize TV tuners # CONFIG_MEDIA_TUNER_E4000=m CONFIG_MEDIA_TUNER_FC0011=m CONFIG_MEDIA_TUNER_FC0012=m CONFIG_MEDIA_TUNER_FC0013=m CONFIG_MEDIA_TUNER_FC2580=m CONFIG_MEDIA_TUNER_IT913X=m CONFIG_MEDIA_TUNER_M88RS6000T=m CONFIG_MEDIA_TUNER_MAX2165=m CONFIG_MEDIA_TUNER_MC44S803=m CONFIG_MEDIA_TUNER_MSI001=m CONFIG_MEDIA_TUNER_MT2060=m CONFIG_MEDIA_TUNER_MT2063=m CONFIG_MEDIA_TUNER_MT20XX=m CONFIG_MEDIA_TUNER_MT2131=m CONFIG_MEDIA_TUNER_MT2266=m CONFIG_MEDIA_TUNER_MXL301RF=m CONFIG_MEDIA_TUNER_MXL5005S=m CONFIG_MEDIA_TUNER_MXL5007T=m CONFIG_MEDIA_TUNER_QM1D1B0004=m CONFIG_MEDIA_TUNER_QM1D1C0042=m CONFIG_MEDIA_TUNER_QT1010=m CONFIG_MEDIA_TUNER_R820T=m CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_TUNER_SIMPLE=m CONFIG_MEDIA_TUNER_TDA18212=m CONFIG_MEDIA_TUNER_TDA18218=m CONFIG_MEDIA_TUNER_TDA18250=m CONFIG_MEDIA_TUNER_TDA18271=m CONFIG_MEDIA_TUNER_TDA827X=m CONFIG_MEDIA_TUNER_TDA8290=m CONFIG_MEDIA_TUNER_TDA9887=m CONFIG_MEDIA_TUNER_TEA5761=m CONFIG_MEDIA_TUNER_TEA5767=m CONFIG_MEDIA_TUNER_TUA9001=m CONFIG_MEDIA_TUNER_XC2028=m CONFIG_MEDIA_TUNER_XC4000=m CONFIG_MEDIA_TUNER_XC5000=m # end of Customize TV tuners # # Customise DVB Frontends # # # Multistandard (satellite) frontends # CONFIG_DVB_M88DS3103=m CONFIG_DVB_MXL5XX=m CONFIG_DVB_STB0899=m CONFIG_DVB_STB6100=m CONFIG_DVB_STV090x=m CONFIG_DVB_STV0910=m CONFIG_DVB_STV6110x=m CONFIG_DVB_STV6111=m # # Multistandard (cable + terrestrial) frontends # CONFIG_DVB_DRXK=m CONFIG_DVB_MN88472=m CONFIG_DVB_MN88473=m CONFIG_DVB_SI2165=m CONFIG_DVB_TDA18271C2DD=m # # DVB-S (satellite) frontends # CONFIG_DVB_CX24110=m CONFIG_DVB_CX24116=m CONFIG_DVB_CX24117=m CONFIG_DVB_CX24120=m CONFIG_DVB_CX24123=m CONFIG_DVB_DS3000=m CONFIG_DVB_MB86A16=m CONFIG_DVB_MT312=m CONFIG_DVB_S5H1420=m CONFIG_DVB_SI21XX=m CONFIG_DVB_STB6000=m CONFIG_DVB_STV0288=m CONFIG_DVB_STV0299=m CONFIG_DVB_STV0900=m CONFIG_DVB_STV6110=m CONFIG_DVB_TDA10071=m CONFIG_DVB_TDA10086=m CONFIG_DVB_TDA8083=m CONFIG_DVB_TDA8261=m CONFIG_DVB_TDA826X=m CONFIG_DVB_TS2020=m CONFIG_DVB_TUA6100=m CONFIG_DVB_TUNER_CX24113=m CONFIG_DVB_TUNER_ITD1000=m CONFIG_DVB_VES1X93=m CONFIG_DVB_ZL10036=m CONFIG_DVB_ZL10039=m # # DVB-T (terrestrial) frontends # CONFIG_DVB_AF9013=m CONFIG_DVB_AS102_FE=m CONFIG_DVB_CX22700=m CONFIG_DVB_CX22702=m CONFIG_DVB_CXD2820R=m CONFIG_DVB_CXD2841ER=m CONFIG_DVB_DIB3000MB=m CONFIG_DVB_DIB3000MC=m CONFIG_DVB_DIB7000M=m CONFIG_DVB_DIB7000P=m CONFIG_DVB_DIB9000=m CONFIG_DVB_DRXD=m CONFIG_DVB_EC100=m CONFIG_DVB_GP8PSK_FE=m CONFIG_DVB_L64781=m CONFIG_DVB_MT352=m CONFIG_DVB_NXT6000=m CONFIG_DVB_RTL2830=m CONFIG_DVB_RTL2832=m CONFIG_DVB_RTL2832_SDR=m CONFIG_DVB_S5H1432=m CONFIG_DVB_SI2168=m CONFIG_DVB_SP887X=m CONFIG_DVB_STV0367=m CONFIG_DVB_TDA10048=m CONFIG_DVB_TDA1004X=m CONFIG_DVB_ZD1301_DEMOD=m CONFIG_DVB_ZL10353=m CONFIG_DVB_CXD2880=m # # DVB-C (cable) frontends # CONFIG_DVB_STV0297=m CONFIG_DVB_TDA10021=m CONFIG_DVB_TDA10023=m CONFIG_DVB_VES1820=m # # ATSC (North American/Korean Terrestrial/Cable DTV) frontends # CONFIG_DVB_AU8522=m CONFIG_DVB_AU8522_DTV=m CONFIG_DVB_AU8522_V4L=m CONFIG_DVB_BCM3510=m CONFIG_DVB_LG2160=m CONFIG_DVB_LGDT3305=m CONFIG_DVB_LGDT3306A=m CONFIG_DVB_LGDT330X=m CONFIG_DVB_MXL692=m CONFIG_DVB_NXT200X=m CONFIG_DVB_OR51132=m CONFIG_DVB_OR51211=m CONFIG_DVB_S5H1409=m CONFIG_DVB_S5H1411=m # # ISDB-T (terrestrial) frontends # CONFIG_DVB_DIB8000=m CONFIG_DVB_MB86A20S=m CONFIG_DVB_S921=m # # ISDB-S (satellite) & ISDB-T (terrestrial) frontends # CONFIG_DVB_MN88443X=m CONFIG_DVB_TC90522=m # # Digital terrestrial only tuners/PLL # CONFIG_DVB_PLL=m CONFIG_DVB_TUNER_DIB0070=m CONFIG_DVB_TUNER_DIB0090=m # # SEC control devices for DVB-S # CONFIG_DVB_A8293=m CONFIG_DVB_AF9033=m CONFIG_DVB_ASCOT2E=m CONFIG_DVB_ATBM8830=m CONFIG_DVB_HELENE=m CONFIG_DVB_HORUS3A=m CONFIG_DVB_ISL6405=m CONFIG_DVB_ISL6421=m CONFIG_DVB_ISL6423=m CONFIG_DVB_IX2505V=m CONFIG_DVB_LGS8GL5=m CONFIG_DVB_LGS8GXX=m CONFIG_DVB_LNBH25=m CONFIG_DVB_LNBH29=m CONFIG_DVB_LNBP21=m CONFIG_DVB_LNBP22=m CONFIG_DVB_M88RS2000=m CONFIG_DVB_TDA665x=m CONFIG_DVB_DRX39XYJ=m # # Common Interface (EN50221) controller drivers # CONFIG_DVB_CXD2099=m CONFIG_DVB_SP2=m # end of Customise DVB Frontends # # Tools to develop new frontends # CONFIG_DVB_DUMMY_FE=m # end of Media ancillary drivers # # Graphics support # CONFIG_APERTURE_HELPERS=y CONFIG_AGP=m CONFIG_AGP_I460=m CONFIG_AGP_HP_ZX1=m CONFIG_IMX_IPUV3_CORE=m CONFIG_DRM=m CONFIG_DRM_MIPI_DBI=m CONFIG_DRM_MIPI_DSI=y CONFIG_DRM_KUNIT_TEST=m CONFIG_DRM_KMS_HELPER=m CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS=y CONFIG_DRM_DEBUG_MODESET_LOCK=y CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM=y CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_DP_AUX_BUS=m CONFIG_DRM_DISPLAY_HELPER=m CONFIG_DRM_DISPLAY_DP_HELPER=y CONFIG_DRM_DISPLAY_HDCP_HELPER=y CONFIG_DRM_DISPLAY_HDMI_HELPER=y CONFIG_DRM_DP_AUX_CHARDEV=y CONFIG_DRM_DP_CEC=y CONFIG_DRM_TTM=m CONFIG_DRM_BUDDY=m CONFIG_DRM_VRAM_HELPER=m CONFIG_DRM_TTM_HELPER=m CONFIG_DRM_GEM_DMA_HELPER=m CONFIG_DRM_GEM_SHMEM_HELPER=m CONFIG_DRM_SCHED=m # # I2C encoder or helper chips # CONFIG_DRM_I2C_CH7006=m CONFIG_DRM_I2C_SIL164=m CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_I2C_NXP_TDA9950=m # end of I2C encoder or helper chips # # ARM devices # CONFIG_DRM_HDLCD=m CONFIG_DRM_HDLCD_SHOW_UNDERRUN=y CONFIG_DRM_MALI_DISPLAY=m CONFIG_DRM_KOMEDA=m # end of ARM devices CONFIG_DRM_RADEON=m CONFIG_DRM_RADEON_USERPTR=y CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y CONFIG_DRM_AMDGPU_USERPTR=y # # ACP (Audio CoProcessor) Configuration # CONFIG_DRM_AMD_ACP=y # end of ACP (Audio CoProcessor) Configuration # # Display Engine Configuration # CONFIG_DRM_AMD_DC=y CONFIG_DRM_AMD_DC_HDCP=y CONFIG_DRM_AMD_DC_SI=y # end of Display Engine Configuration # CONFIG_DRM_NOUVEAU is not set CONFIG_DRM_KMB_DISPLAY=m CONFIG_DRM_VGEM=m CONFIG_DRM_VKMS=m CONFIG_DRM_EXYNOS=m # # CRTCs # CONFIG_DRM_EXYNOS_FIMD=y CONFIG_DRM_EXYNOS5433_DECON=y CONFIG_DRM_EXYNOS7_DECON=y CONFIG_DRM_EXYNOS_MIXER=y CONFIG_DRM_EXYNOS_VIDI=y # # Encoders and Bridges # CONFIG_DRM_EXYNOS_DPI=y CONFIG_DRM_EXYNOS_DSI=y CONFIG_DRM_EXYNOS_DP=y CONFIG_DRM_EXYNOS_HDMI=y CONFIG_DRM_EXYNOS_MIC=y # # Sub-drivers # CONFIG_DRM_EXYNOS_G2D=y CONFIG_DRM_EXYNOS_IPP=y CONFIG_DRM_EXYNOS_FIMC=y CONFIG_DRM_EXYNOS_ROTATOR=y CONFIG_DRM_EXYNOS_SCALER=y CONFIG_DRM_EXYNOS_GSC=y CONFIG_DRM_ROCKCHIP=m CONFIG_ROCKCHIP_VOP=y CONFIG_ROCKCHIP_VOP2=y CONFIG_ROCKCHIP_ANALOGIX_DP=y CONFIG_ROCKCHIP_CDN_DP=y CONFIG_ROCKCHIP_DW_HDMI=y CONFIG_ROCKCHIP_DW_MIPI_DSI=y CONFIG_ROCKCHIP_INNO_HDMI=y CONFIG_ROCKCHIP_LVDS=y CONFIG_ROCKCHIP_RGB=y CONFIG_ROCKCHIP_RK3066_HDMI=y CONFIG_DRM_UDL=m CONFIG_DRM_AST=m CONFIG_DRM_MGAG200=m CONFIG_DRM_RCAR_DW_HDMI=m CONFIG_DRM_RCAR_USE_LVDS=y # CONFIG_DRM_RCAR_MIPI_DSI is not set CONFIG_DRM_SUN4I=m CONFIG_DRM_SUN4I_HDMI=m CONFIG_DRM_SUN4I_HDMI_CEC=y CONFIG_DRM_SUN4I_BACKEND=m CONFIG_DRM_SUN6I_DSI=m CONFIG_DRM_SUN8I_DW_HDMI=m CONFIG_DRM_SUN8I_MIXER=m CONFIG_DRM_SUN8I_TCON_TOP=m CONFIG_DRM_QXL=m CONFIG_DRM_VIRTIO_GPU=m CONFIG_DRM_MSM=m CONFIG_DRM_MSM_GPU_STATE=y CONFIG_DRM_MSM_GPU_SUDO=y CONFIG_DRM_MSM_MDSS=y CONFIG_DRM_MSM_MDP4=y CONFIG_DRM_MSM_MDP5=y CONFIG_DRM_MSM_DPU=y CONFIG_DRM_MSM_DP=y CONFIG_DRM_MSM_DSI=y CONFIG_DRM_MSM_DSI_28NM_PHY=y CONFIG_DRM_MSM_DSI_20NM_PHY=y CONFIG_DRM_MSM_DSI_28NM_8960_PHY=y CONFIG_DRM_MSM_DSI_14NM_PHY=y CONFIG_DRM_MSM_DSI_10NM_PHY=y CONFIG_DRM_MSM_DSI_7NM_PHY=y CONFIG_DRM_MSM_HDMI=y CONFIG_DRM_MSM_HDMI_HDCP=y CONFIG_DRM_PANEL=y # # Display Panels # CONFIG_DRM_PANEL_ABT_Y030XX067A=m CONFIG_DRM_PANEL_ARM_VERSATILE=m CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m CONFIG_DRM_PANEL_BOE_HIMAX8279D=m CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m CONFIG_DRM_PANEL_DSI_CM=m CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_EDP=m CONFIG_DRM_PANEL_EBBG_FT8719=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m CONFIG_DRM_PANEL_ILITEK_IL9322=m CONFIG_DRM_PANEL_ILITEK_ILI9341=m CONFIG_DRM_PANEL_ILITEK_ILI9881C=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m CONFIG_DRM_PANEL_JDI_LT070ME05000=m CONFIG_DRM_PANEL_JDI_R63452=m CONFIG_DRM_PANEL_KHADAS_TS050=m CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m CONFIG_DRM_PANEL_SAMSUNG_LD9040=m CONFIG_DRM_PANEL_LG_LB035Q02=m CONFIG_DRM_PANEL_LG_LG4573=m CONFIG_DRM_PANEL_NEC_NL8048HL11=m CONFIG_DRM_PANEL_NEWVISION_NV3052C=m CONFIG_DRM_PANEL_NOVATEK_NT35510=m CONFIG_DRM_PANEL_NOVATEK_NT35560=m CONFIG_DRM_PANEL_NOVATEK_NT35950=m CONFIG_DRM_PANEL_NOVATEK_NT36672A=m CONFIG_DRM_PANEL_NOVATEK_NT39016=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m CONFIG_DRM_PANEL_RAYDIUM_RM67191=m CONFIG_DRM_PANEL_RAYDIUM_RM68200=m CONFIG_DRM_PANEL_RONBO_RB070D30=m CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m CONFIG_DRM_PANEL_SAMSUNG_DB7430=m CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m CONFIG_DRM_PANEL_SEIKO_43WVF1G=m CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m CONFIG_DRM_PANEL_SITRONIX_ST7701=m CONFIG_DRM_PANEL_SITRONIX_ST7703=m CONFIG_DRM_PANEL_SITRONIX_ST7789V=m CONFIG_DRM_PANEL_SONY_ACX565AKM=m CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m CONFIG_DRM_PANEL_TDO_TL070WSH30=m CONFIG_DRM_PANEL_TPO_TD028TTEC1=m CONFIG_DRM_PANEL_TPO_TD043MTEA1=m CONFIG_DRM_PANEL_TPO_TPG110=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m CONFIG_DRM_PANEL_VISIONOX_RM69299=m CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m CONFIG_DRM_PANEL_XINPENG_XPP055C272=m # end of Display Panels CONFIG_DRM_BRIDGE=y CONFIG_DRM_PANEL_BRIDGE=y # # Display Interface Bridges # CONFIG_DRM_CDNS_DSI=m CONFIG_DRM_CHIPONE_ICN6211=m CONFIG_DRM_CHRONTEL_CH7033=m CONFIG_DRM_CROS_EC_ANX7688=m CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_FSL_LDB=m CONFIG_DRM_ITE_IT6505=m CONFIG_DRM_LONTIUM_LT8912B=m CONFIG_DRM_LONTIUM_LT9211=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LONTIUM_LT9611UXC=m CONFIG_DRM_ITE_IT66121=m CONFIG_DRM_LVDS_CODEC=m CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m CONFIG_DRM_NWL_MIPI_DSI=m CONFIG_DRM_NXP_PTN3460=m CONFIG_DRM_PARADE_PS8622=m CONFIG_DRM_PARADE_PS8640=m CONFIG_DRM_SIL_SII8620=m CONFIG_DRM_SII902X=m CONFIG_DRM_SII9234=m CONFIG_DRM_SIMPLE_BRIDGE=m CONFIG_DRM_THINE_THC63LVD1024=m CONFIG_DRM_TOSHIBA_TC358762=m CONFIG_DRM_TOSHIBA_TC358764=m CONFIG_DRM_TOSHIBA_TC358767=m CONFIG_DRM_TOSHIBA_TC358768=m CONFIG_DRM_TOSHIBA_TC358775=m CONFIG_DRM_TI_DLPC3433=m CONFIG_DRM_TI_TFP410=m CONFIG_DRM_TI_SN65DSI83=m CONFIG_DRM_TI_SN65DSI86=m CONFIG_DRM_TI_TPD12S015=m CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX78XX=m CONFIG_DRM_ANALOGIX_DP=m CONFIG_DRM_ANALOGIX_ANX7625=m CONFIG_DRM_I2C_ADV7511=m CONFIG_DRM_I2C_ADV7511_CEC=y CONFIG_DRM_CDNS_MHDP8546=m CONFIG_DRM_CDNS_MHDP8546_J721E=y CONFIG_DRM_IMX8QM_LDB=m CONFIG_DRM_IMX8QXP_LDB=m CONFIG_DRM_IMX8QXP_PIXEL_COMBINER=m CONFIG_DRM_IMX8QXP_PIXEL_LINK=m CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI=m CONFIG_DRM_DW_HDMI=m CONFIG_DRM_DW_HDMI_CEC=m CONFIG_DRM_DW_MIPI_DSI=m # end of Display Interface Bridges CONFIG_DRM_IMX=m CONFIG_DRM_IMX_PARALLEL_DISPLAY=m CONFIG_DRM_IMX_TVE=m CONFIG_DRM_IMX_LDB=m CONFIG_DRM_IMX_HDMI=m CONFIG_DRM_INGENIC=m CONFIG_DRM_INGENIC_IPU=y CONFIG_DRM_V3D=m CONFIG_DRM_ETNAVIV=m CONFIG_DRM_ETNAVIV_THERMAL=y CONFIG_DRM_HISI_HIBMC=m CONFIG_DRM_LOGICVC=m CONFIG_DRM_MXS=y CONFIG_DRM_MXSFB=m CONFIG_DRM_IMX_LCDIF=m CONFIG_DRM_ARCPGU=m CONFIG_DRM_BOCHS=m CONFIG_DRM_CIRRUS_QEMU=m CONFIG_DRM_GM12U320=m CONFIG_DRM_PANEL_MIPI_DBI=m CONFIG_DRM_SIMPLEDRM=m CONFIG_TINYDRM_HX8357D=m CONFIG_TINYDRM_ILI9163=m CONFIG_TINYDRM_ILI9225=m CONFIG_TINYDRM_ILI9341=m CONFIG_TINYDRM_ILI9486=m CONFIG_TINYDRM_MI0283QT=m CONFIG_TINYDRM_REPAPER=m CONFIG_TINYDRM_ST7586=m CONFIG_TINYDRM_ST7735R=m CONFIG_DRM_PL111=m CONFIG_DRM_TVE200=m CONFIG_DRM_LIMA=m CONFIG_DRM_PANFROST=m CONFIG_DRM_ASPEED_GFX=m CONFIG_DRM_MCDE=m CONFIG_DRM_TIDSS=m CONFIG_DRM_ZYNQMP_DPSUB=m CONFIG_DRM_GUD=m CONFIG_DRM_SSD130X=m CONFIG_DRM_SSD130X_I2C=m CONFIG_DRM_SSD130X_SPI=m CONFIG_DRM_SPRD=m CONFIG_DRM_LEGACY=y CONFIG_DRM_TDFX=m CONFIG_DRM_R128=m CONFIG_DRM_MGA=m CONFIG_DRM_SIS=m CONFIG_DRM_VIA=m CONFIG_DRM_SAVAGE=m CONFIG_DRM_EXPORT_FOR_TESTS=y CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m CONFIG_DRM_NOMODESET=y CONFIG_DRM_LIB_RANDOM=y CONFIG_DRM_PRIVACY_SCREEN=y # # Frame buffer Devices # CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y CONFIG_FB=m CONFIG_FIRMWARE_EDID=y CONFIG_FB_DDC=m CONFIG_FB_CFB_FILLRECT=m CONFIG_FB_CFB_COPYAREA=m CONFIG_FB_CFB_IMAGEBLIT=m CONFIG_FB_CFB_REV_PIXELS_IN_BYTE=y CONFIG_FB_SYS_FILLRECT=m CONFIG_FB_SYS_COPYAREA=m CONFIG_FB_SYS_IMAGEBLIT=m CONFIG_FB_FOREIGN_ENDIAN=y CONFIG_FB_BOTH_ENDIAN=y # CONFIG_FB_BIG_ENDIAN is not set # CONFIG_FB_LITTLE_ENDIAN is not set CONFIG_FB_SYS_FOPS=m CONFIG_FB_DEFERRED_IO=y CONFIG_FB_SVGALIB=m CONFIG_FB_BACKLIGHT=m CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y # # Frame buffer hardware drivers # CONFIG_FB_CIRRUS=m CONFIG_FB_PM2=m CONFIG_FB_PM2_FIFO_DISCONNECT=y CONFIG_FB_CLPS711X=m CONFIG_FB_IMX=m CONFIG_FB_CYBER2000=m CONFIG_FB_CYBER2000_DDC=y CONFIG_FB_ARC=m CONFIG_FB_UVESA=m CONFIG_FB_PVR2=m CONFIG_FB_OPENCORES=m CONFIG_FB_S1D13XXX=m CONFIG_FB_ATMEL=m CONFIG_FB_NVIDIA=m CONFIG_FB_NVIDIA_I2C=y CONFIG_FB_NVIDIA_DEBUG=y CONFIG_FB_NVIDIA_BACKLIGHT=y CONFIG_FB_RIVA=m CONFIG_FB_RIVA_I2C=y CONFIG_FB_RIVA_DEBUG=y CONFIG_FB_RIVA_BACKLIGHT=y CONFIG_FB_I740=m CONFIG_FB_MATROX=m CONFIG_FB_MATROX_MILLENIUM=y CONFIG_FB_MATROX_MYSTIQUE=y CONFIG_FB_MATROX_G=y CONFIG_FB_MATROX_I2C=m CONFIG_FB_MATROX_MAVEN=m CONFIG_FB_RADEON=m CONFIG_FB_RADEON_I2C=y CONFIG_FB_RADEON_BACKLIGHT=y CONFIG_FB_RADEON_DEBUG=y CONFIG_FB_ATY128=m CONFIG_FB_ATY128_BACKLIGHT=y CONFIG_FB_ATY=m CONFIG_FB_ATY_CT=y CONFIG_FB_ATY_GENERIC_LCD=y CONFIG_FB_ATY_GX=y CONFIG_FB_ATY_BACKLIGHT=y CONFIG_FB_S3=m CONFIG_FB_S3_DDC=y CONFIG_FB_SAVAGE=m CONFIG_FB_SAVAGE_I2C=y CONFIG_FB_SAVAGE_ACCEL=y CONFIG_FB_SIS=m CONFIG_FB_SIS_300=y CONFIG_FB_SIS_315=y CONFIG_FB_VIA=m CONFIG_FB_VIA_DIRECT_PROCFS=y CONFIG_FB_VIA_X_COMPATIBILITY=y CONFIG_FB_NEOMAGIC=m CONFIG_FB_KYRO=m CONFIG_FB_3DFX=m CONFIG_FB_3DFX_ACCEL=y CONFIG_FB_3DFX_I2C=y CONFIG_FB_VOODOO1=m CONFIG_FB_VT8623=m CONFIG_FB_TRIDENT=m CONFIG_FB_ARK=m CONFIG_FB_PM3=m CONFIG_FB_CARMINE=m CONFIG_FB_CARMINE_DRAM_EVAL=y # CONFIG_CARMINE_DRAM_CUSTOM is not set CONFIG_FB_PXA168=m CONFIG_FB_W100=m CONFIG_FB_SH_MOBILE_LCDC=m CONFIG_FB_TMIO=m CONFIG_FB_TMIO_ACCELL=y CONFIG_FB_S3C=m CONFIG_FB_S3C_DEBUG_REGWRITE=y CONFIG_FB_SM501=m CONFIG_FB_SMSCUFX=m CONFIG_FB_UDL=m CONFIG_FB_IBM_GXT4500=m CONFIG_FB_GOLDFISH=m CONFIG_FB_DA8XX=m CONFIG_FB_VIRTUAL=m CONFIG_FB_METRONOME=m CONFIG_FB_MB862XX=m CONFIG_FB_MB862XX_PCI_GDC=y CONFIG_FB_MB862XX_I2C=y CONFIG_FB_BROADSHEET=m CONFIG_FB_SIMPLE=m CONFIG_FB_SSD1307=m CONFIG_FB_SM712=m CONFIG_FB_OMAP2=m CONFIG_FB_OMAP2_DEBUG_SUPPORT=y CONFIG_FB_OMAP2_NUM_FBS=3 CONFIG_FB_OMAP2_DSS_INIT=y CONFIG_FB_OMAP2_DSS=m CONFIG_FB_OMAP2_DSS_DEBUG=y CONFIG_FB_OMAP2_DSS_DEBUGFS=y CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS=y CONFIG_FB_OMAP2_DSS_DPI=y CONFIG_FB_OMAP2_DSS_VENC=y CONFIG_FB_OMAP2_DSS_HDMI_COMMON=y CONFIG_FB_OMAP4_DSS_HDMI=y CONFIG_FB_OMAP5_DSS_HDMI=y CONFIG_FB_OMAP2_DSS_SDI=y CONFIG_FB_OMAP2_DSS_DSI=y CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK=0 CONFIG_FB_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y # # OMAPFB Panel and Encoder Drivers # CONFIG_FB_OMAP2_ENCODER_OPA362=m CONFIG_FB_OMAP2_ENCODER_TFP410=m CONFIG_FB_OMAP2_ENCODER_TPD12S015=m CONFIG_FB_OMAP2_CONNECTOR_DVI=m CONFIG_FB_OMAP2_CONNECTOR_HDMI=m CONFIG_FB_OMAP2_CONNECTOR_ANALOG_TV=m CONFIG_FB_OMAP2_PANEL_DPI=m CONFIG_FB_OMAP2_PANEL_LGPHILIPS_LB035Q02=m # end of OMAPFB Panel and Encoder Drivers CONFIG_MMP_DISP=m CONFIG_MMP_DISP_CONTROLLER=y CONFIG_MMP_DISP_SPI=y CONFIG_MMP_PANEL_TPOHVGA=y CONFIG_MMP_FB=m # end of Frame buffer Devices # # Backlight & LCD device support # CONFIG_LCD_CLASS_DEVICE=m CONFIG_LCD_L4F00242T03=m CONFIG_LCD_LMS283GF05=m CONFIG_LCD_LTV350QV=m CONFIG_LCD_ILI922X=m CONFIG_LCD_ILI9320=m CONFIG_LCD_TDO24M=m CONFIG_LCD_VGG2432A4=m CONFIG_LCD_PLATFORM=m CONFIG_LCD_AMS369FG06=m CONFIG_LCD_LMS501KF03=m CONFIG_LCD_HX8357=m CONFIG_LCD_OTM3225A=m CONFIG_BACKLIGHT_CLASS_DEVICE=m CONFIG_BACKLIGHT_ATMEL_LCDC=y CONFIG_BACKLIGHT_KTD253=m CONFIG_BACKLIGHT_LM3533=m CONFIG_BACKLIGHT_OMAP1=m CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_DA9052=m CONFIG_BACKLIGHT_MT6370=m CONFIG_BACKLIGHT_QCOM_WLED=m CONFIG_BACKLIGHT_RT4831=m CONFIG_BACKLIGHT_WM831X=m CONFIG_BACKLIGHT_ADP8860=m CONFIG_BACKLIGHT_ADP8870=m CONFIG_BACKLIGHT_PCF50633=m CONFIG_BACKLIGHT_LM3630A=m CONFIG_BACKLIGHT_LM3639=m CONFIG_BACKLIGHT_LP855X=m CONFIG_BACKLIGHT_SKY81452=m CONFIG_BACKLIGHT_TPS65217=m CONFIG_BACKLIGHT_GPIO=m CONFIG_BACKLIGHT_LV5207LP=m CONFIG_BACKLIGHT_BD6107=m CONFIG_BACKLIGHT_ARCXCNN=m CONFIG_BACKLIGHT_RAVE_SP=m CONFIG_BACKLIGHT_LED=m # end of Backlight & LCD device support CONFIG_VGASTATE=m CONFIG_VIDEOMODE_HELPERS=y CONFIG_HDMI=y # # Console display driver support # CONFIG_VGA_CONSOLE=y CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y # end of Console display driver support CONFIG_LOGO=y CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y # end of Graphics support # CONFIG_SOUND is not set # # HID support # CONFIG_HID=m CONFIG_HID_BATTERY_STRENGTH=y CONFIG_HIDRAW=y CONFIG_UHID=m CONFIG_HID_GENERIC=m # # Special HID drivers # CONFIG_HID_A4TECH=m CONFIG_HID_ACCUTOUCH=m CONFIG_HID_ACRUX=m CONFIG_HID_ACRUX_FF=y CONFIG_HID_APPLE=m CONFIG_HID_APPLEIR=m CONFIG_HID_ASUS=m CONFIG_HID_AUREAL=m CONFIG_HID_BELKIN=m CONFIG_HID_BETOP_FF=m CONFIG_HID_BIGBEN_FF=m CONFIG_HID_CHERRY=m CONFIG_HID_CHICONY=m CONFIG_HID_CORSAIR=m CONFIG_HID_COUGAR=m CONFIG_HID_MACALLY=m CONFIG_HID_CMEDIA=m CONFIG_HID_CP2112=m CONFIG_HID_CREATIVE_SB0540=m CONFIG_HID_CYPRESS=m CONFIG_HID_DRAGONRISE=m CONFIG_DRAGONRISE_FF=y CONFIG_HID_EMS_FF=m CONFIG_HID_ELAN=m CONFIG_HID_ELECOM=m CONFIG_HID_ELO=m CONFIG_HID_EZKEY=m CONFIG_HID_FT260=m CONFIG_HID_GEMBIRD=m CONFIG_HID_GFRM=m CONFIG_HID_GLORIOUS=m CONFIG_HID_HOLTEK=m CONFIG_HOLTEK_FF=y CONFIG_HID_VIVALDI_COMMON=m CONFIG_HID_GOOGLE_HAMMER=m CONFIG_HID_VIVALDI=m CONFIG_HID_GT683R=m CONFIG_HID_KEYTOUCH=m CONFIG_HID_KYE=m CONFIG_HID_UCLOGIC=m CONFIG_HID_WALTOP=m CONFIG_HID_VIEWSONIC=m CONFIG_HID_VRC2=m CONFIG_HID_XIAOMI=m CONFIG_HID_GYRATION=m CONFIG_HID_ICADE=m CONFIG_HID_ITE=m CONFIG_HID_JABRA=m CONFIG_HID_TWINHAN=m CONFIG_HID_KENSINGTON=m CONFIG_HID_LCPOWER=m CONFIG_HID_LED=m CONFIG_HID_LENOVO=m CONFIG_HID_LETSKETCH=m CONFIG_HID_LOGITECH=m CONFIG_HID_LOGITECH_DJ=m CONFIG_HID_LOGITECH_HIDPP=m CONFIG_LOGITECH_FF=y CONFIG_LOGIRUMBLEPAD2_FF=y CONFIG_LOGIG940_FF=y CONFIG_LOGIWHEELS_FF=y CONFIG_HID_MAGICMOUSE=m CONFIG_HID_MALTRON=m CONFIG_HID_MAYFLASH=m CONFIG_HID_MEGAWORLD_FF=m CONFIG_HID_REDRAGON=m CONFIG_HID_MICROSOFT=m CONFIG_HID_MONTEREY=m CONFIG_HID_MULTITOUCH=m CONFIG_HID_NINTENDO=m CONFIG_NINTENDO_FF=y CONFIG_HID_NTI=m CONFIG_HID_NTRIG=m CONFIG_HID_ORTEK=m CONFIG_HID_PANTHERLORD=m CONFIG_PANTHERLORD_FF=y CONFIG_HID_PENMOUNT=m CONFIG_HID_PETALYNX=m CONFIG_HID_PICOLCD=m CONFIG_HID_PICOLCD_FB=y CONFIG_HID_PICOLCD_BACKLIGHT=y CONFIG_HID_PICOLCD_LCD=y CONFIG_HID_PICOLCD_LEDS=y CONFIG_HID_PICOLCD_CIR=y CONFIG_HID_PLANTRONICS=m CONFIG_HID_PLAYSTATION=m CONFIG_PLAYSTATION_FF=y CONFIG_HID_PXRC=m CONFIG_HID_RAZER=m CONFIG_HID_PRIMAX=m CONFIG_HID_RETRODE=m CONFIG_HID_ROCCAT=m CONFIG_HID_SAITEK=m CONFIG_HID_SAMSUNG=m CONFIG_HID_SEMITEK=m CONFIG_HID_SIGMAMICRO=m CONFIG_HID_SONY=m CONFIG_SONY_FF=y CONFIG_HID_SPEEDLINK=m CONFIG_HID_STEAM=m CONFIG_HID_STEELSERIES=m CONFIG_HID_SUNPLUS=m CONFIG_HID_RMI=m CONFIG_HID_GREENASIA=m CONFIG_GREENASIA_FF=y CONFIG_HID_SMARTJOYPLUS=m CONFIG_SMARTJOYPLUS_FF=y CONFIG_HID_TIVO=m CONFIG_HID_TOPSEED=m CONFIG_HID_TOPRE=m CONFIG_HID_THINGM=m CONFIG_HID_THRUSTMASTER=m CONFIG_THRUSTMASTER_FF=y CONFIG_HID_UDRAW_PS3=m CONFIG_HID_U2FZERO=m CONFIG_HID_WACOM=m CONFIG_HID_WIIMOTE=m CONFIG_HID_XINMO=m CONFIG_HID_ZEROPLUS=m CONFIG_ZEROPLUS_FF=y CONFIG_HID_ZYDACRON=m CONFIG_HID_SENSOR_HUB=m CONFIG_HID_SENSOR_CUSTOM_SENSOR=m CONFIG_HID_ALPS=m CONFIG_HID_MCP2221=m # end of Special HID drivers # # USB HID support # CONFIG_USB_HID=m CONFIG_HID_PID=y CONFIG_USB_HIDDEV=y # # USB HID Boot Protocol drivers # CONFIG_USB_KBD=m CONFIG_USB_MOUSE=m # end of USB HID Boot Protocol drivers # end of USB HID support # # I2C HID support # CONFIG_I2C_HID_ACPI=m CONFIG_I2C_HID_OF=m CONFIG_I2C_HID_OF_ELAN=m CONFIG_I2C_HID_OF_GOODIX=m # end of I2C HID support CONFIG_I2C_HID_CORE=m # # Intel ISH HID support # # end of Intel ISH HID support # # AMD SFH HID Support # CONFIG_AMD_SFH_HID=m # end of AMD SFH HID Support # # Surface System Aggregator Module HID support # CONFIG_SURFACE_HID=m CONFIG_SURFACE_KBD=m # end of Surface System Aggregator Module HID support CONFIG_SURFACE_HID_CORE=m # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=m CONFIG_USB_LED_TRIG=y CONFIG_USB_ULPI_BUS=m CONFIG_USB_CONN_GPIO=m CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=m CONFIG_USB_PCI=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # # Miscellaneous USB options # CONFIG_USB_DEFAULT_PERSIST=y CONFIG_USB_FEW_INIT_RETRIES=y CONFIG_USB_DYNAMIC_MINORS=y CONFIG_USB_OTG=y CONFIG_USB_OTG_PRODUCTLIST=y CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB=y CONFIG_USB_OTG_FSM=m CONFIG_USB_LEDS_TRIGGER_USBPORT=m CONFIG_USB_AUTOSUSPEND_DELAY=2 CONFIG_USB_MON=m # # USB Host Controller Drivers # CONFIG_USB_C67X00_HCD=m CONFIG_USB_XHCI_HCD=m CONFIG_USB_XHCI_DBGCAP=y CONFIG_USB_XHCI_PCI=m CONFIG_USB_XHCI_PCI_RENESAS=m CONFIG_USB_XHCI_PLATFORM=m CONFIG_USB_XHCI_HISTB=m CONFIG_USB_XHCI_MTK=m CONFIG_USB_XHCI_MVEBU=m CONFIG_USB_XHCI_RCAR=m CONFIG_USB_EHCI_BRCMSTB=m CONFIG_USB_BRCMSTB=m CONFIG_USB_EHCI_HCD=m CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_TT_NEWSCHED=y CONFIG_USB_EHCI_PCI=m CONFIG_USB_EHCI_FSL=m CONFIG_USB_EHCI_HCD_NPCM7XX=m CONFIG_USB_EHCI_HCD_OMAP=m CONFIG_USB_EHCI_HCD_ORION=m CONFIG_USB_EHCI_HCD_SPEAR=m CONFIG_USB_EHCI_HCD_STI=m CONFIG_USB_EHCI_HCD_AT91=m CONFIG_USB_EHCI_SH=y CONFIG_USB_EHCI_EXYNOS=m CONFIG_USB_EHCI_MV=m CONFIG_USB_CNS3XXX_EHCI=y CONFIG_USB_EHCI_HCD_PLATFORM=m CONFIG_USB_OXU210HP_HCD=m CONFIG_USB_ISP116X_HCD=m CONFIG_USB_ISP1362_HCD=m CONFIG_USB_FOTG210_HCD=m CONFIG_USB_MAX3421_HCD=m CONFIG_USB_OHCI_HCD=m CONFIG_USB_OHCI_HCD_SPEAR=m CONFIG_USB_OHCI_HCD_STI=m CONFIG_USB_OHCI_HCD_S3C2410=m CONFIG_USB_OHCI_HCD_LPC32XX=m CONFIG_USB_OHCI_HCD_AT91=m CONFIG_USB_OHCI_HCD_OMAP3=m CONFIG_USB_OHCI_HCD_DAVINCI=m CONFIG_USB_OHCI_HCD_PCI=m CONFIG_USB_OHCI_HCD_SSB=y CONFIG_USB_OHCI_SH=y CONFIG_USB_OHCI_EXYNOS=m CONFIG_USB_CNS3XXX_OHCI=y CONFIG_USB_OHCI_HCD_PLATFORM=m CONFIG_USB_UHCI_HCD=m CONFIG_USB_U132_HCD=m CONFIG_USB_SL811_HCD=m CONFIG_USB_SL811_HCD_ISO=y CONFIG_USB_SL811_CS=m CONFIG_USB_R8A66597_HCD=m CONFIG_USB_RENESAS_USBHS_HCD=m CONFIG_USB_HCD_BCMA=m CONFIG_USB_HCD_SSB=m CONFIG_USB_HCD_TEST_MODE=y CONFIG_USB_RENESAS_USBHS=m # # USB Device Class drivers # CONFIG_USB_ACM=m CONFIG_USB_PRINTER=m CONFIG_USB_WDM=m CONFIG_USB_TMC=m # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # # also be needed; see USB_STORAGE Help for more info # CONFIG_USB_STORAGE=m CONFIG_USB_STORAGE_DEBUG=y CONFIG_USB_STORAGE_REALTEK=m CONFIG_REALTEK_AUTOPM=y CONFIG_USB_STORAGE_DATAFAB=m CONFIG_USB_STORAGE_FREECOM=m CONFIG_USB_STORAGE_ISD200=m CONFIG_USB_STORAGE_USBAT=m CONFIG_USB_STORAGE_SDDR09=m CONFIG_USB_STORAGE_SDDR55=m CONFIG_USB_STORAGE_JUMPSHOT=m CONFIG_USB_STORAGE_ALAUDA=m CONFIG_USB_STORAGE_ONETOUCH=m CONFIG_USB_STORAGE_KARMA=m CONFIG_USB_STORAGE_CYPRESS_ATACB=m CONFIG_USB_STORAGE_ENE_UB6250=m CONFIG_USB_UAS=m # # USB Imaging devices # CONFIG_USB_MDC800=m CONFIG_USB_MICROTEK=m CONFIG_USBIP_CORE=m CONFIG_USBIP_VHCI_HCD=m CONFIG_USBIP_VHCI_HC_PORTS=8 CONFIG_USBIP_VHCI_NR_HCS=1 CONFIG_USBIP_HOST=m CONFIG_USBIP_VUDC=m CONFIG_USBIP_DEBUG=y CONFIG_USB_CDNS_SUPPORT=m CONFIG_USB_CDNS_HOST=y CONFIG_USB_CDNS3=m CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y CONFIG_USB_CDNS3_PCI_WRAP=m CONFIG_USB_CDNS3_TI=m CONFIG_USB_CDNS3_IMX=m CONFIG_USB_CDNSP_PCI=m CONFIG_USB_CDNSP_GADGET=y CONFIG_USB_CDNSP_HOST=y CONFIG_USB_MTU3=m # CONFIG_USB_MTU3_HOST is not set # CONFIG_USB_MTU3_GADGET is not set CONFIG_USB_MTU3_DUAL_ROLE=y CONFIG_USB_MTU3_DEBUG=y CONFIG_USB_MUSB_HDRC=m # CONFIG_USB_MUSB_HOST is not set # CONFIG_USB_MUSB_GADGET is not set CONFIG_USB_MUSB_DUAL_ROLE=y # # Platform Glue Layer # CONFIG_USB_MUSB_TUSB6010=m CONFIG_USB_MUSB_DSPS=m CONFIG_USB_MUSB_UX500=m CONFIG_USB_MUSB_MEDIATEK=m CONFIG_USB_MUSB_POLARFIRE_SOC=m # # MUSB DMA mode # CONFIG_MUSB_PIO_ONLY=y CONFIG_USB_DWC3=m CONFIG_USB_DWC3_ULPI=y # CONFIG_USB_DWC3_HOST is not set # CONFIG_USB_DWC3_GADGET is not set CONFIG_USB_DWC3_DUAL_ROLE=y # # Platform Glue Driver Support # CONFIG_USB_DWC3_OMAP=m CONFIG_USB_DWC3_EXYNOS=m CONFIG_USB_DWC3_PCI=m CONFIG_USB_DWC3_HAPS=m CONFIG_USB_DWC3_KEYSTONE=m CONFIG_USB_DWC3_MESON_G12A=m CONFIG_USB_DWC3_OF_SIMPLE=m CONFIG_USB_DWC3_ST=m CONFIG_USB_DWC3_QCOM=m CONFIG_USB_DWC3_IMX8MP=m CONFIG_USB_DWC3_AM62=m CONFIG_USB_DWC2=m # CONFIG_USB_DWC2_HOST is not set # # Gadget/Dual-role mode requires USB Gadget support to be enabled # # CONFIG_USB_DWC2_PERIPHERAL is not set CONFIG_USB_DWC2_DUAL_ROLE=y CONFIG_USB_DWC2_PCI=m CONFIG_USB_DWC2_DEBUG=y CONFIG_USB_DWC2_VERBOSE=y CONFIG_USB_DWC2_TRACK_MISSED_SOFS=y CONFIG_USB_DWC2_DEBUG_PERIODIC=y CONFIG_USB_CHIPIDEA=m CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_CHIPIDEA_PCI=m CONFIG_USB_CHIPIDEA_MSM=m CONFIG_USB_CHIPIDEA_IMX=m CONFIG_USB_CHIPIDEA_GENERIC=m CONFIG_USB_CHIPIDEA_TEGRA=m CONFIG_USB_ISP1760=m CONFIG_USB_ISP1760_HCD=y CONFIG_USB_ISP1761_UDC=y # CONFIG_USB_ISP1760_HOST_ROLE is not set # CONFIG_USB_ISP1760_GADGET_ROLE is not set CONFIG_USB_ISP1760_DUAL_ROLE=y # # USB port drivers # CONFIG_USB_USS720=m CONFIG_USB_SERIAL=m CONFIG_USB_SERIAL_GENERIC=y CONFIG_USB_SERIAL_SIMPLE=m CONFIG_USB_SERIAL_AIRCABLE=m CONFIG_USB_SERIAL_ARK3116=m CONFIG_USB_SERIAL_BELKIN=m CONFIG_USB_SERIAL_CH341=m CONFIG_USB_SERIAL_WHITEHEAT=m CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m CONFIG_USB_SERIAL_CP210X=m CONFIG_USB_SERIAL_CYPRESS_M8=m CONFIG_USB_SERIAL_EMPEG=m CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_VISOR=m CONFIG_USB_SERIAL_IPAQ=m CONFIG_USB_SERIAL_IR=m CONFIG_USB_SERIAL_EDGEPORT=m CONFIG_USB_SERIAL_EDGEPORT_TI=m CONFIG_USB_SERIAL_F81232=m CONFIG_USB_SERIAL_F8153X=m CONFIG_USB_SERIAL_GARMIN=m CONFIG_USB_SERIAL_IPW=m CONFIG_USB_SERIAL_IUU=m CONFIG_USB_SERIAL_KEYSPAN_PDA=m CONFIG_USB_SERIAL_KEYSPAN=m CONFIG_USB_SERIAL_KLSI=m CONFIG_USB_SERIAL_KOBIL_SCT=m CONFIG_USB_SERIAL_MCT_U232=m CONFIG_USB_SERIAL_METRO=m CONFIG_USB_SERIAL_MOS7720=m CONFIG_USB_SERIAL_MOS7715_PARPORT=y CONFIG_USB_SERIAL_MOS7840=m CONFIG_USB_SERIAL_MXUPORT=m CONFIG_USB_SERIAL_NAVMAN=m CONFIG_USB_SERIAL_PL2303=m CONFIG_USB_SERIAL_OTI6858=m CONFIG_USB_SERIAL_QCAUX=m CONFIG_USB_SERIAL_QUALCOMM=m CONFIG_USB_SERIAL_SPCP8X5=m CONFIG_USB_SERIAL_SAFE=m CONFIG_USB_SERIAL_SAFE_PADDED=y CONFIG_USB_SERIAL_SIERRAWIRELESS=m CONFIG_USB_SERIAL_SYMBOL=m CONFIG_USB_SERIAL_TI=m CONFIG_USB_SERIAL_CYBERJACK=m CONFIG_USB_SERIAL_WWAN=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_SERIAL_OPTICON=m CONFIG_USB_SERIAL_XSENS_MT=m CONFIG_USB_SERIAL_WISHBONE=m CONFIG_USB_SERIAL_SSU100=m CONFIG_USB_SERIAL_QT2=m CONFIG_USB_SERIAL_UPD78F0730=m CONFIG_USB_SERIAL_XR=m CONFIG_USB_SERIAL_DEBUG=m # # USB Miscellaneous drivers # CONFIG_USB_EMI62=m CONFIG_USB_EMI26=m CONFIG_USB_ADUTUX=m CONFIG_USB_SEVSEG=m CONFIG_USB_LEGOTOWER=m CONFIG_USB_LCD=m CONFIG_USB_CYPRESS_CY7C63=m CONFIG_USB_CYTHERM=m CONFIG_USB_IDMOUSE=m CONFIG_USB_FTDI_ELAN=m CONFIG_USB_APPLEDISPLAY=m CONFIG_USB_QCOM_EUD=m CONFIG_APPLE_MFI_FASTCHARGE=m CONFIG_USB_SISUSBVGA=m CONFIG_USB_LD=m CONFIG_USB_TRANCEVIBRATOR=m CONFIG_USB_IOWARRIOR=m CONFIG_USB_TEST=m CONFIG_USB_EHSET_TEST_FIXTURE=m CONFIG_USB_ISIGHTFW=m CONFIG_USB_YUREX=m CONFIG_USB_EZUSB_FX2=m CONFIG_USB_HUB_USB251XB=m CONFIG_USB_HSIC_USB3503=m CONFIG_USB_HSIC_USB4604=m CONFIG_USB_LINK_LAYER_TEST=m CONFIG_USB_CHAOSKEY=m CONFIG_BRCM_USB_PINMAP=m CONFIG_USB_ONBOARD_HUB=m CONFIG_USB_ATM=m CONFIG_USB_SPEEDTOUCH=m CONFIG_USB_CXACRU=m CONFIG_USB_UEAGLEATM=m CONFIG_USB_XUSBATM=m # # USB Physical Layer drivers # CONFIG_USB_PHY=y CONFIG_KEYSTONE_USB_PHY=m CONFIG_NOP_USB_XCEIV=m CONFIG_AM335X_CONTROL_USB=m CONFIG_AM335X_PHY_USB=m CONFIG_USB_GPIO_VBUS=m CONFIG_TAHVO_USB=m CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y CONFIG_USB_ISP1301=m CONFIG_USB_MV_OTG=m CONFIG_USB_TEGRA_PHY=m CONFIG_USB_ULPI=y CONFIG_USB_ULPI_VIEWPORT=y # CONFIG_JZ4770_PHY is not set # end of USB Physical Layer drivers CONFIG_USB_GADGET=m CONFIG_USB_GADGET_DEBUG=y CONFIG_USB_GADGET_VERBOSE=y CONFIG_USB_GADGET_DEBUG_FILES=y CONFIG_USB_GADGET_DEBUG_FS=y CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 CONFIG_U_SERIAL_CONSOLE=y # # USB Peripheral Controller # CONFIG_USB_LPC32XX=m CONFIG_USB_FOTG210_UDC=m CONFIG_USB_GR_UDC=m CONFIG_USB_R8A66597=m CONFIG_USB_RENESAS_USBHS_UDC=m CONFIG_USB_RENESAS_USB3=m CONFIG_USB_PXA27X=m CONFIG_USB_MV_UDC=m CONFIG_USB_MV_U3D=m CONFIG_USB_SNP_CORE=m CONFIG_USB_SNP_UDC_PLAT=m CONFIG_USB_M66592=m CONFIG_USB_BDC_UDC=m CONFIG_USB_AMD5536UDC=m CONFIG_USB_NET2272=m CONFIG_USB_NET2272_DMA=y CONFIG_USB_NET2280=m CONFIG_USB_GOKU=m CONFIG_USB_EG20T=m CONFIG_USB_GADGET_XILINX=m CONFIG_USB_MAX3420_UDC=m CONFIG_USB_ASPEED_UDC=m CONFIG_USB_ASPEED_VHUB=m CONFIG_USB_DUMMY_HCD=m # end of USB Peripheral Controller CONFIG_USB_LIBCOMPOSITE=m CONFIG_USB_F_ACM=m CONFIG_USB_F_SS_LB=m CONFIG_USB_U_SERIAL=m CONFIG_USB_U_ETHER=m CONFIG_USB_F_SERIAL=m CONFIG_USB_F_OBEX=m CONFIG_USB_F_NCM=m CONFIG_USB_F_ECM=m CONFIG_USB_F_PHONET=m CONFIG_USB_F_EEM=m CONFIG_USB_F_SUBSET=m CONFIG_USB_F_RNDIS=m CONFIG_USB_F_MASS_STORAGE=m CONFIG_USB_F_FS=m CONFIG_USB_F_UVC=m CONFIG_USB_F_HID=m CONFIG_USB_F_PRINTER=m CONFIG_USB_F_TCM=m CONFIG_USB_CONFIGFS=m CONFIG_USB_CONFIGFS_SERIAL=y CONFIG_USB_CONFIGFS_ACM=y CONFIG_USB_CONFIGFS_OBEX=y CONFIG_USB_CONFIGFS_NCM=y CONFIG_USB_CONFIGFS_ECM=y CONFIG_USB_CONFIGFS_ECM_SUBSET=y CONFIG_USB_CONFIGFS_RNDIS=y CONFIG_USB_CONFIGFS_EEM=y CONFIG_USB_CONFIGFS_PHONET=y CONFIG_USB_CONFIGFS_MASS_STORAGE=y CONFIG_USB_CONFIGFS_F_LB_SS=y CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_CONFIGFS_F_HID=y CONFIG_USB_CONFIGFS_F_UVC=y CONFIG_USB_CONFIGFS_F_PRINTER=y CONFIG_USB_CONFIGFS_F_TCM=y # # USB Gadget precomposed configurations # CONFIG_USB_ZERO=m CONFIG_USB_ZERO_HNPTEST=y CONFIG_USB_ETH=m CONFIG_USB_ETH_RNDIS=y CONFIG_USB_ETH_EEM=y CONFIG_USB_G_NCM=m CONFIG_USB_GADGETFS=m CONFIG_USB_FUNCTIONFS=m CONFIG_USB_FUNCTIONFS_ETH=y CONFIG_USB_FUNCTIONFS_RNDIS=y CONFIG_USB_FUNCTIONFS_GENERIC=y CONFIG_USB_MASS_STORAGE=m CONFIG_USB_GADGET_TARGET=m CONFIG_USB_G_SERIAL=m CONFIG_USB_G_PRINTER=m CONFIG_USB_CDC_COMPOSITE=m CONFIG_USB_G_NOKIA=m CONFIG_USB_G_ACM_MS=m CONFIG_USB_G_MULTI=m CONFIG_USB_G_MULTI_RNDIS=y CONFIG_USB_G_MULTI_CDC=y CONFIG_USB_G_HID=m CONFIG_USB_G_DBGP=m # CONFIG_USB_G_DBGP_PRINTK is not set CONFIG_USB_G_DBGP_SERIAL=y CONFIG_USB_G_WEBCAM=m CONFIG_USB_RAW_GADGET=m # end of USB Gadget precomposed configurations CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m CONFIG_TYPEC_RT1711H=m CONFIG_TYPEC_MT6360=m CONFIG_TYPEC_TCPCI_MT6370=m CONFIG_TYPEC_TCPCI_MAXIM=m CONFIG_TYPEC_FUSB302=m CONFIG_TYPEC_UCSI=m CONFIG_UCSI_CCG=m CONFIG_UCSI_ACPI=m CONFIG_UCSI_STM32G0=m CONFIG_TYPEC_TPS6598X=m CONFIG_TYPEC_ANX7411=m CONFIG_TYPEC_RT1719=m CONFIG_TYPEC_HD3SS3220=m CONFIG_TYPEC_STUSB160X=m CONFIG_TYPEC_QCOM_PMIC=m CONFIG_TYPEC_WUSB3801=m # # USB Type-C Multiplexer/DeMultiplexer Switch support # CONFIG_TYPEC_MUX_FSA4480=m CONFIG_TYPEC_MUX_PI3USB30532=m # end of USB Type-C Multiplexer/DeMultiplexer Switch support # # USB Type-C Alternate Mode drivers # CONFIG_TYPEC_DP_ALTMODE=m CONFIG_TYPEC_NVIDIA_ALTMODE=m # end of USB Type-C Alternate Mode drivers CONFIG_USB_ROLE_SWITCH=y CONFIG_MMC=m CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SD8787=m CONFIG_PWRSEQ_SIMPLE=m CONFIG_MMC_BLOCK=m CONFIG_MMC_BLOCK_MINORS=8 CONFIG_SDIO_UART=m CONFIG_MMC_TEST=m CONFIG_MMC_CRYPTO=y # # MMC/SD/SDIO Host Controller Drivers # CONFIG_MMC_DEBUG=y CONFIG_MMC_SDHCI=m CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_PCI=m CONFIG_MMC_RICOH_MMC=y CONFIG_MMC_SDHCI_ACPI=m CONFIG_MMC_SDHCI_PLTFM=m CONFIG_MMC_SDHCI_OF_ARASAN=m CONFIG_MMC_SDHCI_OF_ASPEED=m CONFIG_MMC_SDHCI_OF_ASPEED_TEST=y CONFIG_MMC_SDHCI_OF_AT91=m CONFIG_MMC_SDHCI_OF_ESDHC=m CONFIG_MMC_SDHCI_OF_DWCMSHC=m CONFIG_MMC_SDHCI_OF_SPARX5=m CONFIG_MMC_SDHCI_CADENCE=m CONFIG_MMC_SDHCI_CNS3XXX=m CONFIG_MMC_SDHCI_ESDHC_IMX=m CONFIG_MMC_SDHCI_DOVE=m CONFIG_MMC_SDHCI_TEGRA=m CONFIG_MMC_SDHCI_S3C=m CONFIG_MMC_SDHCI_PXAV3=m CONFIG_MMC_SDHCI_PXAV2=m CONFIG_MMC_SDHCI_SPEAR=m CONFIG_MMC_SDHCI_S3C_DMA=y CONFIG_MMC_SDHCI_BCM_KONA=m CONFIG_MMC_SDHCI_F_SDH30=m CONFIG_MMC_SDHCI_MILBEAUT=m CONFIG_MMC_SDHCI_IPROC=m CONFIG_MMC_MESON_GX=m CONFIG_MMC_MESON_MX_SDHC=m CONFIG_MMC_MESON_MX_SDIO=m CONFIG_MMC_MOXART=m CONFIG_MMC_SDHCI_ST=m CONFIG_MMC_OMAP_HS=m CONFIG_MMC_ALCOR=m CONFIG_MMC_SDHCI_MSM=m CONFIG_MMC_TIFM_SD=m CONFIG_MMC_DAVINCI=m CONFIG_MMC_SPI=m CONFIG_MMC_S3C=m CONFIG_MMC_S3C_HW_SDIO_IRQ=y CONFIG_MMC_S3C_PIO=y # CONFIG_MMC_S3C_DMA is not set CONFIG_MMC_SDRICOH_CS=m CONFIG_MMC_SDHCI_SPRD=m CONFIG_MMC_TMIO_CORE=m CONFIG_MMC_TMIO=m CONFIG_MMC_SDHI=m CONFIG_MMC_SDHI_SYS_DMAC=m CONFIG_MMC_SDHI_INTERNAL_DMAC=m CONFIG_MMC_UNIPHIER=m CONFIG_MMC_CB710=m CONFIG_MMC_VIA_SDMMC=m CONFIG_MMC_CAVIUM_THUNDERX=m CONFIG_MMC_DW=m CONFIG_MMC_DW_PLTFM=m CONFIG_MMC_DW_BLUEFIELD=m CONFIG_MMC_DW_EXYNOS=m CONFIG_MMC_DW_HI3798CV200=m CONFIG_MMC_DW_K3=m CONFIG_MMC_DW_PCI=m CONFIG_MMC_SH_MMCIF=m CONFIG_MMC_VUB300=m CONFIG_MMC_USHC=m CONFIG_MMC_USDHI6ROL0=m CONFIG_MMC_REALTEK_PCI=m CONFIG_MMC_REALTEK_USB=m CONFIG_MMC_SUNXI=m CONFIG_MMC_CQHCI=m CONFIG_MMC_HSQ=m CONFIG_MMC_TOSHIBA_PCI=m CONFIG_MMC_BCM2835=m CONFIG_MMC_MTK=m CONFIG_MMC_SDHCI_XENON=m CONFIG_MMC_SDHCI_OMAP=m CONFIG_MMC_SDHCI_AM654=m CONFIG_MMC_OWL=m CONFIG_MMC_SDHCI_EXTERNAL_DMA=y CONFIG_MMC_LITEX=m CONFIG_SCSI_UFSHCD=m CONFIG_SCSI_UFS_BSG=y CONFIG_SCSI_UFS_CRYPTO=y CONFIG_SCSI_UFS_HPB=y CONFIG_SCSI_UFS_FAULT_INJECTION=y CONFIG_SCSI_UFS_HWMON=y CONFIG_SCSI_UFSHCD_PCI=m CONFIG_SCSI_UFS_DWC_TC_PCI=m CONFIG_SCSI_UFSHCD_PLATFORM=m CONFIG_SCSI_UFS_CDNS_PLATFORM=m CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m CONFIG_SCSI_UFS_HISI=m CONFIG_SCSI_UFS_RENESAS=m CONFIG_SCSI_UFS_TI_J721E=m CONFIG_SCSI_UFS_EXYNOS=m CONFIG_MEMSTICK=m CONFIG_MEMSTICK_DEBUG=y # # MemoryStick drivers # CONFIG_MEMSTICK_UNSAFE_RESUME=y CONFIG_MSPRO_BLOCK=m CONFIG_MS_BLOCK=m # # MemoryStick Host Controller Drivers # CONFIG_MEMSTICK_TIFM_MS=m CONFIG_MEMSTICK_JMICRON_38X=m CONFIG_MEMSTICK_R592=m CONFIG_MEMSTICK_REALTEK_PCI=m CONFIG_MEMSTICK_REALTEK_USB=m CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=m CONFIG_LEDS_CLASS_FLASH=m CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y # # LED drivers # CONFIG_LEDS_AN30259A=m CONFIG_LEDS_ARIEL=m CONFIG_LEDS_AW2013=m CONFIG_LEDS_BCM6328=m CONFIG_LEDS_BCM6358=m CONFIG_LEDS_CPCAP=m CONFIG_LEDS_CR0014114=m CONFIG_LEDS_EL15203000=m CONFIG_LEDS_TURRIS_OMNIA=m CONFIG_LEDS_LM3530=m CONFIG_LEDS_LM3532=m CONFIG_LEDS_LM3533=m CONFIG_LEDS_LM3642=m CONFIG_LEDS_LM3692X=m CONFIG_LEDS_MT6323=m CONFIG_LEDS_S3C24XX=m CONFIG_LEDS_COBALT_QUBE=m CONFIG_LEDS_PCA9532=m CONFIG_LEDS_PCA9532_GPIO=y CONFIG_LEDS_GPIO=m CONFIG_LEDS_LP3944=m CONFIG_LEDS_LP3952=m CONFIG_LEDS_LP50XX=m CONFIG_LEDS_LP55XX_COMMON=m CONFIG_LEDS_LP5521=m CONFIG_LEDS_LP5523=m CONFIG_LEDS_LP5562=m CONFIG_LEDS_LP8501=m CONFIG_LEDS_LP8860=m CONFIG_LEDS_PCA955X=m CONFIG_LEDS_PCA955X_GPIO=y CONFIG_LEDS_PCA963X=m CONFIG_LEDS_WM831X_STATUS=m CONFIG_LEDS_DA9052=m CONFIG_LEDS_DAC124S085=m CONFIG_LEDS_PWM=m CONFIG_LEDS_REGULATOR=m CONFIG_LEDS_BD2802=m CONFIG_LEDS_LT3593=m CONFIG_LEDS_MC13783=m CONFIG_LEDS_NS2=m CONFIG_LEDS_NETXBIG=m CONFIG_LEDS_TCA6507=m CONFIG_LEDS_TLC591XX=m CONFIG_LEDS_MAX77650=m CONFIG_LEDS_LM355x=m CONFIG_LEDS_OT200=m CONFIG_LEDS_MENF21BMC=m CONFIG_LEDS_IS31FL319X=m CONFIG_LEDS_IS31FL32XX=m CONFIG_LEDS_SC27XX_BLTC=m # # LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) # CONFIG_LEDS_BLINKM=m CONFIG_LEDS_PM8058=m CONFIG_LEDS_MLXREG=m CONFIG_LEDS_USER=m CONFIG_LEDS_SPI_BYTE=m CONFIG_LEDS_TI_LMU_COMMON=m CONFIG_LEDS_LM3697=m CONFIG_LEDS_LM36274=m CONFIG_LEDS_TPS6105X=m CONFIG_LEDS_IP30=m CONFIG_LEDS_ACER_A500=m CONFIG_LEDS_BCM63138=m CONFIG_LEDS_LGM=m # # Flash and Torch LED drivers # CONFIG_LEDS_AAT1290=m CONFIG_LEDS_AS3645A=m CONFIG_LEDS_KTD2692=m CONFIG_LEDS_LM3601X=m CONFIG_LEDS_MAX77693=m CONFIG_LEDS_MT6360=m CONFIG_LEDS_RT4505=m CONFIG_LEDS_RT8515=m CONFIG_LEDS_SGM3140=m # # RGB LED drivers # CONFIG_LEDS_PWM_MULTICOLOR=m CONFIG_LEDS_QCOM_LPG=m # # LED Triggers # CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=m CONFIG_LEDS_TRIGGER_ONESHOT=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_HEARTBEAT=m CONFIG_LEDS_TRIGGER_BACKLIGHT=m CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_ACTIVITY=m CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_DEFAULT_ON=m # # iptables trigger is under Netfilter config (LED target) # CONFIG_LEDS_TRIGGER_TRANSIENT=m CONFIG_LEDS_TRIGGER_CAMERA=m CONFIG_LEDS_TRIGGER_PANIC=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_PATTERN=m CONFIG_LEDS_TRIGGER_AUDIO=m CONFIG_LEDS_TRIGGER_TTY=m # # Simple LED drivers # CONFIG_ACCESSIBILITY=y CONFIG_A11Y_BRAILLE_CONSOLE=y # # Speakup console speech # CONFIG_SPEAKUP=m CONFIG_SPEAKUP_SERIALIO=y CONFIG_SPEAKUP_SYNTH_ACNTSA=m CONFIG_SPEAKUP_SYNTH_ACNTPC=m CONFIG_SPEAKUP_SYNTH_APOLLO=m CONFIG_SPEAKUP_SYNTH_AUDPTR=m CONFIG_SPEAKUP_SYNTH_BNS=m CONFIG_SPEAKUP_SYNTH_DECTLK=m CONFIG_SPEAKUP_SYNTH_DECEXT=m CONFIG_SPEAKUP_SYNTH_DECPC=m CONFIG_SPEAKUP_SYNTH_DTLK=m CONFIG_SPEAKUP_SYNTH_KEYPC=m CONFIG_SPEAKUP_SYNTH_LTLK=m CONFIG_SPEAKUP_SYNTH_SOFT=m CONFIG_SPEAKUP_SYNTH_SPKOUT=m CONFIG_SPEAKUP_SYNTH_TXPRT=m CONFIG_SPEAKUP_SYNTH_DUMMY=m # end of Speakup console speech CONFIG_INFINIBAND=m CONFIG_INFINIBAND_USER_MAD=m CONFIG_INFINIBAND_USER_ACCESS=m CONFIG_INFINIBAND_USER_MEM=y CONFIG_INFINIBAND_ON_DEMAND_PAGING=y CONFIG_INFINIBAND_ADDR_TRANS=y CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y CONFIG_INFINIBAND_VIRT_DMA=y CONFIG_INFINIBAND_BNXT_RE=m CONFIG_INFINIBAND_CXGB4=m CONFIG_INFINIBAND_EFA=m CONFIG_INFINIBAND_ERDMA=m CONFIG_INFINIBAND_HNS=m CONFIG_INFINIBAND_HNS_HIP08=y CONFIG_INFINIBAND_IRDMA=m CONFIG_MLX4_INFINIBAND=m CONFIG_MLX5_INFINIBAND=m CONFIG_INFINIBAND_MTHCA=m CONFIG_INFINIBAND_MTHCA_DEBUG=y CONFIG_INFINIBAND_OCRDMA=m CONFIG_INFINIBAND_QEDR=m CONFIG_INFINIBAND_USNIC=m CONFIG_INFINIBAND_VMWARE_PVRDMA=m CONFIG_RDMA_RXE=m CONFIG_RDMA_SIW=m CONFIG_INFINIBAND_IPOIB=m CONFIG_INFINIBAND_IPOIB_CM=y CONFIG_INFINIBAND_IPOIB_DEBUG=y CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y CONFIG_INFINIBAND_SRP=m CONFIG_INFINIBAND_SRPT=m CONFIG_INFINIBAND_ISER=m CONFIG_INFINIBAND_ISERT=m CONFIG_INFINIBAND_RTRS=m CONFIG_INFINIBAND_RTRS_CLIENT=m CONFIG_INFINIBAND_RTRS_SERVER=m CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y CONFIG_RTC_HCTOSYS_DEVICE="rtc0" CONFIG_RTC_SYSTOHC=y CONFIG_RTC_SYSTOHC_DEVICE="rtc0" CONFIG_RTC_DEBUG=y CONFIG_RTC_LIB_KUNIT_TEST=m CONFIG_RTC_NVMEM=y # # RTC interfaces # CONFIG_RTC_INTF_SYSFS=y CONFIG_RTC_INTF_PROC=y CONFIG_RTC_INTF_DEV=y CONFIG_RTC_INTF_DEV_UIE_EMUL=y CONFIG_RTC_DRV_TEST=m # # I2C RTC drivers # CONFIG_RTC_DRV_88PM80X=m CONFIG_RTC_DRV_ABB5ZES3=m CONFIG_RTC_DRV_ABEOZ9=m CONFIG_RTC_DRV_ABX80X=m CONFIG_RTC_DRV_BRCMSTB=m CONFIG_RTC_DRV_DS1307=m CONFIG_RTC_DRV_DS1307_CENTURY=y CONFIG_RTC_DRV_DS1374=m CONFIG_RTC_DRV_DS1374_WDT=y CONFIG_RTC_DRV_DS1672=m CONFIG_RTC_DRV_HYM8563=m CONFIG_RTC_DRV_MAX6900=m CONFIG_RTC_DRV_MAX8907=m CONFIG_RTC_DRV_MAX77686=m CONFIG_RTC_DRV_NCT3018Y=m CONFIG_RTC_DRV_RK808=m CONFIG_RTC_DRV_RS5C372=m CONFIG_RTC_DRV_ISL1208=m CONFIG_RTC_DRV_ISL12022=m CONFIG_RTC_DRV_ISL12026=m CONFIG_RTC_DRV_X1205=m CONFIG_RTC_DRV_PCF8523=m CONFIG_RTC_DRV_PCF85063=m CONFIG_RTC_DRV_PCF85363=m CONFIG_RTC_DRV_PCF8563=m CONFIG_RTC_DRV_PCF8583=m CONFIG_RTC_DRV_M41T80=m CONFIG_RTC_DRV_M41T80_WDT=y CONFIG_RTC_DRV_BQ32K=m CONFIG_RTC_DRV_RC5T619=m CONFIG_RTC_DRV_S35390A=m CONFIG_RTC_DRV_FM3130=m CONFIG_RTC_DRV_RX8010=m CONFIG_RTC_DRV_RX8581=m CONFIG_RTC_DRV_RX8025=m CONFIG_RTC_DRV_EM3027=m CONFIG_RTC_DRV_RV3028=m CONFIG_RTC_DRV_RV3032=m CONFIG_RTC_DRV_RV8803=m CONFIG_RTC_DRV_S5M=m CONFIG_RTC_DRV_SD3078=m # # SPI RTC drivers # CONFIG_RTC_DRV_M41T93=m CONFIG_RTC_DRV_M41T94=m CONFIG_RTC_DRV_DS1302=m CONFIG_RTC_DRV_DS1305=m CONFIG_RTC_DRV_DS1343=m CONFIG_RTC_DRV_DS1347=m CONFIG_RTC_DRV_DS1390=m CONFIG_RTC_DRV_MAX6916=m CONFIG_RTC_DRV_R9701=m CONFIG_RTC_DRV_RX4581=m CONFIG_RTC_DRV_RS5C348=m CONFIG_RTC_DRV_MAX6902=m CONFIG_RTC_DRV_PCF2123=m CONFIG_RTC_DRV_MCP795=m CONFIG_RTC_I2C_AND_SPI=m # # SPI and I2C RTC drivers # CONFIG_RTC_DRV_DS3232=m CONFIG_RTC_DRV_DS3232_HWMON=y CONFIG_RTC_DRV_PCF2127=m CONFIG_RTC_DRV_RV3029C2=m CONFIG_RTC_DRV_RV3029_HWMON=y CONFIG_RTC_DRV_RX6110=m # # Platform RTC drivers # CONFIG_RTC_DRV_DS1286=m CONFIG_RTC_DRV_DS1511=m CONFIG_RTC_DRV_DS1553=m CONFIG_RTC_DRV_DS1685_FAMILY=m CONFIG_RTC_DRV_DS1685=y # CONFIG_RTC_DRV_DS1689 is not set # CONFIG_RTC_DRV_DS17285 is not set # CONFIG_RTC_DRV_DS17485 is not set # CONFIG_RTC_DRV_DS17885 is not set CONFIG_RTC_DRV_DS1742=m CONFIG_RTC_DRV_DS2404=m CONFIG_RTC_DRV_DA9052=m CONFIG_RTC_DRV_DA9063=m CONFIG_RTC_DRV_EFI=m CONFIG_RTC_DRV_STK17TA8=m CONFIG_RTC_DRV_M48T86=m CONFIG_RTC_DRV_M48T35=m CONFIG_RTC_DRV_M48T59=m CONFIG_RTC_DRV_MSM6242=m CONFIG_RTC_DRV_BQ4802=m CONFIG_RTC_DRV_RP5C01=m CONFIG_RTC_DRV_V3020=m CONFIG_RTC_DRV_GAMECUBE=m CONFIG_RTC_DRV_WM831X=m CONFIG_RTC_DRV_SC27XX=m CONFIG_RTC_DRV_SPEAR=m CONFIG_RTC_DRV_PCF50633=m CONFIG_RTC_DRV_ZYNQMP=m CONFIG_RTC_DRV_CROS_EC=m CONFIG_RTC_DRV_NTXEC=m # # on-CPU RTC drivers # CONFIG_RTC_DRV_ASM9260=m CONFIG_RTC_DRV_DAVINCI=m CONFIG_RTC_DRV_DIGICOLOR=m CONFIG_RTC_DRV_FSL_FTM_ALARM=m CONFIG_RTC_DRV_MESON=m CONFIG_RTC_DRV_MESON_VRTC=m CONFIG_RTC_DRV_OMAP=m CONFIG_RTC_DRV_S3C=m CONFIG_RTC_DRV_EP93XX=m CONFIG_RTC_DRV_AT91RM9200=m CONFIG_RTC_DRV_AT91SAM9=m CONFIG_RTC_DRV_RZN1=m CONFIG_RTC_DRV_GENERIC=m CONFIG_RTC_DRV_VT8500=m CONFIG_RTC_DRV_SUN6I=y CONFIG_RTC_DRV_SUNXI=m CONFIG_RTC_DRV_MV=m CONFIG_RTC_DRV_ARMADA38X=m CONFIG_RTC_DRV_CADENCE=m CONFIG_RTC_DRV_FTRTC010=m CONFIG_RTC_DRV_STMP=m CONFIG_RTC_DRV_PCAP=m CONFIG_RTC_DRV_MC13XXX=m CONFIG_RTC_DRV_JZ4740=m CONFIG_RTC_DRV_LPC24XX=m CONFIG_RTC_DRV_LPC32XX=m CONFIG_RTC_DRV_PM8XXX=m CONFIG_RTC_DRV_TEGRA=m CONFIG_RTC_DRV_MXC=m CONFIG_RTC_DRV_MXC_V2=m CONFIG_RTC_DRV_SNVS=m CONFIG_RTC_DRV_MOXART=m CONFIG_RTC_DRV_MT2712=m CONFIG_RTC_DRV_MT6397=m CONFIG_RTC_DRV_MT7622=m CONFIG_RTC_DRV_XGENE=m CONFIG_RTC_DRV_R7301=m CONFIG_RTC_DRV_STM32=m CONFIG_RTC_DRV_CPCAP=m CONFIG_RTC_DRV_RTD119X=y CONFIG_RTC_DRV_ASPEED=m CONFIG_RTC_DRV_TI_K3=m # # HID Sensor RTC drivers # CONFIG_RTC_DRV_HID_SENSOR_TIME=m CONFIG_RTC_DRV_GOLDFISH=m CONFIG_RTC_DRV_WILCO_EC=m CONFIG_RTC_DRV_MSC313=m CONFIG_DMADEVICES=y CONFIG_DMADEVICES_DEBUG=y CONFIG_DMADEVICES_VDEBUG=y # # DMA Devices # CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y CONFIG_DMA_ENGINE=y CONFIG_DMA_VIRTUAL_CHANNELS=y CONFIG_DMA_ACPI=y CONFIG_DMA_OF=y CONFIG_ALTERA_MSGDMA=m CONFIG_APPLE_ADMAC=m CONFIG_AXI_DMAC=m CONFIG_BCM_SBA_RAID=m CONFIG_DMA_JZ4780=m CONFIG_DMA_SA11X0=m CONFIG_DMA_SUN6I=m CONFIG_DW_AXI_DMAC=m CONFIG_EP93XX_DMA=y CONFIG_FSL_EDMA=m CONFIG_HISI_DMA=m CONFIG_IMG_MDC_DMA=m CONFIG_INTEL_IDMA64=m CONFIG_INTEL_IOP_ADMA=m CONFIG_K3_DMA=m CONFIG_MCF_EDMA=m CONFIG_MILBEAUT_HDMAC=m CONFIG_MILBEAUT_XDMAC=m CONFIG_MMP_PDMA=m CONFIG_MMP_TDMA=m CONFIG_MV_XOR=y CONFIG_MXS_DMA=y CONFIG_NBPFAXI_DMA=m CONFIG_PCH_DMA=m CONFIG_PLX_DMA=m CONFIG_STM32_DMA=y CONFIG_STM32_DMAMUX=y CONFIG_STM32_MDMA=y CONFIG_SPRD_DMA=m CONFIG_S3C24XX_DMAC=y CONFIG_TEGRA186_GPC_DMA=m CONFIG_TEGRA20_APB_DMA=m CONFIG_TEGRA210_ADMA=m CONFIG_TIMB_DMA=m CONFIG_UNIPHIER_MDMAC=m CONFIG_UNIPHIER_XDMAC=m CONFIG_XGENE_DMA=m CONFIG_XILINX_ZYNQMP_DMA=m CONFIG_XILINX_ZYNQMP_DPDMA=m CONFIG_MTK_HSDMA=m CONFIG_MTK_CQDMA=m CONFIG_MTK_UART_APDMA=m CONFIG_QCOM_HIDMA_MGMT=m CONFIG_QCOM_HIDMA=m CONFIG_DW_DMAC_CORE=m CONFIG_DW_DMAC=m CONFIG_RZN1_DMAMUX=m CONFIG_DW_DMAC_PCI=m CONFIG_DW_EDMA=m CONFIG_DW_EDMA_PCIE=m CONFIG_HSU_DMA=m CONFIG_SF_PDMA=m CONFIG_RENESAS_DMA=y CONFIG_SH_DMAE_BASE=y CONFIG_SH_DMAE=m CONFIG_RCAR_DMAC=m CONFIG_RENESAS_USB_DMAC=m CONFIG_RZ_DMAC=m CONFIG_TI_EDMA=m CONFIG_DMA_OMAP=m CONFIG_TI_DMA_CROSSBAR=y CONFIG_INTEL_LDMA=y # # DMA Clients # CONFIG_ASYNC_TX_DMA=y CONFIG_DMATEST=m CONFIG_DMA_ENGINE_RAID=y # # DMABUF options # CONFIG_SYNC_FILE=y CONFIG_SW_SYNC=y CONFIG_UDMABUF=y CONFIG_DMABUF_MOVE_NOTIFY=y CONFIG_DMABUF_DEBUG=y CONFIG_DMABUF_SELFTESTS=m CONFIG_DMABUF_HEAPS=y CONFIG_DMABUF_SYSFS_STATS=y CONFIG_DMABUF_HEAPS_SYSTEM=y # end of DMABUF options CONFIG_AUXDISPLAY=y CONFIG_CHARLCD=m CONFIG_LINEDISP=m CONFIG_HD44780_COMMON=m CONFIG_HD44780=m CONFIG_KS0108=m CONFIG_KS0108_PORT=0x378 CONFIG_KS0108_DELAY=2 CONFIG_IMG_ASCII_LCD=m CONFIG_HT16K33=m CONFIG_LCD2S=m CONFIG_PARPORT_PANEL=m CONFIG_PANEL_PARPORT=0 CONFIG_PANEL_PROFILE=5 CONFIG_PANEL_CHANGE_MESSAGE=y CONFIG_PANEL_BOOT_MESSAGE="" # CONFIG_CHARLCD_BL_OFF is not set # CONFIG_CHARLCD_BL_ON is not set CONFIG_CHARLCD_BL_FLASH=y CONFIG_PANEL=m CONFIG_UIO=m CONFIG_UIO_CIF=m CONFIG_UIO_PDRV_GENIRQ=m CONFIG_UIO_DMEM_GENIRQ=m CONFIG_UIO_AEC=m CONFIG_UIO_SERCOS3=m CONFIG_UIO_PCI_GENERIC=m CONFIG_UIO_NETX=m CONFIG_UIO_PRUSS=m CONFIG_UIO_MF624=m CONFIG_UIO_DFL=m CONFIG_VFIO=m CONFIG_VFIO_VIRQFD=m CONFIG_VFIO_NOIOMMU=y CONFIG_VFIO_PCI_CORE=m CONFIG_VFIO_PCI_MMAP=y CONFIG_VFIO_PCI_INTX=y CONFIG_VFIO_PCI=m CONFIG_MLX5_VFIO_PCI=m CONFIG_HISI_ACC_VFIO_PCI=m CONFIG_VFIO_PLATFORM=m CONFIG_VFIO_AMBA=m CONFIG_VFIO_PLATFORM_CALXEDAXGMAC_RESET=m CONFIG_VFIO_PLATFORM_AMDXGBE_RESET=m CONFIG_VFIO_PLATFORM_BCMFLEXRM_RESET=m CONFIG_VFIO_MDEV=m CONFIG_IRQ_BYPASS_MANAGER=m CONFIG_VIRT_DRIVERS=y CONFIG_VMGENID=m CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=y CONFIG_VIRTIO_PCI_LIB=m CONFIG_VIRTIO_PCI_LIB_LEGACY=m CONFIG_VIRTIO_MENU=y CONFIG_VIRTIO_PCI=m CONFIG_VIRTIO_PCI_LEGACY=y CONFIG_VIRTIO_VDPA=m CONFIG_VIRTIO_PMEM=m CONFIG_VIRTIO_BALLOON=m CONFIG_VIRTIO_INPUT=m CONFIG_VIRTIO_MMIO=m CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y CONFIG_VIRTIO_DMA_SHARED_BUFFER=m CONFIG_VDPA=m CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_SIM_BLOCK=m CONFIG_VDPA_USER=m CONFIG_IFCVF=m CONFIG_MLX5_VDPA=y CONFIG_MLX5_VDPA_NET=m CONFIG_VP_VDPA=m CONFIG_VHOST_IOTLB=m CONFIG_VHOST_RING=m CONFIG_VHOST=m CONFIG_VHOST_MENU=y CONFIG_VHOST_NET=m CONFIG_VHOST_SCSI=m CONFIG_VHOST_VSOCK=m CONFIG_VHOST_VDPA=m CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y # # Microsoft Hyper-V guest support # # end of Microsoft Hyper-V guest support CONFIG_GREYBUS=m CONFIG_GREYBUS_ES2=m CONFIG_COMEDI=m CONFIG_COMEDI_DEBUG=y CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 CONFIG_COMEDI_MISC_DRIVERS=y CONFIG_COMEDI_BOND=m CONFIG_COMEDI_TEST=m CONFIG_COMEDI_PARPORT=m CONFIG_COMEDI_SSV_DNP=m CONFIG_COMEDI_ISA_DRIVERS=y CONFIG_COMEDI_PCL711=m CONFIG_COMEDI_PCL724=m CONFIG_COMEDI_PCL726=m CONFIG_COMEDI_PCL730=m CONFIG_COMEDI_PCL812=m CONFIG_COMEDI_PCL816=m CONFIG_COMEDI_PCL818=m CONFIG_COMEDI_PCM3724=m CONFIG_COMEDI_AMPLC_DIO200_ISA=m CONFIG_COMEDI_AMPLC_PC236_ISA=m CONFIG_COMEDI_AMPLC_PC263_ISA=m CONFIG_COMEDI_RTI800=m CONFIG_COMEDI_RTI802=m CONFIG_COMEDI_DAC02=m CONFIG_COMEDI_DAS16M1=m CONFIG_COMEDI_DAS08_ISA=m CONFIG_COMEDI_DAS16=m CONFIG_COMEDI_DAS800=m CONFIG_COMEDI_DAS1800=m CONFIG_COMEDI_DAS6402=m CONFIG_COMEDI_DT2801=m CONFIG_COMEDI_DT2811=m CONFIG_COMEDI_DT2814=m CONFIG_COMEDI_DT2815=m CONFIG_COMEDI_DT2817=m CONFIG_COMEDI_DT282X=m CONFIG_COMEDI_DMM32AT=m CONFIG_COMEDI_FL512=m CONFIG_COMEDI_AIO_AIO12_8=m CONFIG_COMEDI_AIO_IIRO_16=m CONFIG_COMEDI_II_PCI20KC=m CONFIG_COMEDI_C6XDIGIO=m CONFIG_COMEDI_MPC624=m CONFIG_COMEDI_ADQ12B=m CONFIG_COMEDI_NI_AT_A2150=m CONFIG_COMEDI_NI_AT_AO=m CONFIG_COMEDI_NI_ATMIO=m CONFIG_COMEDI_NI_ATMIO16D=m CONFIG_COMEDI_NI_LABPC_ISA=m CONFIG_COMEDI_PCMAD=m CONFIG_COMEDI_PCMDA12=m CONFIG_COMEDI_PCMMIO=m CONFIG_COMEDI_PCMUIO=m CONFIG_COMEDI_MULTIQ3=m CONFIG_COMEDI_S526=m CONFIG_COMEDI_PCI_DRIVERS=m CONFIG_COMEDI_8255_PCI=m CONFIG_COMEDI_ADDI_WATCHDOG=m CONFIG_COMEDI_ADDI_APCI_1032=m CONFIG_COMEDI_ADDI_APCI_1500=m CONFIG_COMEDI_ADDI_APCI_1516=m CONFIG_COMEDI_ADDI_APCI_1564=m CONFIG_COMEDI_ADDI_APCI_16XX=m CONFIG_COMEDI_ADDI_APCI_2032=m CONFIG_COMEDI_ADDI_APCI_2200=m CONFIG_COMEDI_ADDI_APCI_3120=m CONFIG_COMEDI_ADDI_APCI_3501=m CONFIG_COMEDI_ADDI_APCI_3XXX=m CONFIG_COMEDI_ADL_PCI6208=m CONFIG_COMEDI_ADL_PCI7X3X=m CONFIG_COMEDI_ADL_PCI8164=m CONFIG_COMEDI_ADL_PCI9111=m CONFIG_COMEDI_ADL_PCI9118=m CONFIG_COMEDI_ADV_PCI1710=m CONFIG_COMEDI_ADV_PCI1720=m CONFIG_COMEDI_ADV_PCI1723=m CONFIG_COMEDI_ADV_PCI1724=m CONFIG_COMEDI_ADV_PCI1760=m CONFIG_COMEDI_ADV_PCI_DIO=m CONFIG_COMEDI_AMPLC_DIO200_PCI=m CONFIG_COMEDI_AMPLC_PC236_PCI=m CONFIG_COMEDI_AMPLC_PC263_PCI=m CONFIG_COMEDI_AMPLC_PCI224=m CONFIG_COMEDI_AMPLC_PCI230=m CONFIG_COMEDI_CONTEC_PCI_DIO=m CONFIG_COMEDI_DAS08_PCI=m CONFIG_COMEDI_DT3000=m CONFIG_COMEDI_DYNA_PCI10XX=m CONFIG_COMEDI_GSC_HPDI=m CONFIG_COMEDI_MF6X4=m CONFIG_COMEDI_ICP_MULTI=m CONFIG_COMEDI_DAQBOARD2000=m CONFIG_COMEDI_JR3_PCI=m CONFIG_COMEDI_KE_COUNTER=m CONFIG_COMEDI_CB_PCIDAS64=m CONFIG_COMEDI_CB_PCIDAS=m CONFIG_COMEDI_CB_PCIDDA=m CONFIG_COMEDI_CB_PCIMDAS=m CONFIG_COMEDI_CB_PCIMDDA=m CONFIG_COMEDI_ME4000=m CONFIG_COMEDI_ME_DAQ=m CONFIG_COMEDI_NI_6527=m CONFIG_COMEDI_NI_65XX=m CONFIG_COMEDI_NI_660X=m CONFIG_COMEDI_NI_670X=m CONFIG_COMEDI_NI_LABPC_PCI=m CONFIG_COMEDI_NI_PCIDIO=m CONFIG_COMEDI_NI_PCIMIO=m CONFIG_COMEDI_RTD520=m CONFIG_COMEDI_S626=m CONFIG_COMEDI_MITE=m CONFIG_COMEDI_NI_TIOCMD=m CONFIG_COMEDI_PCMCIA_DRIVERS=m CONFIG_COMEDI_CB_DAS16_CS=m CONFIG_COMEDI_DAS08_CS=m CONFIG_COMEDI_NI_DAQ_700_CS=m CONFIG_COMEDI_NI_DAQ_DIO24_CS=m CONFIG_COMEDI_NI_LABPC_CS=m CONFIG_COMEDI_NI_MIO_CS=m CONFIG_COMEDI_QUATECH_DAQP_CS=m CONFIG_COMEDI_USB_DRIVERS=m CONFIG_COMEDI_DT9812=m CONFIG_COMEDI_NI_USB6501=m CONFIG_COMEDI_USBDUX=m CONFIG_COMEDI_USBDUXFAST=m CONFIG_COMEDI_USBDUXSIGMA=m CONFIG_COMEDI_VMK80XX=m CONFIG_COMEDI_8254=m CONFIG_COMEDI_8255=m CONFIG_COMEDI_8255_SA=m CONFIG_COMEDI_KCOMEDILIB=m CONFIG_COMEDI_AMPLC_DIO200=m CONFIG_COMEDI_AMPLC_PC236=m CONFIG_COMEDI_DAS08=m CONFIG_COMEDI_NI_LABPC=m CONFIG_COMEDI_NI_TIO=m CONFIG_COMEDI_NI_ROUTING=m CONFIG_COMEDI_TESTS=m CONFIG_COMEDI_TESTS_EXAMPLE=m CONFIG_COMEDI_TESTS_NI_ROUTES=m CONFIG_STAGING=y CONFIG_PRISM2_USB=m CONFIG_RTL8192U=m CONFIG_RTLLIB=m CONFIG_RTLLIB_CRYPTO_CCMP=m CONFIG_RTLLIB_CRYPTO_TKIP=m CONFIG_RTLLIB_CRYPTO_WEP=m CONFIG_RTL8192E=m CONFIG_RTL8723BS=m CONFIG_R8712U=m CONFIG_R8188EU=m CONFIG_RTS5208=m CONFIG_OCTEON_ETHERNET=m CONFIG_VT6655=m CONFIG_VT6656=m # # IIO staging drivers # # # Accelerometers # CONFIG_ADIS16203=m CONFIG_ADIS16240=m # end of Accelerometers # # Analog to digital converters # CONFIG_AD7816=m # end of Analog to digital converters # # Analog digital bi-direction converters # CONFIG_ADT7316=m CONFIG_ADT7316_SPI=m CONFIG_ADT7316_I2C=m # end of Analog digital bi-direction converters # # Direct Digital Synthesis # CONFIG_AD9832=m CONFIG_AD9834=m # end of Direct Digital Synthesis # # Network Analyzer, Impedance Converters # CONFIG_AD5933=m # end of Network Analyzer, Impedance Converters # # Active energy metering IC # CONFIG_ADE7854=m CONFIG_ADE7854_I2C=m CONFIG_ADE7854_SPI=m # end of Active energy metering IC # # Resolver to digital converters # CONFIG_AD2S1210=m # end of Resolver to digital converters # end of IIO staging drivers CONFIG_FB_SM750=m CONFIG_USB_EMXX=m CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_IMX_MEDIA=m # # i.MX5/6/7/8 Media Sub devices # CONFIG_VIDEO_IMX_CSI=m # end of i.MX5/6/7/8 Media Sub devices CONFIG_VIDEO_IMX8MQ_MIPI_CSI2=m CONFIG_VIDEO_MAX96712=m CONFIG_VIDEO_MESON_VDEC=m CONFIG_VIDEO_OMAP4=m CONFIG_VIDEO_ROCKCHIP_VDEC=m CONFIG_VIDEO_SUNXI=y CONFIG_VIDEO_SUNXI_CEDRUS=m CONFIG_VIDEO_SUN6I_ISP=m CONFIG_STAGING_MEDIA_DEPRECATED=y # # Atmel media platform drivers # CONFIG_VIDEO_ATMEL_ISC=m CONFIG_VIDEO_ATMEL_XISC=m CONFIG_VIDEO_ATMEL_ISC_BASE=m CONFIG_VIDEO_CPIA2=m CONFIG_VIDEO_VIU=m CONFIG_VIDEO_SAA7146=m CONFIG_VIDEO_SAA7146_VV=m CONFIG_DVB_AV7110_IR=y CONFIG_DVB_AV7110=m CONFIG_DVB_AV7110_OSD=y CONFIG_DVB_BUDGET_PATCH=m CONFIG_DVB_SP8870=m CONFIG_VIDEO_HEXIUM_GEMINI=m CONFIG_VIDEO_HEXIUM_ORION=m CONFIG_VIDEO_MXB=m CONFIG_DVB_BUDGET_CORE=m CONFIG_DVB_BUDGET=m CONFIG_DVB_BUDGET_CI=m CONFIG_DVB_BUDGET_AV=m CONFIG_VIDEO_STKWEBCAM=m CONFIG_VIDEO_TM6000=m CONFIG_VIDEO_TM6000_DVB=m CONFIG_VIDEO_DM6446_CCDC=m CONFIG_VIDEO_DM355_CCDC=m CONFIG_VIDEO_DM365_ISIF=m CONFIG_USB_ZR364XX=m CONFIG_STAGING_BOARD=y CONFIG_LTE_GDM724X=m CONFIG_FB_TFT=m CONFIG_FB_TFT_AGM1264K_FL=m CONFIG_FB_TFT_BD663474=m CONFIG_FB_TFT_HX8340BN=m CONFIG_FB_TFT_HX8347D=m CONFIG_FB_TFT_HX8353D=m CONFIG_FB_TFT_HX8357D=m CONFIG_FB_TFT_ILI9163=m CONFIG_FB_TFT_ILI9320=m CONFIG_FB_TFT_ILI9325=m CONFIG_FB_TFT_ILI9340=m CONFIG_FB_TFT_ILI9341=m CONFIG_FB_TFT_ILI9481=m CONFIG_FB_TFT_ILI9486=m CONFIG_FB_TFT_PCD8544=m CONFIG_FB_TFT_RA8875=m CONFIG_FB_TFT_S6D02A1=m CONFIG_FB_TFT_S6D1121=m CONFIG_FB_TFT_SEPS525=m CONFIG_FB_TFT_SH1106=m CONFIG_FB_TFT_SSD1289=m CONFIG_FB_TFT_SSD1305=m CONFIG_FB_TFT_SSD1306=m CONFIG_FB_TFT_SSD1331=m CONFIG_FB_TFT_SSD1351=m CONFIG_FB_TFT_ST7735R=m CONFIG_FB_TFT_ST7789V=m CONFIG_FB_TFT_TINYLCD=m CONFIG_FB_TFT_TLS8204=m CONFIG_FB_TFT_UC1611=m CONFIG_FB_TFT_UC1701=m CONFIG_FB_TFT_UPD161704=m CONFIG_MOST_COMPONENTS=m CONFIG_MOST_NET=m CONFIG_MOST_VIDEO=m CONFIG_MOST_DIM2=m CONFIG_MOST_I2C=m CONFIG_KS7010=m CONFIG_GREYBUS_BOOTROM=m CONFIG_GREYBUS_FIRMWARE=m CONFIG_GREYBUS_HID=m CONFIG_GREYBUS_LIGHT=m CONFIG_GREYBUS_LOG=m CONFIG_GREYBUS_LOOPBACK=m CONFIG_GREYBUS_POWER=m CONFIG_GREYBUS_RAW=m CONFIG_GREYBUS_VIBRATOR=m CONFIG_GREYBUS_BRIDGED_PHY=m CONFIG_GREYBUS_GPIO=m CONFIG_GREYBUS_I2C=m CONFIG_GREYBUS_PWM=m CONFIG_GREYBUS_SDIO=m CONFIG_GREYBUS_SPI=m CONFIG_GREYBUS_UART=m CONFIG_GREYBUS_USB=m CONFIG_GREYBUS_ARCHE=m CONFIG_BCM_VIDEOCORE=m CONFIG_BCM2835_VCHIQ=m CONFIG_VCHIQ_CDEV=y CONFIG_VIDEO_BCM2835=m CONFIG_BCM2835_VCHIQ_MMAL=m CONFIG_PI433=m CONFIG_XIL_AXIS_FIFO=m CONFIG_FIELDBUS_DEV=m CONFIG_HMS_ANYBUSS_BUS=m CONFIG_ARCX_ANYBUS_CONTROLLER=m CONFIG_HMS_PROFINET=m CONFIG_QLGE=m CONFIG_VME_BUS=y # # VME Bridge Drivers # CONFIG_VME_TSI148=m CONFIG_VME_FAKE=m # # VME Device Drivers # CONFIG_VME_USER=m CONFIG_GOLDFISH=y CONFIG_GOLDFISH_PIPE=m CONFIG_CHROME_PLATFORMS=y CONFIG_CHROMEOS_ACPI=m CONFIG_CHROMEOS_TBMC=m CONFIG_CROS_EC=m CONFIG_CROS_EC_I2C=m CONFIG_CROS_EC_RPMSG=m CONFIG_CROS_EC_SPI=m CONFIG_CROS_EC_LPC=m CONFIG_CROS_EC_PROTO=y CONFIG_CROS_KBD_LED_BACKLIGHT=m CONFIG_CROS_EC_CHARDEV=m CONFIG_CROS_EC_LIGHTBAR=m CONFIG_CROS_EC_VBC=m CONFIG_CROS_EC_DEBUGFS=m CONFIG_CROS_EC_SENSORHUB=m CONFIG_CROS_EC_SYSFS=m CONFIG_CROS_EC_TYPEC=m CONFIG_CROS_USBPD_LOGGER=m CONFIG_CROS_USBPD_NOTIFY=m CONFIG_CHROMEOS_PRIVACY_SCREEN=m CONFIG_CROS_TYPEC_SWITCH=m CONFIG_WILCO_EC=m CONFIG_WILCO_EC_DEBUGFS=m CONFIG_WILCO_EC_EVENTS=m CONFIG_WILCO_EC_TELEMETRY=m CONFIG_CROS_KUNIT=m CONFIG_MELLANOX_PLATFORM=y CONFIG_MLXREG_HOTPLUG=m CONFIG_MLXREG_IO=m CONFIG_MLXREG_LC=m CONFIG_NVSW_SN2201=m CONFIG_OLPC_EC=y CONFIG_OLPC_XO175=y CONFIG_OLPC_XO175_EC=m CONFIG_SURFACE_PLATFORMS=y CONFIG_SURFACE_3_POWER_OPREGION=m CONFIG_SURFACE_ACPI_NOTIFY=m CONFIG_SURFACE_AGGREGATOR_CDEV=m CONFIG_SURFACE_AGGREGATOR_HUB=m CONFIG_SURFACE_AGGREGATOR_REGISTRY=m CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m CONFIG_SURFACE_DTX=m CONFIG_SURFACE_GPE=m CONFIG_SURFACE_HOTPLUG=m CONFIG_SURFACE_PLATFORM_PROFILE=m CONFIG_SURFACE_PRO3_BUTTON=m CONFIG_SURFACE_AGGREGATOR=m CONFIG_SURFACE_AGGREGATOR_BUS=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_WM831X=m # # Clock driver for ARM Reference designs # CONFIG_CLK_ICST=y CONFIG_CLK_SP810=y # end of Clock driver for ARM Reference designs CONFIG_CLK_HSDK=y CONFIG_LMK04832=m CONFIG_COMMON_CLK_APPLE_NCO=m CONFIG_COMMON_CLK_MAX77686=m CONFIG_COMMON_CLK_MAX9485=m CONFIG_COMMON_CLK_RK808=m CONFIG_COMMON_CLK_HI655X=m CONFIG_COMMON_CLK_SCMI=m CONFIG_COMMON_CLK_SCPI=m CONFIG_COMMON_CLK_SI5341=m CONFIG_COMMON_CLK_SI5351=m CONFIG_COMMON_CLK_SI514=m CONFIG_COMMON_CLK_SI544=m CONFIG_COMMON_CLK_SI570=m CONFIG_COMMON_CLK_BM1880=y CONFIG_COMMON_CLK_CDCE706=m CONFIG_COMMON_CLK_TPS68470=m CONFIG_COMMON_CLK_CDCE925=m CONFIG_COMMON_CLK_CS2000_CP=m CONFIG_COMMON_CLK_EN7523=y CONFIG_COMMON_CLK_FSL_FLEXSPI=m CONFIG_COMMON_CLK_FSL_SAI=y CONFIG_COMMON_CLK_GEMINI=y CONFIG_COMMON_CLK_LAN966X=m CONFIG_COMMON_CLK_ASPEED=y CONFIG_COMMON_CLK_S2MPS11=m CONFIG_COMMON_CLK_AXI_CLKGEN=m CONFIG_CLK_QORIQ=y CONFIG_CLK_LS1028A_PLLDIG=m CONFIG_COMMON_CLK_XGENE=y CONFIG_COMMON_CLK_PWM=m CONFIG_COMMON_CLK_OXNAS=y CONFIG_COMMON_CLK_RS9_PCIE=m CONFIG_COMMON_CLK_VC5=m CONFIG_COMMON_CLK_VC7=m CONFIG_COMMON_CLK_MMP2_AUDIO=m CONFIG_COMMON_CLK_FIXED_MMIO=y CONFIG_CLK_ACTIONS=y CONFIG_CLK_OWL_S500=y CONFIG_CLK_OWL_S700=y CONFIG_CLK_OWL_S900=y CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y CONFIG_CLK_BAIKAL_T1=y CONFIG_CLK_BT1_CCU_PLL=y CONFIG_CLK_BT1_CCU_DIV=y CONFIG_CLK_BT1_CCU_RST=y CONFIG_CLK_BCM2711_DVP=m CONFIG_CLK_BCM2835=y CONFIG_CLK_BCM_63XX=y CONFIG_CLK_BCM_63XX_GATE=y CONFIG_CLK_BCM_KONA=y CONFIG_COMMON_CLK_IPROC=y CONFIG_CLK_BCM_CYGNUS=y CONFIG_CLK_BCM_HR2=y CONFIG_CLK_BCM_NSP=y CONFIG_CLK_BCM_NS2=y CONFIG_CLK_BCM_SR=y CONFIG_CLK_RASPBERRYPI=m CONFIG_COMMON_CLK_HI3516CV300=m CONFIG_COMMON_CLK_HI3519=m CONFIG_COMMON_CLK_HI3559A=y CONFIG_COMMON_CLK_HI3660=y CONFIG_COMMON_CLK_HI3670=y CONFIG_COMMON_CLK_HI3798CV200=m CONFIG_COMMON_CLK_HI6220=y CONFIG_RESET_HISI=y CONFIG_STUB_CLK_HI6220=y CONFIG_STUB_CLK_HI3660=y CONFIG_COMMON_CLK_BOSTON=y CONFIG_MXC_CLK=m CONFIG_CLK_IMX8MM=m CONFIG_CLK_IMX8MN=m CONFIG_CLK_IMX8MP=m CONFIG_CLK_IMX8MQ=m CONFIG_CLK_IMX8ULP=m CONFIG_CLK_IMX93=m # # Ingenic SoCs drivers # CONFIG_INGENIC_CGU_COMMON=y CONFIG_INGENIC_CGU_JZ4740=y CONFIG_INGENIC_CGU_JZ4725B=y CONFIG_INGENIC_CGU_JZ4760=y CONFIG_INGENIC_CGU_JZ4770=y CONFIG_INGENIC_CGU_JZ4780=y CONFIG_INGENIC_CGU_X1000=y CONFIG_INGENIC_CGU_X1830=y CONFIG_INGENIC_TCU_CLK=y # end of Ingenic SoCs drivers CONFIG_COMMON_CLK_KEYSTONE=m CONFIG_TI_SYSCON_CLK=m # # Clock driver for MediaTek SoC # CONFIG_COMMON_CLK_MEDIATEK=y CONFIG_COMMON_CLK_MT2701=y CONFIG_COMMON_CLK_MT2701_MMSYS=y CONFIG_COMMON_CLK_MT2701_IMGSYS=y CONFIG_COMMON_CLK_MT2701_VDECSYS=y CONFIG_COMMON_CLK_MT2701_HIFSYS=y CONFIG_COMMON_CLK_MT2701_ETHSYS=y CONFIG_COMMON_CLK_MT2701_BDPSYS=y CONFIG_COMMON_CLK_MT2701_AUDSYS=y CONFIG_COMMON_CLK_MT2701_G3DSYS=y CONFIG_COMMON_CLK_MT2712=y CONFIG_COMMON_CLK_MT2712_BDPSYS=y CONFIG_COMMON_CLK_MT2712_IMGSYS=y CONFIG_COMMON_CLK_MT2712_JPGDECSYS=y CONFIG_COMMON_CLK_MT2712_MFGCFG=y CONFIG_COMMON_CLK_MT2712_MMSYS=y CONFIG_COMMON_CLK_MT2712_VDECSYS=y CONFIG_COMMON_CLK_MT2712_VENCSYS=y CONFIG_COMMON_CLK_MT6765=y CONFIG_COMMON_CLK_MT6765_AUDIOSYS=y CONFIG_COMMON_CLK_MT6765_CAMSYS=y CONFIG_COMMON_CLK_MT6765_GCESYS=y CONFIG_COMMON_CLK_MT6765_MMSYS=y CONFIG_COMMON_CLK_MT6765_IMGSYS=y CONFIG_COMMON_CLK_MT6765_VCODECSYS=y CONFIG_COMMON_CLK_MT6765_MFGSYS=y CONFIG_COMMON_CLK_MT6765_MIPI0ASYS=y CONFIG_COMMON_CLK_MT6765_MIPI0BSYS=y CONFIG_COMMON_CLK_MT6765_MIPI1ASYS=y CONFIG_COMMON_CLK_MT6765_MIPI1BSYS=y CONFIG_COMMON_CLK_MT6765_MIPI2ASYS=y CONFIG_COMMON_CLK_MT6765_MIPI2BSYS=y CONFIG_COMMON_CLK_MT6779=m CONFIG_COMMON_CLK_MT6779_MMSYS=m CONFIG_COMMON_CLK_MT6779_IMGSYS=m CONFIG_COMMON_CLK_MT6779_IPESYS=m CONFIG_COMMON_CLK_MT6779_CAMSYS=m CONFIG_COMMON_CLK_MT6779_VDECSYS=m CONFIG_COMMON_CLK_MT6779_VENCSYS=m CONFIG_COMMON_CLK_MT6779_MFGCFG=m CONFIG_COMMON_CLK_MT6779_AUDSYS=m CONFIG_COMMON_CLK_MT6795=m CONFIG_COMMON_CLK_MT6795_MFGCFG=m CONFIG_COMMON_CLK_MT6795_MMSYS=m CONFIG_COMMON_CLK_MT6795_VDECSYS=m CONFIG_COMMON_CLK_MT6795_VENCSYS=m CONFIG_COMMON_CLK_MT6797=y CONFIG_COMMON_CLK_MT6797_MMSYS=y CONFIG_COMMON_CLK_MT6797_IMGSYS=y CONFIG_COMMON_CLK_MT6797_VDECSYS=y CONFIG_COMMON_CLK_MT6797_VENCSYS=y CONFIG_COMMON_CLK_MT7622=y CONFIG_COMMON_CLK_MT7622_ETHSYS=y CONFIG_COMMON_CLK_MT7622_HIFSYS=y CONFIG_COMMON_CLK_MT7622_AUDSYS=y CONFIG_COMMON_CLK_MT7629=y CONFIG_COMMON_CLK_MT7629_ETHSYS=y CONFIG_COMMON_CLK_MT7629_HIFSYS=y CONFIG_COMMON_CLK_MT7986=y CONFIG_COMMON_CLK_MT7986_ETHSYS=y CONFIG_COMMON_CLK_MT8135=y CONFIG_COMMON_CLK_MT8167=y CONFIG_COMMON_CLK_MT8167_AUDSYS=y CONFIG_COMMON_CLK_MT8167_IMGSYS=y CONFIG_COMMON_CLK_MT8167_MFGCFG=y CONFIG_COMMON_CLK_MT8167_MMSYS=y CONFIG_COMMON_CLK_MT8167_VDECSYS=y CONFIG_COMMON_CLK_MT8173=y CONFIG_COMMON_CLK_MT8173_MMSYS=y CONFIG_COMMON_CLK_MT8183=y CONFIG_COMMON_CLK_MT8183_AUDIOSYS=y CONFIG_COMMON_CLK_MT8183_CAMSYS=y CONFIG_COMMON_CLK_MT8183_IMGSYS=y CONFIG_COMMON_CLK_MT8183_IPU_CORE0=y CONFIG_COMMON_CLK_MT8183_IPU_CORE1=y CONFIG_COMMON_CLK_MT8183_IPU_ADL=y CONFIG_COMMON_CLK_MT8183_IPU_CONN=y CONFIG_COMMON_CLK_MT8183_MFGCFG=y CONFIG_COMMON_CLK_MT8183_MMSYS=y CONFIG_COMMON_CLK_MT8183_VDECSYS=y CONFIG_COMMON_CLK_MT8183_VENCSYS=y CONFIG_COMMON_CLK_MT8186=y CONFIG_COMMON_CLK_MT8192=y CONFIG_COMMON_CLK_MT8192_AUDSYS=y CONFIG_COMMON_CLK_MT8192_CAMSYS=y CONFIG_COMMON_CLK_MT8192_IMGSYS=y CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP=y CONFIG_COMMON_CLK_MT8192_IPESYS=y CONFIG_COMMON_CLK_MT8192_MDPSYS=y CONFIG_COMMON_CLK_MT8192_MFGCFG=y CONFIG_COMMON_CLK_MT8192_MMSYS=y CONFIG_COMMON_CLK_MT8192_MSDC=y CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y CONFIG_COMMON_CLK_MT8192_VDECSYS=y CONFIG_COMMON_CLK_MT8192_VENCSYS=y CONFIG_COMMON_CLK_MT8195=y CONFIG_COMMON_CLK_MT8365=m CONFIG_COMMON_CLK_MT8365_APU=m CONFIG_COMMON_CLK_MT8365_CAM=m CONFIG_COMMON_CLK_MT8365_MFG=m CONFIG_COMMON_CLK_MT8365_MMSYS=m CONFIG_COMMON_CLK_MT8365_VDEC=m CONFIG_COMMON_CLK_MT8365_VENC=m CONFIG_COMMON_CLK_MT8516=y CONFIG_COMMON_CLK_MT8516_AUDSYS=y # end of Clock driver for MediaTek SoC # # Clock support for Amlogic platforms # # end of Clock support for Amlogic platforms CONFIG_MSTAR_MSC313_MPLL=y CONFIG_MCHP_CLK_MPFS=y CONFIG_COMMON_CLK_PISTACHIO=y CONFIG_QCOM_GDSC=y CONFIG_QCOM_RPMCC=y CONFIG_COMMON_CLK_QCOM=m CONFIG_QCOM_A53PLL=m CONFIG_QCOM_A7PLL=m CONFIG_QCOM_CLK_APCS_MSM8916=m CONFIG_QCOM_CLK_APCS_SDX55=m CONFIG_QCOM_CLK_SMD_RPM=m CONFIG_QCOM_CLK_RPMH=m CONFIG_APQ_GCC_8084=m CONFIG_APQ_MMCC_8084=m CONFIG_IPQ_APSS_PLL=m CONFIG_IPQ_APSS_6018=m CONFIG_IPQ_GCC_4019=m CONFIG_IPQ_GCC_6018=m CONFIG_IPQ_GCC_806X=m CONFIG_IPQ_LCC_806X=m CONFIG_IPQ_GCC_8074=m CONFIG_MSM_GCC_8660=m CONFIG_MSM_GCC_8909=m CONFIG_MSM_GCC_8916=m CONFIG_MSM_GCC_8939=m CONFIG_MSM_GCC_8960=m CONFIG_MSM_LCC_8960=m CONFIG_MDM_GCC_9607=m CONFIG_MDM_GCC_9615=m CONFIG_MDM_LCC_9615=m CONFIG_MSM_MMCC_8960=m CONFIG_MSM_GCC_8953=m CONFIG_MSM_GCC_8974=m CONFIG_MSM_MMCC_8974=m CONFIG_MSM_GCC_8976=m CONFIG_MSM_MMCC_8994=m CONFIG_MSM_GCC_8994=m CONFIG_MSM_GCC_8996=m CONFIG_MSM_MMCC_8996=m CONFIG_MSM_GCC_8998=m CONFIG_MSM_GPUCC_8998=m CONFIG_MSM_MMCC_8998=m CONFIG_QCM_GCC_2290=m CONFIG_QCM_DISPCC_2290=m CONFIG_QCS_GCC_404=m CONFIG_SC_CAMCC_7180=m CONFIG_SC_CAMCC_7280=m CONFIG_SC_DISPCC_7180=m CONFIG_SC_DISPCC_7280=m CONFIG_SC_GCC_7180=m CONFIG_SC_GCC_7280=m CONFIG_SC_GCC_8180X=m CONFIG_SC_GCC_8280XP=m CONFIG_SC_GPUCC_7180=m CONFIG_SC_GPUCC_7280=m CONFIG_SC_GPUCC_8280XP=m CONFIG_SC_LPASSCC_7280=m CONFIG_SC_LPASS_CORECC_7180=m CONFIG_SC_LPASS_CORECC_7280=m CONFIG_SC_MSS_7180=m CONFIG_SC_VIDEOCC_7180=m CONFIG_SC_VIDEOCC_7280=m CONFIG_SDM_CAMCC_845=m CONFIG_SDM_GCC_660=m CONFIG_SDM_MMCC_660=m CONFIG_SDM_GPUCC_660=m CONFIG_QCS_TURING_404=m CONFIG_QCS_Q6SSTOP_404=m CONFIG_SDM_GCC_845=m CONFIG_SDM_GPUCC_845=m CONFIG_SDM_VIDEOCC_845=m CONFIG_SDM_DISPCC_845=m CONFIG_SDM_LPASSCC_845=m CONFIG_SDX_GCC_55=m CONFIG_SDX_GCC_65=m CONFIG_SM_CAMCC_8250=m CONFIG_SM_CAMCC_8450=m CONFIG_SM_DISPCC_6115=m CONFIG_SM_DISPCC_6125=m CONFIG_SM_DISPCC_8250=m CONFIG_SM_DISPCC_6350=m CONFIG_SM_DISPCC_8450=m CONFIG_SM_GCC_6115=m CONFIG_SM_GCC_6125=m CONFIG_SM_GCC_6350=m CONFIG_SM_GCC_6375=m CONFIG_SM_GCC_8150=m CONFIG_SM_GCC_8250=m CONFIG_SM_GCC_8350=m CONFIG_SM_GCC_8450=m CONFIG_SM_GPUCC_6350=m CONFIG_SM_GPUCC_8150=m CONFIG_SM_GPUCC_8250=m CONFIG_SM_GPUCC_8350=m CONFIG_SM_VIDEOCC_8150=m CONFIG_SM_VIDEOCC_8250=m CONFIG_SPMI_PMIC_CLKDIV=m CONFIG_QCOM_HFPLL=m CONFIG_KPSS_XCC=m CONFIG_CLK_GFM_LPASS_SM8250=m CONFIG_CLK_MT7621=y CONFIG_CLK_RENESAS=y CONFIG_CLK_EMEV2=y CONFIG_CLK_RZA1=y CONFIG_CLK_R7S9210=y CONFIG_CLK_R8A73A4=y CONFIG_CLK_R8A7740=y CONFIG_CLK_R8A7742=y CONFIG_CLK_R8A7743=y CONFIG_CLK_R8A7745=y CONFIG_CLK_R8A77470=y CONFIG_CLK_R8A774A1=y CONFIG_CLK_R8A774B1=y CONFIG_CLK_R8A774C0=y CONFIG_CLK_R8A774E1=y CONFIG_CLK_R8A7778=y CONFIG_CLK_R8A7779=y CONFIG_CLK_R8A7790=y CONFIG_CLK_R8A7791=y CONFIG_CLK_R8A7792=y CONFIG_CLK_R8A7794=y CONFIG_CLK_R8A7795=y CONFIG_CLK_R8A77960=y CONFIG_CLK_R8A77961=y CONFIG_CLK_R8A77965=y CONFIG_CLK_R8A77970=y CONFIG_CLK_R8A77980=y CONFIG_CLK_R8A77990=y CONFIG_CLK_R8A77995=y CONFIG_CLK_R8A779A0=y CONFIG_CLK_R8A779F0=y CONFIG_CLK_R8A779G0=y CONFIG_CLK_R9A06G032=y CONFIG_CLK_R9A07G043=y CONFIG_CLK_R9A07G044=y CONFIG_CLK_R9A07G054=y CONFIG_CLK_R9A09G011=y CONFIG_CLK_SH73A0=y CONFIG_CLK_RCAR_CPG_LIB=y CONFIG_CLK_RCAR_GEN2_CPG=y CONFIG_CLK_RCAR_GEN3_CPG=y CONFIG_CLK_RCAR_GEN4_CPG=y CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y CONFIG_CLK_RZG2L=y CONFIG_CLK_RENESAS_CPG_MSSR=y CONFIG_CLK_RENESAS_CPG_MSTP=y CONFIG_CLK_RENESAS_DIV6=y CONFIG_COMMON_CLK_SAMSUNG=y CONFIG_S3C64XX_COMMON_CLK=y CONFIG_S5PV210_COMMON_CLK=y CONFIG_EXYNOS_3250_COMMON_CLK=y CONFIG_EXYNOS_4_COMMON_CLK=y CONFIG_EXYNOS_5250_COMMON_CLK=y CONFIG_EXYNOS_5260_COMMON_CLK=y CONFIG_EXYNOS_5410_COMMON_CLK=y CONFIG_EXYNOS_5420_COMMON_CLK=y CONFIG_EXYNOS_ARM64_COMMON_CLK=y CONFIG_EXYNOS_AUDSS_CLK_CON=m CONFIG_EXYNOS_CLKOUT=m CONFIG_S3C2410_COMMON_CLK=y CONFIG_S3C2412_COMMON_CLK=y CONFIG_S3C2443_COMMON_CLK=y CONFIG_TESLA_FSD_COMMON_CLK=y CONFIG_CLK_SIFIVE=y CONFIG_CLK_SIFIVE_PRCI=y CONFIG_CLK_INTEL_SOCFPGA=y CONFIG_CLK_INTEL_SOCFPGA32=y CONFIG_CLK_INTEL_SOCFPGA64=y CONFIG_SPRD_COMMON_CLK=m CONFIG_SPRD_SC9860_CLK=m CONFIG_SPRD_SC9863A_CLK=m CONFIG_SPRD_UMS512_CLK=m CONFIG_CLK_STARFIVE_JH7100=y CONFIG_CLK_STARFIVE_JH7100_AUDIO=m CONFIG_CLK_SUNXI=y CONFIG_CLK_SUNXI_CLOCKS=y CONFIG_CLK_SUNXI_PRCM_SUN6I=y CONFIG_CLK_SUNXI_PRCM_SUN8I=y CONFIG_CLK_SUNXI_PRCM_SUN9I=y CONFIG_SUNXI_CCU=m CONFIG_SUNIV_F1C100S_CCU=m CONFIG_SUN20I_D1_CCU=m CONFIG_SUN20I_D1_R_CCU=m CONFIG_SUN50I_A64_CCU=m CONFIG_SUN50I_A100_CCU=m CONFIG_SUN50I_A100_R_CCU=m CONFIG_SUN50I_H6_CCU=m CONFIG_SUN50I_H616_CCU=m CONFIG_SUN50I_H6_R_CCU=m CONFIG_SUN4I_A10_CCU=m CONFIG_SUN6I_A31_CCU=m CONFIG_SUN6I_RTC_CCU=m CONFIG_SUN8I_A23_CCU=m CONFIG_SUN8I_A33_CCU=m CONFIG_SUN8I_A83T_CCU=m CONFIG_SUN8I_H3_CCU=m CONFIG_SUN8I_V3S_CCU=m CONFIG_SUN8I_DE2_CCU=m CONFIG_SUN8I_R40_CCU=m CONFIG_SUN9I_A80_CCU=m CONFIG_SUN8I_R_CCU=m CONFIG_COMMON_CLK_TI_ADPLL=m CONFIG_CLK_UNIPHIER=y CONFIG_COMMON_CLK_VISCONTI=y CONFIG_CLK_LGM_CGU=y CONFIG_XILINX_VCU=m CONFIG_COMMON_CLK_XLNX_CLKWZRD=m CONFIG_COMMON_CLK_ZYNQMP=y CONFIG_CLK_KUNIT_TEST=m CONFIG_CLK_GATE_KUNIT_TEST=m CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_OMAP=m CONFIG_HWSPINLOCK_QCOM=m CONFIG_HWSPINLOCK_SPRD=m CONFIG_HWSPINLOCK_STM32=m CONFIG_HWSPINLOCK_SUN6I=m CONFIG_HSEM_U8500=m CONFIG_MAILBOX=y CONFIG_IMX_MBOX=m CONFIG_PLATFORM_MHU=m CONFIG_ARMADA_37XX_RWTM_MBOX=m CONFIG_ROCKCHIP_MBOX=y CONFIG_PCC=y CONFIG_ALTERA_MBOX=m CONFIG_HI3660_MBOX=m CONFIG_HI6220_MBOX=m CONFIG_MAILBOX_TEST=m CONFIG_POLARFIRE_SOC_MAILBOX=m CONFIG_QCOM_APCS_IPC=m CONFIG_BCM_PDC_MBOX=m CONFIG_STM32_IPCC=m CONFIG_MTK_ADSP_MBOX=m CONFIG_MTK_CMDQ_MBOX=m CONFIG_SUN6I_MSGBOX=m CONFIG_SPRD_MBOX=m CONFIG_QCOM_IPCC=m CONFIG_IOMMU_IOVA=y CONFIG_IOASID=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # CONFIG_IOMMU_IO_PGTABLE=y CONFIG_IOMMU_IO_PGTABLE_LPAE=y CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST=y CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST=y CONFIG_IOMMU_IO_PGTABLE_DART=y # end of Generic IOMMU Pagetable Support CONFIG_IOMMU_DEBUGFS=y # CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set CONFIG_IOMMU_DEFAULT_DMA_LAZY=y # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set CONFIG_OF_IOMMU=y CONFIG_IOMMU_DMA=y CONFIG_DMAR_TABLE=y CONFIG_DMAR_PERF=y CONFIG_DMAR_DEBUG=y CONFIG_INTEL_IOMMU=y CONFIG_INTEL_IOMMU_DEBUGFS=y CONFIG_INTEL_IOMMU_DEFAULT_ON=y CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON=y CONFIG_OMAP_IOMMU=y CONFIG_OMAP_IOMMU_DEBUG=y CONFIG_ROCKCHIP_IOMMU=y CONFIG_SUN50I_IOMMU=y CONFIG_EXYNOS_IOMMU=y CONFIG_EXYNOS_IOMMU_DEBUG=y CONFIG_IPMMU_VMSA=y CONFIG_APPLE_DART=m CONFIG_ARM_SMMU=m CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y CONFIG_S390_CCW_IOMMU=y CONFIG_S390_AP_IOMMU=y CONFIG_MTK_IOMMU=m CONFIG_QCOM_IOMMU=y CONFIG_SPRD_IOMMU=m # # Remoteproc drivers # CONFIG_REMOTEPROC=y CONFIG_REMOTEPROC_CDEV=y CONFIG_INGENIC_VPU_RPROC=m CONFIG_MTK_SCP=m CONFIG_MESON_MX_AO_ARC_REMOTEPROC=m CONFIG_RCAR_REMOTEPROC=m # end of Remoteproc drivers # # Rpmsg drivers # CONFIG_RPMSG=m CONFIG_RPMSG_CHAR=m CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_NS=m CONFIG_RPMSG_MTK_SCP=m CONFIG_RPMSG_QCOM_GLINK=m CONFIG_RPMSG_QCOM_GLINK_RPM=m CONFIG_RPMSG_QCOM_GLINK_SMEM=m CONFIG_RPMSG_QCOM_SMD=m CONFIG_RPMSG_VIRTIO=m # end of Rpmsg drivers CONFIG_SOUNDWIRE=m # # SoundWire Devices # # # SOC (System On Chip) specific Drivers # CONFIG_OWL_PM_DOMAINS_HELPER=y CONFIG_OWL_PM_DOMAINS=y # # Amlogic SoC drivers # CONFIG_MESON_CANVAS=m CONFIG_MESON_CLK_MEASURE=m CONFIG_MESON_GX_SOCINFO=y CONFIG_MESON_GX_PM_DOMAINS=m CONFIG_MESON_EE_PM_DOMAINS=m CONFIG_MESON_MX_SOCINFO=y # end of Amlogic SoC drivers # # Apple SoC drivers # CONFIG_APPLE_PMGR_PWRSTATE=y CONFIG_APPLE_RTKIT=m CONFIG_APPLE_SART=m # end of Apple SoC drivers # # ASPEED SoC drivers # CONFIG_ASPEED_LPC_CTRL=m CONFIG_ASPEED_LPC_SNOOP=m CONFIG_ASPEED_UART_ROUTING=m CONFIG_ASPEED_P2A_CTRL=m CONFIG_ASPEED_SOCINFO=y # end of ASPEED SoC drivers CONFIG_AT91_SOC_ID=y CONFIG_AT91_SOC_SFR=m # # Broadcom SoC drivers # CONFIG_BCM2835_POWER=y CONFIG_SOC_BCM63XX=y CONFIG_SOC_BRCMSTB=y CONFIG_BCM63XX_POWER=y CONFIG_BCM_PMB=y # end of Broadcom SoC drivers # # NXP/Freescale QorIQ SoC drivers # CONFIG_QUICC_ENGINE=y CONFIG_UCC_SLOW=y CONFIG_UCC_FAST=y CONFIG_UCC=y CONFIG_QE_TDM=y CONFIG_FSL_GUTS=y CONFIG_DPAA2_CONSOLE=m # end of NXP/Freescale QorIQ SoC drivers # # fujitsu SoC drivers # # end of fujitsu SoC drivers # # i.MX SoC drivers # CONFIG_IMX_GPCV2_PM_DOMAINS=y CONFIG_SOC_IMX8M=y CONFIG_SOC_IMX9=m # end of i.MX SoC drivers # # IXP4xx SoC drivers # CONFIG_IXP4XX_QMGR=m CONFIG_IXP4XX_NPE=m # end of IXP4xx SoC drivers # # Enable LiteX SoC Builder specific drivers # CONFIG_LITEX=y CONFIG_LITEX_SOC_CONTROLLER=m # end of Enable LiteX SoC Builder specific drivers # # MediaTek SoC drivers # CONFIG_MTK_CMDQ=m CONFIG_MTK_DEVAPC=m CONFIG_MTK_INFRACFG=y CONFIG_MTK_PMIC_WRAP=m CONFIG_MTK_SCPSYS=y CONFIG_MTK_SCPSYS_PM_DOMAINS=y CONFIG_MTK_MMSYS=y CONFIG_MTK_SVS=m # end of MediaTek SoC drivers CONFIG_POLARFIRE_SOC_SYS_CTRL=m # # Qualcomm SoC drivers # CONFIG_QCOM_AOSS_QMP=m CONFIG_QCOM_COMMAND_DB=m CONFIG_QCOM_GENI_SE=m CONFIG_QCOM_GSBI=m CONFIG_QCOM_LLCC=m CONFIG_QCOM_PDR_HELPERS=m CONFIG_QCOM_QMI_HELPERS=m CONFIG_QCOM_RPMH=m CONFIG_QCOM_RPMHPD=m CONFIG_QCOM_RPMPD=m CONFIG_QCOM_SMEM=m CONFIG_QCOM_SMD_RPM=m CONFIG_QCOM_SMEM_STATE=y CONFIG_QCOM_SMP2P=m CONFIG_QCOM_SMSM=m CONFIG_QCOM_SOCINFO=m CONFIG_QCOM_SPM=m CONFIG_QCOM_STATS=m CONFIG_QCOM_WCNSS_CTRL=m CONFIG_QCOM_APR=m CONFIG_QCOM_ICC_BWMON=m # end of Qualcomm SoC drivers CONFIG_SOC_RENESAS=y CONFIG_RST_RCAR=y CONFIG_SYSC_RCAR=y CONFIG_SYSC_RCAR_GEN4=y CONFIG_SYSC_R8A77995=y CONFIG_SYSC_R8A7794=y CONFIG_SYSC_R8A77990=y CONFIG_SYSC_R8A7779=y CONFIG_SYSC_R8A7790=y CONFIG_SYSC_R8A7795=y CONFIG_SYSC_R8A7791=y CONFIG_SYSC_R8A77965=y CONFIG_SYSC_R8A77960=y CONFIG_SYSC_R8A77961=y CONFIG_SYSC_R8A779F0=y CONFIG_SYSC_R8A7792=y CONFIG_SYSC_R8A77980=y CONFIG_SYSC_R8A77970=y CONFIG_SYSC_R8A779A0=y CONFIG_SYSC_R8A779G0=y CONFIG_SYSC_RMOBILE=y CONFIG_SYSC_R8A77470=y CONFIG_SYSC_R8A7745=y CONFIG_SYSC_R8A7742=y CONFIG_SYSC_R8A7743=y CONFIG_SYSC_R8A774C0=y CONFIG_SYSC_R8A774E1=y CONFIG_SYSC_R8A774A1=y CONFIG_SYSC_R8A774B1=y CONFIG_ROCKCHIP_GRF=y CONFIG_ROCKCHIP_IODOMAIN=m CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ROCKCHIP_DTPM=m CONFIG_SOC_SAMSUNG=y CONFIG_EXYNOS_ASV_ARM=y CONFIG_EXYNOS_CHIPID=m CONFIG_EXYNOS_USI=m CONFIG_EXYNOS_PM_DOMAINS=y CONFIG_EXYNOS_REGULATOR_COUPLER=y CONFIG_SUNXI_SRAM=y CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER=y CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER=y CONFIG_SOC_TI=y CONFIG_UX500_SOC_ID=y # # Xilinx SoC drivers # # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers CONFIG_PM_DEVFREQ=y # # DEVFREQ Governors # CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m CONFIG_DEVFREQ_GOV_PERFORMANCE=m CONFIG_DEVFREQ_GOV_POWERSAVE=m CONFIG_DEVFREQ_GOV_USERSPACE=m CONFIG_DEVFREQ_GOV_PASSIVE=m # # DEVFREQ Drivers # CONFIG_ARM_EXYNOS_BUS_DEVFREQ=m CONFIG_ARM_IMX_BUS_DEVFREQ=m CONFIG_ARM_TEGRA_DEVFREQ=m CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=m CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m CONFIG_PM_DEVFREQ_EVENT=y CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=m CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU=m CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=m CONFIG_EXTCON=y # # Extcon Device Drivers # CONFIG_EXTCON_ADC_JACK=m CONFIG_EXTCON_FSA9480=m CONFIG_EXTCON_GPIO=m CONFIG_EXTCON_INTEL_INT3496=m CONFIG_EXTCON_MAX14577=m CONFIG_EXTCON_MAX3355=m CONFIG_EXTCON_MAX77693=m CONFIG_EXTCON_PTN5150=m CONFIG_EXTCON_QCOM_SPMI_MISC=m CONFIG_EXTCON_RT8973A=m CONFIG_EXTCON_SM5502=m CONFIG_EXTCON_USB_GPIO=m CONFIG_EXTCON_USBC_CROS_EC=m CONFIG_EXTCON_USBC_TUSB320=m CONFIG_MEMORY=y CONFIG_DDR=y CONFIG_ATMEL_SDRAMC=y CONFIG_ATMEL_EBI=y CONFIG_BRCMSTB_DPFE=m CONFIG_BRCMSTB_MEMC=m CONFIG_BT1_L2_CTL=y CONFIG_TI_AEMIF=m CONFIG_TI_EMIF=m CONFIG_OMAP_GPMC=m CONFIG_OMAP_GPMC_DEBUG=y CONFIG_FPGA_DFL_EMIF=m CONFIG_MVEBU_DEVBUS=y CONFIG_FSL_CORENET_CF=m CONFIG_FSL_IFC=y CONFIG_JZ4780_NEMC=y CONFIG_MTK_SMI=m CONFIG_DA8XX_DDRCTL=y CONFIG_RENESAS_RPCIF=m CONFIG_STM32_FMC2_EBI=m CONFIG_SAMSUNG_MC=y CONFIG_EXYNOS5422_DMC=m CONFIG_EXYNOS_SROM=y CONFIG_TEGRA_MC=y CONFIG_TEGRA20_EMC=m CONFIG_TEGRA30_EMC=m CONFIG_TEGRA124_EMC=m CONFIG_TEGRA210_EMC_TABLE=y CONFIG_TEGRA210_EMC=m CONFIG_IIO=m CONFIG_IIO_BUFFER=y CONFIG_IIO_BUFFER_CB=m CONFIG_IIO_BUFFER_DMA=m CONFIG_IIO_BUFFER_DMAENGINE=m CONFIG_IIO_BUFFER_HW_CONSUMER=m CONFIG_IIO_KFIFO_BUF=m CONFIG_IIO_TRIGGERED_BUFFER=m CONFIG_IIO_CONFIGFS=m CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 CONFIG_IIO_SW_DEVICE=m CONFIG_IIO_SW_TRIGGER=m CONFIG_IIO_TRIGGERED_EVENT=m # # Accelerometers # CONFIG_ADIS16201=m CONFIG_ADIS16209=m CONFIG_ADXL313=m CONFIG_ADXL313_I2C=m CONFIG_ADXL313_SPI=m CONFIG_ADXL355=m CONFIG_ADXL355_I2C=m CONFIG_ADXL355_SPI=m CONFIG_ADXL367=m CONFIG_ADXL367_SPI=m CONFIG_ADXL367_I2C=m CONFIG_ADXL372=m CONFIG_ADXL372_SPI=m CONFIG_ADXL372_I2C=m CONFIG_BMA220=m CONFIG_BMA400=m CONFIG_BMA400_I2C=m CONFIG_BMA400_SPI=m CONFIG_BMC150_ACCEL=m CONFIG_BMC150_ACCEL_I2C=m CONFIG_BMC150_ACCEL_SPI=m CONFIG_BMI088_ACCEL=m CONFIG_BMI088_ACCEL_SPI=m CONFIG_DA280=m CONFIG_DA311=m CONFIG_DMARD06=m CONFIG_DMARD09=m CONFIG_DMARD10=m CONFIG_FXLS8962AF=m CONFIG_FXLS8962AF_I2C=m CONFIG_FXLS8962AF_SPI=m CONFIG_HID_SENSOR_ACCEL_3D=m CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m CONFIG_IIO_ST_ACCEL_3AXIS=m CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m CONFIG_KXSD9=m CONFIG_KXSD9_SPI=m CONFIG_KXSD9_I2C=m CONFIG_KXCJK1013=m CONFIG_MC3230=m CONFIG_MMA7455=m CONFIG_MMA7455_I2C=m CONFIG_MMA7455_SPI=m CONFIG_MMA7660=m CONFIG_MMA8452=m CONFIG_MMA9551_CORE=m CONFIG_MMA9551=m CONFIG_MMA9553=m CONFIG_MSA311=m CONFIG_MXC4005=m CONFIG_MXC6255=m CONFIG_SCA3000=m CONFIG_SCA3300=m CONFIG_STK8312=m CONFIG_STK8BA50=m # end of Accelerometers # # Analog to digital converters # CONFIG_AD_SIGMA_DELTA=m CONFIG_AD7091R5=m CONFIG_AD7124=m CONFIG_AD7192=m CONFIG_AD7266=m CONFIG_AD7280=m CONFIG_AD7291=m CONFIG_AD7292=m CONFIG_AD7298=m CONFIG_AD7476=m CONFIG_AD7606=m CONFIG_AD7606_IFACE_PARALLEL=m CONFIG_AD7606_IFACE_SPI=m CONFIG_AD7766=m CONFIG_AD7768_1=m CONFIG_AD7780=m CONFIG_AD7791=m CONFIG_AD7793=m CONFIG_AD7887=m CONFIG_AD7923=m CONFIG_AD7949=m CONFIG_AD799X=m CONFIG_AD9467=m CONFIG_ADI_AXI_ADC=m CONFIG_ASPEED_ADC=m CONFIG_AT91_ADC=m CONFIG_AT91_SAMA5D2_ADC=m CONFIG_AXP20X_ADC=m CONFIG_AXP288_ADC=m CONFIG_BCM_IPROC_ADC=m CONFIG_BERLIN2_ADC=m CONFIG_CC10001_ADC=m CONFIG_CPCAP_ADC=m CONFIG_DA9150_GPADC=m CONFIG_DLN2_ADC=m CONFIG_ENVELOPE_DETECTOR=m CONFIG_EXYNOS_ADC=m CONFIG_MXS_LRADC_ADC=m CONFIG_FSL_MX25_ADC=m CONFIG_HI8435=m CONFIG_HX711=m CONFIG_INA2XX_ADC=m CONFIG_INGENIC_ADC=m CONFIG_IMX7D_ADC=m CONFIG_IMX8QXP_ADC=m CONFIG_LPC18XX_ADC=m CONFIG_LPC32XX_ADC=m CONFIG_LTC2471=m CONFIG_LTC2485=m CONFIG_LTC2496=m CONFIG_LTC2497=m CONFIG_MAX1027=m CONFIG_MAX11100=m CONFIG_MAX1118=m CONFIG_MAX11205=m CONFIG_MAX1241=m CONFIG_MAX1363=m CONFIG_MAX9611=m CONFIG_MCP320X=m CONFIG_MCP3422=m CONFIG_MCP3911=m CONFIG_MEDIATEK_MT6360_ADC=m CONFIG_MEDIATEK_MT6577_AUXADC=m CONFIG_MEN_Z188_ADC=m CONFIG_MESON_SARADC=m CONFIG_MP2629_ADC=m CONFIG_NAU7802=m CONFIG_NPCM_ADC=m CONFIG_QCOM_VADC_COMMON=m CONFIG_QCOM_PM8XXX_XOADC=m CONFIG_QCOM_SPMI_RRADC=m CONFIG_QCOM_SPMI_IADC=m CONFIG_QCOM_SPMI_VADC=m CONFIG_QCOM_SPMI_ADC5=m CONFIG_RCAR_GYRO_ADC=m CONFIG_RN5T618_ADC=m CONFIG_ROCKCHIP_SARADC=m CONFIG_RICHTEK_RTQ6056=m CONFIG_RZG2L_ADC=m CONFIG_SC27XX_ADC=m CONFIG_SPEAR_ADC=m CONFIG_SD_ADC_MODULATOR=m CONFIG_STM32_ADC_CORE=m CONFIG_STM32_ADC=m CONFIG_STM32_DFSDM_CORE=m CONFIG_STM32_DFSDM_ADC=m CONFIG_STMPE_ADC=m CONFIG_SUN4I_GPADC=m CONFIG_TI_ADC081C=m CONFIG_TI_ADC0832=m CONFIG_TI_ADC084S021=m CONFIG_TI_ADC12138=m CONFIG_TI_ADC108S102=m CONFIG_TI_ADC128S052=m CONFIG_TI_ADC161S626=m CONFIG_TI_ADS1015=m CONFIG_TI_ADS7950=m CONFIG_TI_ADS8344=m CONFIG_TI_ADS8688=m CONFIG_TI_ADS124S08=m CONFIG_TI_ADS131E08=m CONFIG_TI_AM335X_ADC=m CONFIG_TI_TLC4541=m CONFIG_TI_TSC2046=m CONFIG_VF610_ADC=m CONFIG_VIPERBOARD_ADC=m CONFIG_XILINX_XADC=m CONFIG_XILINX_AMS=m # end of Analog to digital converters # # Analog to digital and digital to analog converters # CONFIG_AD74413R=m # end of Analog to digital and digital to analog converters # # Analog Front Ends # CONFIG_IIO_RESCALE=m # end of Analog Front Ends # # Amplifiers # CONFIG_AD8366=m CONFIG_ADA4250=m CONFIG_HMC425=m # end of Amplifiers # # Capacitance to digital converters # CONFIG_AD7150=m CONFIG_AD7746=m # end of Capacitance to digital converters # # Chemical Sensors # CONFIG_ATLAS_PH_SENSOR=m CONFIG_ATLAS_EZO_SENSOR=m CONFIG_BME680=m CONFIG_BME680_I2C=m CONFIG_BME680_SPI=m CONFIG_CCS811=m CONFIG_IAQCORE=m CONFIG_PMS7003=m CONFIG_SCD30_CORE=m CONFIG_SCD30_I2C=m CONFIG_SCD30_SERIAL=m CONFIG_SCD4X=m CONFIG_SENSIRION_SGP30=m CONFIG_SENSIRION_SGP40=m CONFIG_SPS30=m CONFIG_SPS30_I2C=m CONFIG_SPS30_SERIAL=m CONFIG_SENSEAIR_SUNRISE_CO2=m CONFIG_VZ89X=m # end of Chemical Sensors CONFIG_IIO_CROS_EC_SENSORS_CORE=m CONFIG_IIO_CROS_EC_SENSORS=m CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m # # Hid Sensor IIO Common # CONFIG_HID_SENSOR_IIO_COMMON=m CONFIG_HID_SENSOR_IIO_TRIGGER=m # end of Hid Sensor IIO Common CONFIG_IIO_MS_SENSORS_I2C=m # # IIO SCMI Sensors # CONFIG_IIO_SCMI=m # end of IIO SCMI Sensors # # SSP Sensor Common # CONFIG_IIO_SSP_SENSORS_COMMONS=m CONFIG_IIO_SSP_SENSORHUB=m # end of SSP Sensor Common CONFIG_IIO_ST_SENSORS_I2C=m CONFIG_IIO_ST_SENSORS_SPI=m CONFIG_IIO_ST_SENSORS_CORE=m # # Digital to analog converters # CONFIG_AD3552R=m CONFIG_AD5064=m CONFIG_AD5360=m CONFIG_AD5380=m CONFIG_AD5421=m CONFIG_AD5446=m CONFIG_AD5449=m CONFIG_AD5592R_BASE=m CONFIG_AD5592R=m CONFIG_AD5593R=m CONFIG_AD5504=m CONFIG_AD5624R_SPI=m CONFIG_LTC2688=m CONFIG_AD5686=m CONFIG_AD5686_SPI=m CONFIG_AD5696_I2C=m CONFIG_AD5755=m CONFIG_AD5758=m CONFIG_AD5761=m CONFIG_AD5764=m CONFIG_AD5766=m CONFIG_AD5770R=m CONFIG_AD5791=m CONFIG_AD7293=m CONFIG_AD7303=m CONFIG_AD8801=m CONFIG_DPOT_DAC=m CONFIG_DS4424=m CONFIG_LPC18XX_DAC=m CONFIG_LTC1660=m CONFIG_LTC2632=m CONFIG_M62332=m CONFIG_MAX517=m CONFIG_MAX5821=m CONFIG_MCP4725=m CONFIG_MCP4922=m CONFIG_STM32_DAC=m CONFIG_STM32_DAC_CORE=m CONFIG_TI_DAC082S085=m CONFIG_TI_DAC5571=m CONFIG_TI_DAC7311=m CONFIG_TI_DAC7612=m CONFIG_VF610_DAC=m # end of Digital to analog converters # # IIO dummy driver # CONFIG_IIO_DUMMY_EVGEN=m CONFIG_IIO_SIMPLE_DUMMY=m CONFIG_IIO_SIMPLE_DUMMY_EVENTS=y CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y # end of IIO dummy driver # # Filters # CONFIG_ADMV8818=m # end of Filters # # Frequency Synthesizers DDS/PLL # # # Clock Generator/Distribution # CONFIG_AD9523=m # end of Clock Generator/Distribution # # Phase-Locked Loop (PLL) frequency synthesizers # CONFIG_ADF4350=m CONFIG_ADF4371=m CONFIG_ADMV1013=m CONFIG_ADMV1014=m CONFIG_ADMV4420=m CONFIG_ADRF6780=m # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL # # Digital gyroscope sensors # CONFIG_ADIS16080=m CONFIG_ADIS16130=m CONFIG_ADIS16136=m CONFIG_ADIS16260=m CONFIG_ADXRS290=m CONFIG_ADXRS450=m CONFIG_BMG160=m CONFIG_BMG160_I2C=m CONFIG_BMG160_SPI=m CONFIG_FXAS21002C=m CONFIG_FXAS21002C_I2C=m CONFIG_FXAS21002C_SPI=m CONFIG_HID_SENSOR_GYRO_3D=m CONFIG_MPU3050=m CONFIG_MPU3050_I2C=m CONFIG_IIO_ST_GYRO_3AXIS=m CONFIG_IIO_ST_GYRO_I2C_3AXIS=m CONFIG_IIO_ST_GYRO_SPI_3AXIS=m CONFIG_ITG3200=m # end of Digital gyroscope sensors # # Health Sensors # # # Heart Rate Monitors # CONFIG_AFE4403=m CONFIG_AFE4404=m CONFIG_MAX30100=m CONFIG_MAX30102=m # end of Heart Rate Monitors # end of Health Sensors # # Humidity sensors # CONFIG_AM2315=m CONFIG_DHT11=m CONFIG_HDC100X=m CONFIG_HDC2010=m CONFIG_HID_SENSOR_HUMIDITY=m CONFIG_HTS221=m CONFIG_HTS221_I2C=m CONFIG_HTS221_SPI=m CONFIG_HTU21=m CONFIG_SI7005=m CONFIG_SI7020=m # end of Humidity sensors # # Inertial measurement units # CONFIG_ADIS16400=m CONFIG_ADIS16460=m CONFIG_ADIS16475=m CONFIG_ADIS16480=m CONFIG_BMI160=m CONFIG_BMI160_I2C=m CONFIG_BMI160_SPI=m CONFIG_BOSCH_BNO055=m CONFIG_BOSCH_BNO055_SERIAL=m CONFIG_BOSCH_BNO055_I2C=m CONFIG_FXOS8700=m CONFIG_FXOS8700_I2C=m CONFIG_FXOS8700_SPI=m CONFIG_KMX61=m CONFIG_INV_ICM42600=m CONFIG_INV_ICM42600_I2C=m CONFIG_INV_ICM42600_SPI=m CONFIG_INV_MPU6050_IIO=m CONFIG_INV_MPU6050_I2C=m CONFIG_INV_MPU6050_SPI=m CONFIG_IIO_ST_LSM6DSX=m CONFIG_IIO_ST_LSM6DSX_I2C=m CONFIG_IIO_ST_LSM6DSX_SPI=m CONFIG_IIO_ST_LSM6DSX_I3C=m CONFIG_IIO_ST_LSM9DS0=m CONFIG_IIO_ST_LSM9DS0_I2C=m CONFIG_IIO_ST_LSM9DS0_SPI=m # end of Inertial measurement units CONFIG_IIO_ADIS_LIB=m CONFIG_IIO_ADIS_LIB_BUFFER=y # # Light sensors # CONFIG_ACPI_ALS=m CONFIG_ADJD_S311=m CONFIG_ADUX1020=m CONFIG_AL3010=m CONFIG_AL3320A=m CONFIG_APDS9300=m CONFIG_APDS9960=m CONFIG_AS73211=m CONFIG_BH1750=m CONFIG_BH1780=m CONFIG_CM32181=m CONFIG_CM3232=m CONFIG_CM3323=m CONFIG_CM3605=m CONFIG_CM36651=m CONFIG_IIO_CROS_EC_LIGHT_PROX=m CONFIG_GP2AP002=m CONFIG_GP2AP020A00F=m CONFIG_IQS621_ALS=m CONFIG_SENSORS_ISL29018=m CONFIG_SENSORS_ISL29028=m CONFIG_ISL29125=m CONFIG_HID_SENSOR_ALS=m CONFIG_HID_SENSOR_PROX=m CONFIG_JSA1212=m CONFIG_RPR0521=m CONFIG_SENSORS_LM3533=m CONFIG_LTR501=m CONFIG_LTRF216A=m CONFIG_LV0104CS=m CONFIG_MAX44000=m CONFIG_MAX44009=m CONFIG_NOA1305=m CONFIG_OPT3001=m CONFIG_PA12203001=m CONFIG_SI1133=m CONFIG_SI1145=m CONFIG_STK3310=m CONFIG_ST_UVIS25=m CONFIG_ST_UVIS25_I2C=m CONFIG_ST_UVIS25_SPI=m CONFIG_TCS3414=m CONFIG_TCS3472=m CONFIG_SENSORS_TSL2563=m CONFIG_TSL2583=m CONFIG_TSL2591=m CONFIG_TSL2772=m CONFIG_TSL4531=m CONFIG_US5182D=m CONFIG_VCNL4000=m CONFIG_VCNL4035=m CONFIG_VEML6030=m CONFIG_VEML6070=m CONFIG_VL6180=m CONFIG_ZOPT2201=m # end of Light sensors # # Magnetometer sensors # CONFIG_AK8974=m CONFIG_AK8975=m CONFIG_AK09911=m CONFIG_BMC150_MAGN=m CONFIG_BMC150_MAGN_I2C=m CONFIG_BMC150_MAGN_SPI=m CONFIG_MAG3110=m CONFIG_HID_SENSOR_MAGNETOMETER_3D=m CONFIG_MMC35240=m CONFIG_IIO_ST_MAGN_3AXIS=m CONFIG_IIO_ST_MAGN_I2C_3AXIS=m CONFIG_IIO_ST_MAGN_SPI_3AXIS=m CONFIG_SENSORS_HMC5843=m CONFIG_SENSORS_HMC5843_I2C=m CONFIG_SENSORS_HMC5843_SPI=m CONFIG_SENSORS_RM3100=m CONFIG_SENSORS_RM3100_I2C=m CONFIG_SENSORS_RM3100_SPI=m CONFIG_YAMAHA_YAS530=m # end of Magnetometer sensors # # Multiplexers # CONFIG_IIO_MUX=m # end of Multiplexers # # Inclinometer sensors # CONFIG_HID_SENSOR_INCLINOMETER_3D=m CONFIG_HID_SENSOR_DEVICE_ROTATION=m # end of Inclinometer sensors CONFIG_IIO_RESCALE_KUNIT_TEST=m CONFIG_IIO_FORMAT_KUNIT_TEST=m # # Triggers - standalone # CONFIG_IIO_HRTIMER_TRIGGER=m CONFIG_IIO_INTERRUPT_TRIGGER=m CONFIG_IIO_STM32_LPTIMER_TRIGGER=m CONFIG_IIO_STM32_TIMER_TRIGGER=m CONFIG_IIO_TIGHTLOOP_TRIGGER=m CONFIG_IIO_SYSFS_TRIGGER=m # end of Triggers - standalone # # Linear and angular position sensors # CONFIG_IQS624_POS=m CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m # end of Linear and angular position sensors # # Digital potentiometers # CONFIG_AD5110=m CONFIG_AD5272=m CONFIG_DS1803=m CONFIG_MAX5432=m CONFIG_MAX5481=m CONFIG_MAX5487=m CONFIG_MCP4018=m CONFIG_MCP4131=m CONFIG_MCP4531=m CONFIG_MCP41010=m CONFIG_TPL0102=m # end of Digital potentiometers # # Digital potentiostats # CONFIG_LMP91000=m # end of Digital potentiostats # # Pressure sensors # CONFIG_ABP060MG=m CONFIG_BMP280=m CONFIG_BMP280_I2C=m CONFIG_BMP280_SPI=m CONFIG_IIO_CROS_EC_BARO=m CONFIG_DLHL60D=m CONFIG_DPS310=m CONFIG_HID_SENSOR_PRESS=m CONFIG_HP03=m CONFIG_ICP10100=m CONFIG_MPL115=m CONFIG_MPL115_I2C=m CONFIG_MPL115_SPI=m CONFIG_MPL3115=m CONFIG_MS5611=m CONFIG_MS5611_I2C=m CONFIG_MS5611_SPI=m CONFIG_MS5637=m CONFIG_IIO_ST_PRESS=m CONFIG_IIO_ST_PRESS_I2C=m CONFIG_IIO_ST_PRESS_SPI=m CONFIG_T5403=m CONFIG_HP206C=m CONFIG_ZPA2326=m CONFIG_ZPA2326_I2C=m CONFIG_ZPA2326_SPI=m # end of Pressure sensors # # Lightning sensors # CONFIG_AS3935=m # end of Lightning sensors # # Proximity and distance sensors # CONFIG_CROS_EC_MKBP_PROXIMITY=m CONFIG_ISL29501=m CONFIG_LIDAR_LITE_V2=m CONFIG_MB1232=m CONFIG_PING=m CONFIG_RFD77402=m CONFIG_SRF04=m CONFIG_SX_COMMON=m CONFIG_SX9310=m CONFIG_SX9324=m CONFIG_SX9360=m CONFIG_SX9500=m CONFIG_SRF08=m CONFIG_VCNL3020=m CONFIG_VL53L0X_I2C=m # end of Proximity and distance sensors # # Resolver to digital converters # CONFIG_AD2S90=m CONFIG_AD2S1200=m # end of Resolver to digital converters # # Temperature sensors # CONFIG_IQS620AT_TEMP=m CONFIG_LTC2983=m CONFIG_MAXIM_THERMOCOUPLE=m CONFIG_HID_SENSOR_TEMP=m CONFIG_MLX90614=m CONFIG_MLX90632=m CONFIG_TMP006=m CONFIG_TMP007=m CONFIG_TMP117=m CONFIG_TSYS01=m CONFIG_TSYS02D=m CONFIG_MAX31856=m CONFIG_MAX31865=m # end of Temperature sensors CONFIG_NTB=m CONFIG_NTB_MSI=y CONFIG_NTB_IDT=m CONFIG_NTB_EPF=m CONFIG_NTB_SWITCHTEC=m CONFIG_NTB_PINGPONG=m CONFIG_NTB_TOOL=m CONFIG_NTB_PERF=m CONFIG_NTB_MSI_TEST=m CONFIG_NTB_TRANSPORT=m CONFIG_PWM=y CONFIG_PWM_SYSFS=y CONFIG_PWM_DEBUG=y CONFIG_PWM_ATMEL=m CONFIG_PWM_ATMEL_HLCDC_PWM=m CONFIG_PWM_ATMEL_TCB=m CONFIG_PWM_BCM_IPROC=m CONFIG_PWM_BCM_KONA=m CONFIG_PWM_BCM2835=m CONFIG_PWM_BERLIN=m CONFIG_PWM_BRCMSTB=m CONFIG_PWM_CLK=m CONFIG_PWM_CLPS711X=m CONFIG_PWM_CROS_EC=m CONFIG_PWM_DWC=m CONFIG_PWM_EP93XX=m CONFIG_PWM_FSL_FTM=m CONFIG_PWM_HIBVT=m CONFIG_PWM_IMG=m CONFIG_PWM_IMX1=m CONFIG_PWM_IMX27=m CONFIG_PWM_IMX_TPM=m CONFIG_PWM_INTEL_LGM=m CONFIG_PWM_IQS620A=m CONFIG_PWM_JZ4740=m CONFIG_PWM_KEEMBAY=m CONFIG_PWM_LP3943=m CONFIG_PWM_LPC18XX_SCT=m CONFIG_PWM_LPC32XX=m CONFIG_PWM_LPSS=m CONFIG_PWM_LPSS_PCI=m CONFIG_PWM_LPSS_PLATFORM=m CONFIG_PWM_MESON=m CONFIG_PWM_MTK_DISP=m CONFIG_PWM_MEDIATEK=m CONFIG_PWM_MXS=m CONFIG_PWM_NTXEC=m CONFIG_PWM_OMAP_DMTIMER=m CONFIG_PWM_PCA9685=m CONFIG_PWM_PXA=m CONFIG_PWM_RASPBERRYPI_POE=m CONFIG_PWM_RCAR=m CONFIG_PWM_RENESAS_TPU=m CONFIG_PWM_ROCKCHIP=m CONFIG_PWM_SAMSUNG=m CONFIG_PWM_SIFIVE=m CONFIG_PWM_SL28CPLD=m CONFIG_PWM_SPEAR=m CONFIG_PWM_SPRD=m CONFIG_PWM_STI=m CONFIG_PWM_STM32=m CONFIG_PWM_STM32_LP=m CONFIG_PWM_STMPE=y CONFIG_PWM_SUN4I=m CONFIG_PWM_SUNPLUS=m CONFIG_PWM_TEGRA=m CONFIG_PWM_TIECAP=m CONFIG_PWM_TIEHRPWM=m CONFIG_PWM_VISCONTI=m CONFIG_PWM_VT8500=m CONFIG_PWM_XILINX=m # # IRQ chip support # CONFIG_IRQCHIP=y CONFIG_AL_FIC=y CONFIG_MADERA_IRQ=m CONFIG_JCORE_AIC=y CONFIG_RENESAS_INTC_IRQPIN=y CONFIG_RENESAS_IRQC=y CONFIG_RENESAS_RZA1_IRQC=y CONFIG_RENESAS_RZG2L_IRQC=y CONFIG_SL28CPLD_INTC=y CONFIG_TS4800_IRQ=m CONFIG_XILINX_INTC=y CONFIG_INGENIC_TCU_IRQ=y CONFIG_IRQ_UNIPHIER_AIDET=y CONFIG_MESON_IRQ_GPIO=m CONFIG_IMX_IRQSTEER=y CONFIG_IMX_INTMUX=y CONFIG_IMX_MU_MSI=m CONFIG_EXYNOS_IRQ_COMBINER=y CONFIG_MST_IRQ=y CONFIG_MCHP_EIC=y CONFIG_SUNPLUS_SP7021_INTC=y # end of IRQ chip support CONFIG_IPACK_BUS=m CONFIG_BOARD_TPCI200=m CONFIG_SERIAL_IPOCTAL=m CONFIG_RESET_CONTROLLER=y CONFIG_RESET_A10SR=m CONFIG_RESET_ATH79=y CONFIG_RESET_AXS10X=y CONFIG_RESET_BCM6345=y CONFIG_RESET_BERLIN=m CONFIG_RESET_BRCMSTB=m CONFIG_RESET_BRCMSTB_RESCAL=m CONFIG_RESET_HSDK=y CONFIG_RESET_IMX7=m CONFIG_RESET_INTEL_GW=y CONFIG_RESET_K210=y CONFIG_RESET_LANTIQ=y CONFIG_RESET_LPC18XX=y CONFIG_RESET_MCHP_SPARX5=y CONFIG_RESET_MESON=m CONFIG_RESET_MESON_AUDIO_ARB=m CONFIG_RESET_NPCM=y CONFIG_RESET_PISTACHIO=y CONFIG_RESET_POLARFIRE_SOC=y CONFIG_RESET_QCOM_AOSS=m CONFIG_RESET_QCOM_PDC=m CONFIG_RESET_RASPBERRYPI=m CONFIG_RESET_RZG2L_USBPHY_CTRL=m CONFIG_RESET_SCMI=m CONFIG_RESET_SIMPLE=y CONFIG_RESET_SOCFPGA=y CONFIG_RESET_STARFIVE_JH7100=y CONFIG_RESET_SUNPLUS=y CONFIG_RESET_SUNXI=y CONFIG_RESET_TI_SCI=m CONFIG_RESET_TI_SYSCON=m CONFIG_RESET_TI_TPS380X=m CONFIG_RESET_TN48M_CPLD=m CONFIG_RESET_UNIPHIER=m CONFIG_RESET_UNIPHIER_GLUE=m CONFIG_RESET_ZYNQ=y CONFIG_COMMON_RESET_HI3660=m CONFIG_COMMON_RESET_HI6220=m # # PHY Subsystem # CONFIG_GENERIC_PHY=y CONFIG_GENERIC_PHY_MIPI_DPHY=y CONFIG_PHY_LPC18XX_USB_OTG=m CONFIG_PHY_PISTACHIO_USB=m CONFIG_PHY_XGENE=m CONFIG_USB_LGM_PHY=m CONFIG_PHY_CAN_TRANSCEIVER=m CONFIG_PHY_SUN4I_USB=m CONFIG_PHY_SUN6I_MIPI_DPHY=m CONFIG_PHY_SUN9I_USB=m CONFIG_PHY_SUN50I_USB3=m CONFIG_PHY_MESON8_HDMI_TX=m CONFIG_PHY_MESON8B_USB2=m CONFIG_PHY_MESON_GXL_USB2=m CONFIG_PHY_MESON_G12A_MIPI_DPHY_ANALOG=m CONFIG_PHY_MESON_G12A_USB2=m CONFIG_PHY_MESON_G12A_USB3_PCIE=m CONFIG_PHY_MESON_AXG_PCIE=m CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=m CONFIG_PHY_MESON_AXG_MIPI_DPHY=m # # PHY drivers for Broadcom platforms # CONFIG_PHY_BCM63XX_USBH=m CONFIG_PHY_CYGNUS_PCIE=m CONFIG_PHY_BCM_SR_USB=m CONFIG_BCM_KONA_USB2_PHY=m CONFIG_PHY_BCM_NS_USB2=m CONFIG_PHY_BCM_NS_USB3=m CONFIG_PHY_NS2_PCIE=m CONFIG_PHY_NS2_USB_DRD=m CONFIG_PHY_BRCM_SATA=m CONFIG_PHY_BRCM_USB=m CONFIG_PHY_BCM_SR_PCIE=m # end of PHY drivers for Broadcom platforms CONFIG_PHY_CADENCE_TORRENT=m CONFIG_PHY_CADENCE_DPHY=m CONFIG_PHY_CADENCE_DPHY_RX=m CONFIG_PHY_CADENCE_SIERRA=m CONFIG_PHY_CADENCE_SALVO=m CONFIG_PHY_FSL_IMX8MQ_USB=m CONFIG_PHY_MIXEL_LVDS_PHY=m CONFIG_PHY_MIXEL_MIPI_DPHY=m CONFIG_PHY_FSL_IMX8M_PCIE=m CONFIG_PHY_FSL_LYNX_28G=m CONFIG_PHY_HI6220_USB=m CONFIG_PHY_HI3660_USB=m CONFIG_PHY_HI3670_USB=m CONFIG_PHY_HI3670_PCIE=m CONFIG_PHY_HISTB_COMBPHY=m CONFIG_PHY_HISI_INNO_USB2=m CONFIG_PHY_INGENIC_USB=m CONFIG_PHY_LANTIQ_VRX200_PCIE=m CONFIG_PHY_LANTIQ_RCU_USB2=m CONFIG_ARMADA375_USBCLUSTER_PHY=y CONFIG_PHY_BERLIN_SATA=m CONFIG_PHY_BERLIN_USB=m CONFIG_PHY_MVEBU_A3700_UTMI=m CONFIG_PHY_MVEBU_A38X_COMPHY=m CONFIG_PHY_MVEBU_CP110_UTMI=m CONFIG_PHY_PXA_28NM_HSIC=m CONFIG_PHY_PXA_28NM_USB2=m CONFIG_PHY_PXA_USB=m CONFIG_PHY_MMP3_USB=m CONFIG_PHY_MMP3_HSIC=m CONFIG_PHY_MTK_PCIE=m CONFIG_PHY_MTK_TPHY=m CONFIG_PHY_MTK_UFS=m CONFIG_PHY_MTK_XSPHY=m CONFIG_PHY_MTK_HDMI=m CONFIG_PHY_MTK_MIPI_DSI=m CONFIG_PHY_MTK_DP=m CONFIG_PHY_SPARX5_SERDES=m CONFIG_PHY_LAN966X_SERDES=m CONFIG_PHY_CPCAP_USB=m CONFIG_PHY_MAPPHONE_MDM6600=m CONFIG_PHY_OCELOT_SERDES=m CONFIG_PHY_ATH79_USB=m CONFIG_PHY_QCOM_EDP=m CONFIG_PHY_QCOM_IPQ4019_USB=m CONFIG_PHY_QCOM_PCIE2=m CONFIG_PHY_QCOM_QMP=m CONFIG_PHY_QCOM_QUSB2=m CONFIG_PHY_QCOM_USB_HS=m CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m CONFIG_PHY_QCOM_USB_HSIC=m CONFIG_PHY_QCOM_USB_HS_28NM=m CONFIG_PHY_QCOM_USB_SS=m CONFIG_PHY_QCOM_IPQ806X_USB=m CONFIG_PHY_MT7621_PCI=m CONFIG_PHY_RALINK_USB=m CONFIG_PHY_RCAR_GEN3_USB3=m CONFIG_PHY_ROCKCHIP_DPHY_RX0=m CONFIG_PHY_ROCKCHIP_INNO_HDMI=m CONFIG_PHY_ROCKCHIP_INNO_USB2=m CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m CONFIG_PHY_ROCKCHIP_PCIE=m CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m CONFIG_PHY_ROCKCHIP_TYPEC=m CONFIG_PHY_EXYNOS_DP_VIDEO=m CONFIG_PHY_EXYNOS_MIPI_VIDEO=m CONFIG_PHY_EXYNOS_PCIE=y CONFIG_PHY_SAMSUNG_UFS=m CONFIG_PHY_SAMSUNG_USB2=m CONFIG_PHY_S5PV210_USB2=y CONFIG_PHY_EXYNOS5_USBDRD=m CONFIG_PHY_UNIPHIER_USB2=m CONFIG_PHY_UNIPHIER_USB3=m CONFIG_PHY_UNIPHIER_PCIE=m CONFIG_PHY_UNIPHIER_AHCI=m CONFIG_PHY_ST_SPEAR1310_MIPHY=m CONFIG_PHY_ST_SPEAR1340_MIPHY=m CONFIG_PHY_STIH407_USB=m CONFIG_PHY_STM32_USBPHYC=m CONFIG_PHY_SUNPLUS_USB=m CONFIG_PHY_TEGRA194_P2U=m CONFIG_PHY_DA8XX_USB=m CONFIG_PHY_DM816X_USB=m CONFIG_PHY_AM654_SERDES=m CONFIG_PHY_J721E_WIZ=m CONFIG_OMAP_CONTROL_PHY=m CONFIG_TI_PIPE3=m CONFIG_PHY_TUSB1210=m CONFIG_PHY_TI_GMII_SEL=m CONFIG_PHY_INTEL_KEEMBAY_EMMC=m CONFIG_PHY_INTEL_KEEMBAY_USB=m CONFIG_PHY_INTEL_LGM_COMBO=y CONFIG_PHY_INTEL_LGM_EMMC=m CONFIG_PHY_INTEL_THUNDERBAY_EMMC=m CONFIG_PHY_XILINX_ZYNQMP=m # end of PHY Subsystem CONFIG_POWERCAP=y CONFIG_DTPM=y CONFIG_DTPM_CPU=y CONFIG_DTPM_DEVFREQ=y CONFIG_MCB=m CONFIG_MCB_PCI=m CONFIG_MCB_LPC=m CONFIG_RAS=y CONFIG_USB4=m CONFIG_USB4_DEBUGFS_WRITE=y CONFIG_USB4_DEBUGFS_MARGINING=y CONFIG_USB4_DMA_TEST=m # # Android # CONFIG_ANDROID_BINDER_IPC=y CONFIG_ANDROID_BINDERFS=y CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" CONFIG_ANDROID_BINDER_IPC_SELFTEST=y # end of Android CONFIG_LIBNVDIMM=m CONFIG_BLK_DEV_PMEM=m CONFIG_ND_CLAIM=y CONFIG_ND_BTT=m CONFIG_BTT=y CONFIG_OF_PMEM=m CONFIG_NVDIMM_KEYS=y CONFIG_DAX=m CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y CONFIG_NVMEM_APPLE_EFUSES=m CONFIG_NVMEM_BCM_OCOTP=m CONFIG_NVMEM_BRCM_NVRAM=m CONFIG_NVMEM_IMX_IIM=m CONFIG_NVMEM_IMX_OCOTP=m CONFIG_NVMEM_JZ4780_EFUSE=m CONFIG_NVMEM_LAN9662_OTPC=m CONFIG_NVMEM_LAYERSCAPE_SFP=m CONFIG_NVMEM_LPC18XX_EEPROM=m CONFIG_NVMEM_LPC18XX_OTP=m CONFIG_NVMEM_MESON_MX_EFUSE=m CONFIG_NVMEM_MICROCHIP_OTPC=m CONFIG_NVMEM_MTK_EFUSE=m CONFIG_NVMEM_MXS_OCOTP=m CONFIG_NVMEM_NINTENDO_OTP=m CONFIG_NVMEM_QCOM_QFPROM=m CONFIG_NVMEM_RAVE_SP_EEPROM=m CONFIG_NVMEM_RMEM=m CONFIG_NVMEM_ROCKCHIP_EFUSE=m CONFIG_NVMEM_ROCKCHIP_OTP=m CONFIG_NVMEM_SC27XX_EFUSE=m CONFIG_NVMEM_SNVS_LPGPR=m CONFIG_NVMEM_SPMI_SDAM=m CONFIG_NVMEM_SPRD_EFUSE=m CONFIG_NVMEM_STM32_ROMEM=m CONFIG_NVMEM_SUNPLUS_OCOTP=m CONFIG_NVMEM_U_BOOT_ENV=m CONFIG_NVMEM_UNIPHIER_EFUSE=m CONFIG_NVMEM_VF610_OCOTP=m # # HW tracing support # CONFIG_STM=m CONFIG_STM_PROTO_BASIC=m CONFIG_STM_PROTO_SYS_T=m CONFIG_STM_DUMMY=m CONFIG_STM_SOURCE_CONSOLE=m CONFIG_STM_SOURCE_HEARTBEAT=m CONFIG_INTEL_TH=m CONFIG_INTEL_TH_PCI=m CONFIG_INTEL_TH_ACPI=m CONFIG_INTEL_TH_GTH=m CONFIG_INTEL_TH_STH=m CONFIG_INTEL_TH_MSU=m CONFIG_INTEL_TH_PTI=m CONFIG_INTEL_TH_DEBUG=y # end of HW tracing support CONFIG_FPGA=m CONFIG_FPGA_MGR_SOCFPGA=m CONFIG_FPGA_MGR_SOCFPGA_A10=m CONFIG_ALTERA_PR_IP_CORE=m CONFIG_ALTERA_PR_IP_CORE_PLAT=m CONFIG_FPGA_MGR_ALTERA_PS_SPI=m CONFIG_FPGA_MGR_ALTERA_CVP=m CONFIG_FPGA_MGR_ZYNQ_FPGA=m CONFIG_FPGA_MGR_XILINX_SPI=m CONFIG_FPGA_MGR_ICE40_SPI=m CONFIG_FPGA_MGR_MACHXO2_SPI=m CONFIG_FPGA_BRIDGE=m CONFIG_ALTERA_FREEZE_BRIDGE=m CONFIG_XILINX_PR_DECOUPLER=m CONFIG_FPGA_REGION=m CONFIG_OF_FPGA_REGION=m CONFIG_FPGA_DFL=m CONFIG_FPGA_DFL_AFU=m CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m CONFIG_FPGA_DFL_PCI=m CONFIG_FPGA_MGR_ZYNQMP_FPGA=m CONFIG_FPGA_MGR_VERSAL_FPGA=m CONFIG_FPGA_M10_BMC_SEC_UPDATE=m CONFIG_FPGA_MGR_MICROCHIP_SPI=m CONFIG_FSI=m CONFIG_FSI_NEW_DEV_NODE=y CONFIG_FSI_MASTER_GPIO=m CONFIG_FSI_MASTER_HUB=m CONFIG_FSI_MASTER_AST_CF=m CONFIG_FSI_MASTER_ASPEED=m CONFIG_FSI_SCOM=m CONFIG_FSI_SBEFIFO=m CONFIG_FSI_OCC=m CONFIG_TEE=m CONFIG_MULTIPLEXER=m # # Multiplexer drivers # CONFIG_MUX_ADG792A=m CONFIG_MUX_ADGS1408=m CONFIG_MUX_GPIO=m CONFIG_MUX_MMIO=m # end of Multiplexer drivers CONFIG_PM_OPP=y CONFIG_SIOX=m CONFIG_SIOX_BUS_GPIO=m CONFIG_SLIMBUS=m CONFIG_SLIM_QCOM_CTRL=m CONFIG_SLIM_QCOM_NGD_CTRL=m CONFIG_INTERCONNECT=y CONFIG_INTERCONNECT_IMX=m CONFIG_INTERCONNECT_IMX8MM=m CONFIG_INTERCONNECT_IMX8MN=m CONFIG_INTERCONNECT_IMX8MQ=m CONFIG_INTERCONNECT_IMX8MP=m CONFIG_INTERCONNECT_QCOM_OSM_L3=m CONFIG_INTERCONNECT_SAMSUNG=y CONFIG_INTERCONNECT_EXYNOS=m CONFIG_COUNTER=m CONFIG_104_QUAD_8=m CONFIG_INTERRUPT_CNT=m CONFIG_STM32_TIMER_CNT=m CONFIG_STM32_LPTIMER_CNT=m CONFIG_TI_EQEP=m CONFIG_FTM_QUADDEC=m CONFIG_MICROCHIP_TCB_CAPTURE=m CONFIG_INTEL_QEP=m CONFIG_TI_ECAP_CAPTURE=m CONFIG_MOST=m CONFIG_MOST_USB_HDM=m CONFIG_MOST_CDEV=m CONFIG_PECI=m CONFIG_PECI_CPU=m CONFIG_PECI_ASPEED=m CONFIG_HTE=y # end of Device Drivers # # File systems # CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y CONFIG_EXT2_FS=m CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=m CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT4_FS=m CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y CONFIG_EXT4_DEBUG=y CONFIG_EXT4_KUNIT_TESTS=m CONFIG_JBD2=m CONFIG_JBD2_DEBUG=y CONFIG_FS_MBCACHE=m CONFIG_REISERFS_FS=m CONFIG_REISERFS_CHECK=y CONFIG_REISERFS_PROC_INFO=y CONFIG_REISERFS_FS_XATTR=y CONFIG_REISERFS_FS_POSIX_ACL=y CONFIG_REISERFS_FS_SECURITY=y CONFIG_JFS_FS=m CONFIG_JFS_POSIX_ACL=y CONFIG_JFS_SECURITY=y CONFIG_JFS_DEBUG=y CONFIG_JFS_STATISTICS=y CONFIG_XFS_FS=m CONFIG_XFS_SUPPORT_V4=y CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y CONFIG_XFS_ONLINE_SCRUB=y CONFIG_XFS_ONLINE_REPAIR=y CONFIG_XFS_DEBUG=y CONFIG_XFS_ASSERT_FATAL=y CONFIG_GFS2_FS=m CONFIG_GFS2_FS_LOCKING_DLM=y CONFIG_OCFS2_FS=m CONFIG_OCFS2_FS_O2CB=m CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCFS2_FS_STATS=y CONFIG_OCFS2_DEBUG_MASKLOG=y CONFIG_OCFS2_DEBUG_FS=y CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_BTRFS_FS_CHECK_INTEGRITY=y CONFIG_BTRFS_FS_RUN_SANITY_TESTS=y CONFIG_BTRFS_DEBUG=y CONFIG_BTRFS_ASSERT=y CONFIG_BTRFS_FS_REF_VERIFY=y CONFIG_NILFS2_FS=m CONFIG_F2FS_FS=m CONFIG_F2FS_STAT_FS=y CONFIG_F2FS_FS_XATTR=y CONFIG_F2FS_FS_POSIX_ACL=y CONFIG_F2FS_FS_SECURITY=y CONFIG_F2FS_CHECK_FS=y CONFIG_F2FS_FAULT_INJECTION=y CONFIG_F2FS_FS_COMPRESSION=y CONFIG_F2FS_FS_LZO=y CONFIG_F2FS_FS_LZORLE=y CONFIG_F2FS_FS_LZ4=y CONFIG_F2FS_FS_LZ4HC=y CONFIG_F2FS_FS_ZSTD=y CONFIG_F2FS_IOSTAT=y CONFIG_F2FS_UNFAIR_RWSEM=y CONFIG_ZONEFS_FS=m CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y CONFIG_EXPORTFS_BLOCK_OPS=y CONFIG_FILE_LOCKING=y CONFIG_FS_ENCRYPTION=y CONFIG_FS_ENCRYPTION_ALGS=m CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y CONFIG_FS_VERITY=y CONFIG_FS_VERITY_DEBUG=y CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_FANOTIFY=y CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_PRINT_QUOTA_WARNING=y CONFIG_QUOTA_DEBUG=y CONFIG_QUOTA_TREE=m CONFIG_QFMT_V1=m CONFIG_QFMT_V2=m CONFIG_QUOTACTL=y CONFIG_AUTOFS4_FS=m CONFIG_AUTOFS_FS=m CONFIG_FUSE_FS=m CONFIG_CUSE=m CONFIG_VIRTIO_FS=m CONFIG_OVERLAY_FS=m CONFIG_OVERLAY_FS_REDIRECT_DIR=y CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y CONFIG_OVERLAY_FS_INDEX=y CONFIG_OVERLAY_FS_XINO_AUTO=y CONFIG_OVERLAY_FS_METACOPY=y # # Caches # CONFIG_NETFS_SUPPORT=m CONFIG_NETFS_STATS=y CONFIG_FSCACHE=m CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE_DEBUG=y CONFIG_CACHEFILES=m CONFIG_CACHEFILES_DEBUG=y CONFIG_CACHEFILES_ERROR_INJECTION=y CONFIG_CACHEFILES_ONDEMAND=y # end of Caches # # CD-ROM/DVD Filesystems # CONFIG_ISO9660_FS=m CONFIG_JOLIET=y CONFIG_ZISOFS=y CONFIG_UDF_FS=m # end of CD-ROM/DVD Filesystems # # DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=m CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_FAT_DEFAULT_UTF8=y CONFIG_FAT_KUNIT_TEST=m CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" CONFIG_NTFS_FS=m CONFIG_NTFS_DEBUG=y CONFIG_NTFS_RW=y CONFIG_NTFS3_FS=m CONFIG_NTFS3_64BIT_CLUSTER=y CONFIG_NTFS3_LZX_XPRESS=y CONFIG_NTFS3_FS_POSIX_ACL=y # end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems # CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_VMCORE=y CONFIG_PROC_VMCORE_DEVICE_DUMP=y CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_PROC_CHILDREN=y CONFIG_KERNFS=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS_INODE64=y CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y CONFIG_CONFIGFS_FS=y CONFIG_EFIVAR_FS=m # end of Pseudo filesystems CONFIG_MISC_FILESYSTEMS=y CONFIG_ORANGEFS_FS=m CONFIG_ADFS_FS=m CONFIG_ADFS_FS_RW=y CONFIG_AFFS_FS=m CONFIG_ECRYPT_FS=m CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_HFS_FS=m CONFIG_HFSPLUS_FS=m CONFIG_BEFS_FS=m CONFIG_BEFS_DEBUG=y CONFIG_BFS_FS=m CONFIG_EFS_FS=m CONFIG_JFFS2_FS=m CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y CONFIG_JFFS2_FS_WBUF_VERIFY=y CONFIG_JFFS2_SUMMARY=y CONFIG_JFFS2_FS_XATTR=y CONFIG_JFFS2_FS_POSIX_ACL=y CONFIG_JFFS2_FS_SECURITY=y CONFIG_JFFS2_COMPRESSION_OPTIONS=y CONFIG_JFFS2_ZLIB=y CONFIG_JFFS2_LZO=y CONFIG_JFFS2_RTIME=y CONFIG_JFFS2_RUBIN=y # CONFIG_JFFS2_CMODE_NONE is not set CONFIG_JFFS2_CMODE_PRIORITY=y # CONFIG_JFFS2_CMODE_SIZE is not set # CONFIG_JFFS2_CMODE_FAVOURLZO is not set CONFIG_UBIFS_FS=m CONFIG_UBIFS_FS_ADVANCED_COMPR=y CONFIG_UBIFS_FS_LZO=y CONFIG_UBIFS_FS_ZLIB=y CONFIG_UBIFS_FS_ZSTD=y CONFIG_UBIFS_ATIME_SUPPORT=y CONFIG_UBIFS_FS_XATTR=y CONFIG_UBIFS_FS_SECURITY=y CONFIG_UBIFS_FS_AUTHENTICATION=y CONFIG_CRAMFS=m CONFIG_CRAMFS_BLOCKDEV=y CONFIG_CRAMFS_MTD=y CONFIG_SQUASHFS=m CONFIG_SQUASHFS_FILE_CACHE=y # CONFIG_SQUASHFS_FILE_DIRECT is not set CONFIG_SQUASHFS_DECOMP_SINGLE=y # CONFIG_SQUASHFS_DECOMP_MULTI is not set # CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set CONFIG_SQUASHFS_XATTR=y CONFIG_SQUASHFS_ZLIB=y CONFIG_SQUASHFS_LZ4=y CONFIG_SQUASHFS_LZO=y CONFIG_SQUASHFS_XZ=y CONFIG_SQUASHFS_ZSTD=y CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y CONFIG_SQUASHFS_EMBEDDED=y CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 CONFIG_VXFS_FS=m CONFIG_MINIX_FS=m CONFIG_OMFS_FS=m CONFIG_HPFS_FS=m CONFIG_QNX4FS_FS=m CONFIG_QNX6FS_FS=m CONFIG_QNX6FS_DEBUG=y CONFIG_ROMFS_FS=m CONFIG_ROMFS_BACKED_BY_BLOCK=y # CONFIG_ROMFS_BACKED_BY_MTD is not set # CONFIG_ROMFS_BACKED_BY_BOTH is not set CONFIG_ROMFS_ON_BLOCK=y CONFIG_PSTORE=m CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=m CONFIG_PSTORE_LZO_COMPRESS=m CONFIG_PSTORE_LZ4_COMPRESS=m CONFIG_PSTORE_LZ4HC_COMPRESS=m CONFIG_PSTORE_842_COMPRESS=y CONFIG_PSTORE_ZSTD_COMPRESS=y CONFIG_PSTORE_COMPRESS=y CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y # CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set # CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set # CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set # CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set # CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" CONFIG_PSTORE_CONSOLE=y CONFIG_PSTORE_PMSG=y CONFIG_PSTORE_RAM=m CONFIG_PSTORE_ZONE=m CONFIG_PSTORE_BLK=m CONFIG_PSTORE_BLK_BLKDEV="" CONFIG_PSTORE_BLK_KMSG_SIZE=64 CONFIG_PSTORE_BLK_MAX_REASON=2 CONFIG_PSTORE_BLK_PMSG_SIZE=64 CONFIG_PSTORE_BLK_CONSOLE_SIZE=64 CONFIG_SYSV_FS=m CONFIG_UFS_FS=m CONFIG_UFS_FS_WRITE=y CONFIG_UFS_DEBUG=y CONFIG_EROFS_FS=m CONFIG_EROFS_FS_DEBUG=y CONFIG_EROFS_FS_XATTR=y CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_ZIP=y CONFIG_EROFS_FS_ZIP_LZMA=y CONFIG_EROFS_FS_ONDEMAND=y CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V2=m CONFIG_NFS_V3=m CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=m CONFIG_NFS_SWAP=y CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y CONFIG_PNFS_FILE_LAYOUT=m CONFIG_PNFS_BLOCK=m CONFIG_PNFS_FLEXFILE_LAYOUT=m CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" CONFIG_NFS_V4_1_MIGRATION=y CONFIG_NFS_V4_SECURITY_LABEL=y CONFIG_NFS_FSCACHE=y CONFIG_NFS_USE_LEGACY_DNS=y CONFIG_NFS_DEBUG=y CONFIG_NFS_DISABLE_UDP_SUPPORT=y CONFIG_NFS_V4_2_READ_PLUS=y CONFIG_NFSD=m CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y CONFIG_NFSD_PNFS=y CONFIG_NFSD_BLOCKLAYOUT=y CONFIG_NFSD_SCSILAYOUT=y CONFIG_NFSD_FLEXFILELAYOUT=y CONFIG_NFSD_V4_2_INTER_SSC=y CONFIG_NFSD_V4_SECURITY_LABEL=y CONFIG_GRACE_PERIOD=m CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_NFS_ACL_SUPPORT=m CONFIG_NFS_COMMON=y CONFIG_NFS_V4_2_SSC_HELPER=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m CONFIG_SUNRPC_BACKCHANNEL=y CONFIG_SUNRPC_SWAP=y CONFIG_RPCSEC_GSS_KRB5=m CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y CONFIG_SUNRPC_DEBUG=y CONFIG_SUNRPC_XPRT_RDMA=m CONFIG_CEPH_FS=m CONFIG_CEPH_FSCACHE=y CONFIG_CEPH_FS_POSIX_ACL=y CONFIG_CEPH_FS_SECURITY_LABEL=y CONFIG_CIFS=m CONFIG_CIFS_STATS2=y CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y CONFIG_CIFS_UPCALL=y CONFIG_CIFS_XATTR=y CONFIG_CIFS_POSIX=y CONFIG_CIFS_DEBUG=y CONFIG_CIFS_DEBUG2=y CONFIG_CIFS_DEBUG_DUMP_KEYS=y CONFIG_CIFS_DFS_UPCALL=y CONFIG_CIFS_SWN_UPCALL=y CONFIG_CIFS_SMB_DIRECT=y CONFIG_CIFS_FSCACHE=y CONFIG_SMB_SERVER=m CONFIG_SMB_SERVER_SMBDIRECT=y CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y CONFIG_SMB_SERVER_KERBEROS5=y CONFIG_SMBFS_COMMON=m CONFIG_CODA_FS=m CONFIG_AFS_FS=m CONFIG_AFS_DEBUG=y CONFIG_AFS_FSCACHE=y CONFIG_AFS_DEBUG_CURSOR=y CONFIG_9P_FS=m CONFIG_9P_FSCACHE=y CONFIG_9P_FS_POSIX_ACL=y CONFIG_9P_FS_SECURITY=y CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m CONFIG_NLS_CODEPAGE_737=m CONFIG_NLS_CODEPAGE_775=m CONFIG_NLS_CODEPAGE_850=m CONFIG_NLS_CODEPAGE_852=m CONFIG_NLS_CODEPAGE_855=m CONFIG_NLS_CODEPAGE_857=m CONFIG_NLS_CODEPAGE_860=m CONFIG_NLS_CODEPAGE_861=m CONFIG_NLS_CODEPAGE_862=m CONFIG_NLS_CODEPAGE_863=m CONFIG_NLS_CODEPAGE_864=m CONFIG_NLS_CODEPAGE_865=m CONFIG_NLS_CODEPAGE_866=m CONFIG_NLS_CODEPAGE_869=m CONFIG_NLS_CODEPAGE_936=m CONFIG_NLS_CODEPAGE_950=m CONFIG_NLS_CODEPAGE_932=m CONFIG_NLS_CODEPAGE_949=m CONFIG_NLS_CODEPAGE_874=m CONFIG_NLS_ISO8859_8=m CONFIG_NLS_CODEPAGE_1250=m CONFIG_NLS_CODEPAGE_1251=m CONFIG_NLS_ASCII=m CONFIG_NLS_ISO8859_1=m CONFIG_NLS_ISO8859_2=m CONFIG_NLS_ISO8859_3=m CONFIG_NLS_ISO8859_4=m CONFIG_NLS_ISO8859_5=m CONFIG_NLS_ISO8859_6=m CONFIG_NLS_ISO8859_7=m CONFIG_NLS_ISO8859_9=m CONFIG_NLS_ISO8859_13=m CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_MAC_ROMAN=m CONFIG_NLS_MAC_CELTIC=m CONFIG_NLS_MAC_CENTEURO=m CONFIG_NLS_MAC_CROATIAN=m CONFIG_NLS_MAC_CYRILLIC=m CONFIG_NLS_MAC_GAELIC=m CONFIG_NLS_MAC_GREEK=m CONFIG_NLS_MAC_ICELAND=m CONFIG_NLS_MAC_INUIT=m CONFIG_NLS_MAC_ROMANIAN=m CONFIG_NLS_MAC_TURKISH=m CONFIG_NLS_UTF8=m CONFIG_DLM=m CONFIG_DLM_DEPRECATED_API=y CONFIG_DLM_DEBUG=y CONFIG_UNICODE=m CONFIG_UNICODE_NORMALIZATION_SELFTEST=m CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y CONFIG_KEYS_REQUEST_CACHE=y CONFIG_PERSISTENT_KEYRINGS=y CONFIG_TRUSTED_KEYS=m CONFIG_TRUSTED_KEYS_TPM=y CONFIG_TRUSTED_KEYS_TEE=y CONFIG_ENCRYPTED_KEYS=y CONFIG_USER_DECRYPTED_DATA=y CONFIG_KEY_DH_OPERATIONS=y CONFIG_KEY_NOTIFICATIONS=y CONFIG_SECURITY_DMESG_RESTRICT=y CONFIG_SECURITY=y CONFIG_SECURITY_WRITABLE_HOOKS=y CONFIG_SECURITYFS=y CONFIG_SECURITY_NETWORK=y CONFIG_SECURITY_INFINIBAND=y CONFIG_SECURITY_NETWORK_XFRM=y CONFIG_SECURITY_PATH=y CONFIG_LSM_MMAP_MIN_ADDR=65536 CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y CONFIG_HARDENED_USERCOPY=y CONFIG_STATIC_USERMODEHELPER=y CONFIG_STATIC_USERMODEHELPER_PATH="/sbin/usermode-helper" CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SELINUX_BOOTPARAM=y CONFIG_SECURITY_SELINUX_DISABLE=y CONFIG_SECURITY_SELINUX_DEVELOP=y CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0 CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 CONFIG_SECURITY_SMACK=y CONFIG_SECURITY_SMACK_BRINGUP=y CONFIG_SECURITY_SMACK_NETFILTER=y CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y CONFIG_SECURITY_TOMOYO=y CONFIG_SECURITY_TOMOYO_MAX_ACCEPT_ENTRY=2048 CONFIG_SECURITY_TOMOYO_MAX_AUDIT_LOG=1024 CONFIG_SECURITY_TOMOYO_OMIT_USERSPACE_LOADER=y CONFIG_SECURITY_TOMOYO_INSECURE_BUILTIN_SETTING=y CONFIG_SECURITY_APPARMOR=y CONFIG_SECURITY_APPARMOR_DEBUG=y CONFIG_SECURITY_APPARMOR_DEBUG_ASSERTS=y CONFIG_SECURITY_APPARMOR_DEBUG_MESSAGES=y CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y CONFIG_SECURITY_APPARMOR_HASH=y CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y CONFIG_SECURITY_LOADPIN=y CONFIG_SECURITY_LOADPIN_ENFORCE=y CONFIG_SECURITY_YAMA=y CONFIG_SECURITY_SAFESETID=y CONFIG_SECURITY_LOCKDOWN_LSM=y CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y # CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set # CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set CONFIG_SECURITY_LANDLOCK=y CONFIG_INTEGRITY=y CONFIG_INTEGRITY_SIGNATURE=y CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y CONFIG_INTEGRITY_TRUSTED_KEYRING=y CONFIG_INTEGRITY_PLATFORM_KEYRING=y CONFIG_LOAD_UEFI_KEYS=y CONFIG_INTEGRITY_AUDIT=y CONFIG_IMA=y CONFIG_IMA_MEASURE_PCR_IDX=10 CONFIG_IMA_LSM_RULES=y CONFIG_IMA_NG_TEMPLATE=y # CONFIG_IMA_SIG_TEMPLATE is not set CONFIG_IMA_DEFAULT_TEMPLATE="ima-ng" CONFIG_IMA_DEFAULT_HASH_SHA1=y # CONFIG_IMA_DEFAULT_HASH_SHA256 is not set # CONFIG_IMA_DEFAULT_HASH_SHA512 is not set CONFIG_IMA_DEFAULT_HASH="sha1" CONFIG_IMA_WRITE_POLICY=y CONFIG_IMA_READ_POLICY=y CONFIG_IMA_APPRAISE=y CONFIG_IMA_ARCH_POLICY=y CONFIG_IMA_APPRAISE_BUILD_POLICY=y CONFIG_IMA_APPRAISE_REQUIRE_FIRMWARE_SIGS=y CONFIG_IMA_APPRAISE_REQUIRE_KEXEC_SIGS=y CONFIG_IMA_APPRAISE_REQUIRE_MODULE_SIGS=y CONFIG_IMA_APPRAISE_REQUIRE_POLICY_SIGS=y CONFIG_IMA_APPRAISE_BOOTPARAM=y CONFIG_IMA_APPRAISE_MODSIG=y CONFIG_IMA_TRUSTED_KEYRING=y CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY=y CONFIG_IMA_BLACKLIST_KEYRING=y CONFIG_IMA_LOAD_X509=y CONFIG_IMA_X509_PATH="/etc/keys/x509_ima.der" CONFIG_IMA_APPRAISE_SIGNED_INIT=y CONFIG_IMA_MEASURE_ASYMMETRIC_KEYS=y CONFIG_IMA_QUEUE_EARLY_BOOT_KEYS=y CONFIG_IMA_DISABLE_HTABLE=y CONFIG_EVM=y CONFIG_EVM_ATTR_FSUUID=y CONFIG_EVM_EXTRA_SMACK_XATTRS=y CONFIG_EVM_ADD_XATTRS=y CONFIG_EVM_LOAD_X509=y CONFIG_EVM_X509_PATH="/etc/keys/x509_evm.der" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SECURITY_SMACK is not set # CONFIG_DEFAULT_SECURITY_TOMOYO is not set # CONFIG_DEFAULT_SECURITY_APPARMOR is not set # CONFIG_DEFAULT_SECURITY_DAC is not set CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor,bpf" # # Kernel hardening options # # # Memory initialization # CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INIT_STACK_ALL_PATTERN=y # CONFIG_INIT_STACK_ALL_ZERO is not set CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y CONFIG_INIT_ON_FREE_DEFAULT_ON=y CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y # CONFIG_ZERO_CALL_USED_REGS is not set # end of Memory initialization CONFIG_RANDSTRUCT_NONE=y # end of Kernel hardening options # end of Security options CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m CONFIG_ASYNC_MEMCPY=m CONFIG_ASYNC_XOR=m CONFIG_ASYNC_PQ=m CONFIG_ASYNC_RAID6_RECOV=m CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA=y CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA=y CONFIG_CRYPTO=y # # Crypto core or helper # CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=m CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_RNG_DEFAULT=y CONFIG_CRYPTO_AKCIPHER2=y CONFIG_CRYPTO_AKCIPHER=y CONFIG_CRYPTO_KPP2=y CONFIG_CRYPTO_KPP=y CONFIG_CRYPTO_ACOMP2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_PCRYPT=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_ENGINE=m # end of Crypto core or helper # # Public-key cryptography # CONFIG_CRYPTO_RSA=y CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m CONFIG_CRYPTO_ECDSA=m CONFIG_CRYPTO_ECRDSA=m CONFIG_CRYPTO_SM2=m CONFIG_CRYPTO_CURVE25519=m # end of Public-key cryptography # # Block ciphers # CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_AES_TI=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_ARIA=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_BLOWFISH_COMMON=m CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST_COMMON=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m CONFIG_CRYPTO_DES=m CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_SM4=m CONFIG_CRYPTO_SM4_GENERIC=m CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_TWOFISH_COMMON=m # end of Block ciphers # # Length-preserving ciphers and modes # CONFIG_CRYPTO_ADIANTUM=m CONFIG_CRYPTO_ARC4=m CONFIG_CRYPTO_CHACHA20=m CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CFB=m CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_ECB=m CONFIG_CRYPTO_HCTR2=m CONFIG_CRYPTO_KEYWRAP=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_OFB=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XCTR=m CONFIG_CRYPTO_XTS=m CONFIG_CRYPTO_NHPOLY1305=m # end of Length-preserving ciphers and modes # # AEAD (authenticated encryption with associated data) ciphers # CONFIG_CRYPTO_AEGIS128=m CONFIG_CRYPTO_CHACHA20POLY1305=m CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_GCM=m CONFIG_CRYPTO_SEQIV=m CONFIG_CRYPTO_ECHAINIV=m CONFIG_CRYPTO_ESSIV=m # end of AEAD (authenticated encryption with associated data) ciphers # # Hashes, digests, and MACs # CONFIG_CRYPTO_BLAKE2B=m CONFIG_CRYPTO_CMAC=m CONFIG_CRYPTO_GHASH=m CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_POLYVAL=m CONFIG_CRYPTO_POLY1305=m CONFIG_CRYPTO_RMD160=m CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA3=m CONFIG_CRYPTO_SM3=m CONFIG_CRYPTO_SM3_GENERIC=m CONFIG_CRYPTO_STREEBOG=m CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_XCBC=m CONFIG_CRYPTO_XXHASH=m # end of Hashes, digests, and MACs # # CRCs (cyclic redundancy checks) # CONFIG_CRYPTO_CRC32C=m CONFIG_CRYPTO_CRC32=m CONFIG_CRYPTO_CRCT10DIF=m CONFIG_CRYPTO_CRC64_ROCKSOFT=m # end of CRCs (cyclic redundancy checks) # # Compression # CONFIG_CRYPTO_DEFLATE=m CONFIG_CRYPTO_LZO=y CONFIG_CRYPTO_842=m CONFIG_CRYPTO_LZ4=m CONFIG_CRYPTO_LZ4HC=m CONFIG_CRYPTO_ZSTD=m # end of Compression # # Random number generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_DRBG_MENU=y CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG_HASH=y CONFIG_CRYPTO_DRBG_CTR=y CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_KDF800108_CTR=y # end of Random number generation # # Userspace interface # CONFIG_CRYPTO_USER_API=m CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_USER_API_RNG=m CONFIG_CRYPTO_USER_API_RNG_CAVP=y CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_STATS=y # end of Userspace interface CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_ALLWINNER=y CONFIG_CRYPTO_DEV_SUN8I_CE=m CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y CONFIG_CRYPTO_DEV_SUN8I_SS=m CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG=y CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y CONFIG_CRYPTO_DEV_SL3516=m CONFIG_CRYPTO_DEV_SL3516_DEBUG=y CONFIG_CRYPTO_DEV_EXYNOS_RNG=m CONFIG_CRYPTO_DEV_S5P=m CONFIG_CRYPTO_DEV_ATMEL_AUTHENC=y CONFIG_CRYPTO_DEV_ATMEL_AES=m CONFIG_CRYPTO_DEV_ATMEL_TDES=m CONFIG_CRYPTO_DEV_ATMEL_SHA=m CONFIG_CRYPTO_DEV_ATMEL_I2C=m CONFIG_CRYPTO_DEV_ATMEL_ECC=m CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m CONFIG_CRYPTO_DEV_QAT=m CONFIG_CRYPTO_DEV_QAT_DH895xCC=m CONFIG_CRYPTO_DEV_QAT_C3XXX=m CONFIG_CRYPTO_DEV_QAT_C62X=m CONFIG_CRYPTO_DEV_QAT_4XXX=m CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m CONFIG_CRYPTO_DEV_QAT_C62XVF=m CONFIG_CRYPTO_DEV_CPT=m CONFIG_CAVIUM_CPT=m CONFIG_CRYPTO_DEV_NITROX=m CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m CONFIG_CRYPTO_DEV_MARVELL=m CONFIG_CRYPTO_DEV_OCTEONTX_CPT=m CONFIG_CRYPTO_DEV_OCTEONTX2_CPT=m CONFIG_CRYPTO_DEV_CAVIUM_ZIP=m CONFIG_CRYPTO_DEV_QCE=m CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y CONFIG_CRYPTO_DEV_QCE_SHA=y CONFIG_CRYPTO_DEV_QCE_AEAD=y CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL=y # CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER is not set # CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set # CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512 CONFIG_CRYPTO_DEV_QCOM_RNG=m CONFIG_CRYPTO_DEV_IMGTEC_HASH=m CONFIG_CRYPTO_DEV_ZYNQMP_AES=m CONFIG_CRYPTO_DEV_ZYNQMP_SHA3=m CONFIG_CRYPTO_DEV_CHELSIO=m CONFIG_CRYPTO_DEV_VIRTIO=m CONFIG_CRYPTO_DEV_SAFEXCEL=m CONFIG_CRYPTO_DEV_CCREE=m CONFIG_CRYPTO_DEV_HISI_SEC=m CONFIG_CRYPTO_DEV_HISI_SEC2=m CONFIG_CRYPTO_DEV_HISI_QM=m CONFIG_CRYPTO_DEV_HISI_ZIP=m CONFIG_CRYPTO_DEV_HISI_HPRE=m CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG=y CONFIG_CRYPTO_DEV_SA2UL=m CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4=m CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_ECB=y CONFIG_CRYPTO_DEV_KEEMBAY_OCS_AES_SM4_CTS=y CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECC=m CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU=m CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224=y CONFIG_CRYPTO_DEV_ASPEED=m CONFIG_CRYPTO_DEV_ASPEED_DEBUG=y CONFIG_CRYPTO_DEV_ASPEED_HACE_HASH=y CONFIG_CRYPTO_DEV_ASPEED_HACE_CRYPTO=y CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y CONFIG_PKCS8_PRIVATE_KEY_PARSER=m CONFIG_PKCS7_MESSAGE_PARSER=y CONFIG_PKCS7_TEST_KEY=m CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_FIPS_SIGNATURE_SELFTEST=y # # Certificates for signature checking # CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" CONFIG_MODULE_SIG_KEY_TYPE_RSA=y # CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set CONFIG_SYSTEM_TRUSTED_KEYRING=y CONFIG_SYSTEM_TRUSTED_KEYS="" CONFIG_SYSTEM_EXTRA_CERTIFICATE=y CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 CONFIG_SECONDARY_TRUSTED_KEYRING=y CONFIG_SYSTEM_BLACKLIST_KEYRING=y CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" CONFIG_SYSTEM_REVOCATION_LIST=y CONFIG_SYSTEM_REVOCATION_KEYS="" CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y # end of Certificates for signature checking CONFIG_BINARY_PRINTF=y # # Library routines # CONFIG_RAID6_PQ=m CONFIG_RAID6_PQ_BENCHMARK=y CONFIG_LINEAR_RANGES=y CONFIG_PACKING=y CONFIG_BITREVERSE=y CONFIG_ARCH_HAS_STRNCPY_FROM_USER=y CONFIG_ARCH_HAS_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=m CONFIG_PRIME_NUMBERS=m CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_IOMAP=y CONFIG_STMP_DEVICE=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # # Crypto library routines # CONFIG_CRYPTO_LIB_UTILS=y CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m CONFIG_CRYPTO_LIB_CHACHA=m CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m CONFIG_CRYPTO_LIB_CURVE25519=m CONFIG_CRYPTO_LIB_DES=m CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines CONFIG_CRC_CCITT=m CONFIG_CRC16=m CONFIG_CRC_T10DIF=m CONFIG_CRC64_ROCKSOFT=m CONFIG_CRC_ITU_T=m CONFIG_CRC32=y CONFIG_CRC32_SELFTEST=m CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set CONFIG_CRC64=m CONFIG_CRC4=m CONFIG_CRC7=m CONFIG_LIBCRC32C=m CONFIG_CRC8=y CONFIG_XXHASH=y CONFIG_RANDOM32_SELFTEST=y CONFIG_842_COMPRESS=m CONFIG_842_DECOMPRESS=m CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_COMPRESS=m CONFIG_LZ4HC_COMPRESS=m CONFIG_LZ4_DECOMPRESS=y CONFIG_ZSTD_COMMON=y CONFIG_ZSTD_COMPRESS=m CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_IA64=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_SPARC=y CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_BCJ=y CONFIG_XZ_DEC_TEST=m CONFIG_DECOMPRESS_GZIP=y CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=m CONFIG_REED_SOLOMON_ENC8=y CONFIG_REED_SOLOMON_DEC8=y CONFIG_REED_SOLOMON_ENC16=y CONFIG_REED_SOLOMON_DEC16=y CONFIG_BCH=m CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m CONFIG_TEXTSEARCH_FSM=m CONFIG_BTREE=y CONFIG_INTERVAL_TREE=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_ARCH_HAS_DMA_MARK_CLEAN=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_SWIOTLB=y CONFIG_DMA_RESTRICTED_POOL=y CONFIG_DMA_API_DEBUG=y CONFIG_DMA_API_DEBUG_SG=y CONFIG_DMA_MAP_BENCHMARK=y CONFIG_SGL_ALLOC=y CONFIG_CHECK_SIGNATURE=y CONFIG_CPUMASK_OFFSTACK=y CONFIG_FORCE_NR_CPUS=y CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y CONFIG_GLOB_SELFTEST=m CONFIG_NLATTR=y CONFIG_LRU_CACHE=m CONFIG_CLZ_TAB=y CONFIG_IRQ_POLL=y CONFIG_MPILIB=y CONFIG_SIGNATURE=y CONFIG_DIMLIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y CONFIG_FONT_SUPPORT=m CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_FONT_6x11=y CONFIG_FONT_7x14=y CONFIG_FONT_PEARL_8x8=y CONFIG_FONT_ACORN_8x8=y CONFIG_FONT_MINI_4x6=y CONFIG_FONT_6x10=y CONFIG_FONT_10x18=y CONFIG_FONT_SUN8x16=y CONFIG_FONT_SUN12x22=y CONFIG_FONT_TER16x32=y CONFIG_FONT_6x8=y CONFIG_SG_SPLIT=y CONFIG_SG_POOL=y CONFIG_MEMREGION=y CONFIG_STACKDEPOT=y CONFIG_STACKDEPOT_ALWAYS_INIT=y CONFIG_REF_TRACKER=y CONFIG_SBITMAP=y CONFIG_PARMAN=m CONFIG_OBJAGG=m # end of Library routines CONFIG_PLDMFW=y CONFIG_ASN1_ENCODER=m CONFIG_POLYNOMIAL=m # # Kernel hacking # # # printk and dmesg options # CONFIG_PRINTK_TIME=y CONFIG_PRINTK_CALLER=y CONFIG_STACKTRACE_BUILD_ID=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 CONFIG_BOOT_PRINTK_DELAY=y CONFIG_DYNAMIC_DEBUG=y CONFIG_DYNAMIC_DEBUG_CORE=y CONFIG_SYMBOLIC_ERRNAME=y # end of printk and dmesg options CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y # # Compile-time checks and compiler options # CONFIG_AS_HAS_NON_CONST_LEB128=y CONFIG_DEBUG_INFO_NONE=y # CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set # CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=2048 CONFIG_STRIP_ASM_SYMS=y CONFIG_READABLE_ASM=y CONFIG_HEADERS_INSTALL=y CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_VMLINUX_MAP=y CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y # end of Compile-time checks and compiler options # # Generic Kernel Debugging Instruments # CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_UBSAN=y CONFIG_CC_HAS_UBSAN_BOUNDS=y CONFIG_UBSAN_BOUNDS=y CONFIG_UBSAN_ONLY_BOUNDS=y CONFIG_UBSAN_SHIFT=y CONFIG_UBSAN_DIV_ZERO=y CONFIG_UBSAN_UNREACHABLE=y CONFIG_UBSAN_BOOL=y CONFIG_UBSAN_ENUM=y CONFIG_TEST_UBSAN=m CONFIG_HAVE_KCSAN_COMPILER=y # end of Generic Kernel Debugging Instruments # # Networking Debugging # CONFIG_NET_DEV_REFCNT_TRACKER=y CONFIG_NET_NS_REFCNT_TRACKER=y CONFIG_DEBUG_NET=y # end of Networking Debugging # # Memory Debugging # CONFIG_PAGE_EXTENSION=y CONFIG_DEBUG_PAGEALLOC=y CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y CONFIG_SLUB_DEBUG=y CONFIG_SLUB_DEBUG_ON=y CONFIG_PAGE_OWNER=y CONFIG_PAGE_POISONING=y CONFIG_DEBUG_OBJECTS=y CONFIG_DEBUG_OBJECTS_SELFTEST=y CONFIG_DEBUG_OBJECTS_FREE=y CONFIG_DEBUG_OBJECTS_TIMERS=y CONFIG_DEBUG_OBJECTS_WORK=y CONFIG_DEBUG_OBJECTS_RCU_HEAD=y CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 CONFIG_SHRINKER_DEBUG=y CONFIG_SCHED_STACK_END_CHECK=y CONFIG_DEBUG_VM_IRQSOFF=y CONFIG_DEBUG_VM=y CONFIG_DEBUG_VM_MAPLE_TREE=y CONFIG_DEBUG_VM_RB=y CONFIG_DEBUG_VM_PGFLAGS=y CONFIG_DEBUG_MEMORY_INIT=y CONFIG_MEMORY_NOTIFIER_ERROR_INJECT=m CONFIG_DEBUG_PER_CPU_MAPS=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # end of Memory Debugging CONFIG_DEBUG_SHIRQ=y # # Debug Oops, Lockups and Hangs # CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_ON_OOPS_VALUE=1 CONFIG_PANIC_TIMEOUT=0 CONFIG_LOCKUP_DETECTOR=y CONFIG_SOFTLOCKUP_DETECTOR=y CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y CONFIG_DETECT_HUNG_TASK=y CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y CONFIG_WQ_WATCHDOG=y CONFIG_TEST_LOCKUP=m # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # CONFIG_SCHED_DEBUG=y CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y # end of Scheduler Debugging CONFIG_DEBUG_TIMEKEEPING=y # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_DEBUG_LOCKING_API_SELFTESTS=y CONFIG_LOCK_TORTURE_TEST=m CONFIG_WW_MUTEX_SELFTEST=m CONFIG_SCF_TORTURE_TEST=m CONFIG_CSD_LOCK_WAIT_DEBUG=y # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_DEBUG_IRQFLAGS=y CONFIG_STACKTRACE=y CONFIG_WARN_ALL_UNSEEDED_RANDOM=y CONFIG_DEBUG_KOBJECT=y CONFIG_DEBUG_KOBJECT_RELEASE=y # # Debug kernel data structures # CONFIG_DEBUG_LIST=y CONFIG_DEBUG_PLIST=y CONFIG_DEBUG_SG=y CONFIG_DEBUG_NOTIFIERS=y CONFIG_BUG_ON_DATA_CORRUPTION=y CONFIG_DEBUG_MAPLE_TREE=y # end of Debug kernel data structures CONFIG_DEBUG_CREDENTIALS=y # # RCU Debugging # CONFIG_TORTURE_TEST=m CONFIG_RCU_SCALE_TEST=m CONFIG_RCU_TORTURE_TEST=m CONFIG_RCU_REF_SCALE_TEST=m CONFIG_RCU_CPU_STALL_TIMEOUT=21 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 CONFIG_RCU_TRACE=y CONFIG_RCU_EQS_DEBUG=y # end of RCU Debugging CONFIG_DEBUG_WQ_FORCE_RR_CPU=y CONFIG_CPU_HOTPLUG_STATE_CONTROL=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_TRACE_CLOCK=y # CONFIG_SAMPLES is not set # CONFIG_STRICT_DEVMEM is not set # # ia64 Debugging # CONFIG_IA64_GRANULE_16MB=y CONFIG_IA64_PRINT_HAZARDS=y CONFIG_DISABLE_VHPT=y CONFIG_IA64_DEBUG_CMPXCHG=y CONFIG_IA64_DEBUG_IRQ=y # end of ia64 Debugging # # Kernel Testing and Coverage # CONFIG_KUNIT=m CONFIG_KUNIT_DEBUGFS=y CONFIG_KUNIT_TEST=m CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT_ALL_TESTS=m CONFIG_KUNIT_DEFAULT_ENABLED=y CONFIG_NOTIFIER_ERROR_INJECTION=m CONFIG_PM_NOTIFIER_ERROR_INJECT=m CONFIG_OF_RECONFIG_NOTIFIER_ERROR_INJECT=m CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m CONFIG_FAULT_INJECTION=y CONFIG_FAILSLAB=y CONFIG_FAIL_PAGE_ALLOC=y CONFIG_FAULT_INJECTION_USERCOPY=y CONFIG_FAIL_MAKE_REQUEST=y CONFIG_FAIL_IO_TIMEOUT=y CONFIG_FAIL_FUTEX=y CONFIG_FAULT_INJECTION_DEBUG_FS=y CONFIG_FAIL_MMC_REQUEST=y CONFIG_FAIL_SUNRPC=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y CONFIG_LKDTM=m CONFIG_CPUMASK_KUNIT_TEST=m CONFIG_TEST_LIST_SORT=m CONFIG_TEST_MIN_HEAP=m CONFIG_TEST_SORT=m CONFIG_TEST_DIV64=m CONFIG_KPROBES_SANITY_TEST=m CONFIG_BACKTRACE_SELF_TEST=m CONFIG_TEST_REF_TRACKER=m CONFIG_RBTREE_TEST=m CONFIG_REED_SOLOMON_TEST=m CONFIG_INTERVAL_TREE_TEST=m CONFIG_PERCPU_TEST=m CONFIG_ATOMIC64_SELFTEST=m CONFIG_ASYNC_RAID6_TEST=m CONFIG_TEST_HEXDUMP=m CONFIG_STRING_SELFTEST=m CONFIG_TEST_STRING_HELPERS=m # CONFIG_TEST_STRSCPY is not set CONFIG_TEST_KSTRTOX=m CONFIG_TEST_PRINTF=m CONFIG_TEST_SCANF=m CONFIG_TEST_BITMAP=m CONFIG_TEST_UUID=m CONFIG_TEST_XARRAY=m CONFIG_TEST_RHASHTABLE=m # CONFIG_TEST_SIPHASH is not set CONFIG_TEST_IDA=m CONFIG_TEST_PARMAN=m CONFIG_TEST_LKM=m CONFIG_TEST_BITOPS=m CONFIG_TEST_VMALLOC=m CONFIG_TEST_USER_COPY=m CONFIG_TEST_BPF=m CONFIG_TEST_BLACKHOLE_DEV=m CONFIG_FIND_BIT_BENCHMARK=m CONFIG_TEST_FIRMWARE=m CONFIG_TEST_SYSCTL=m CONFIG_BITFIELD_KUNIT=m CONFIG_HASH_KUNIT_TEST=m CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_SYSCTL_KUNIT_TEST=m CONFIG_LIST_KUNIT_TEST=m CONFIG_LINEAR_RANGES_TEST=m CONFIG_CMDLINE_KUNIT_TEST=m CONFIG_BITS_TEST=m CONFIG_SLUB_KUNIT_TEST=m CONFIG_RATIONAL_KUNIT_TEST=m CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_IS_SIGNED_TYPE_KUNIT_TEST=m CONFIG_OVERFLOW_KUNIT_TEST=m CONFIG_STACKINIT_KUNIT_TEST=m CONFIG_TEST_UDELAY=m CONFIG_TEST_STATIC_KEYS=m CONFIG_TEST_DYNAMIC_DEBUG=m CONFIG_TEST_KMOD=m CONFIG_TEST_MEMCAT_P=m CONFIG_TEST_OBJAGG=m CONFIG_TEST_MEMINIT=m CONFIG_TEST_FREE_PAGES=m # end of Kernel Testing and Coverage # # Rust hacking # # end of Rust hacking CONFIG_WARN_MISSING_DOCUMENTS=y CONFIG_WARN_ABI_ERRORS=y # end of Kernel hacking ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v11 2/6] media: chips-media: wave5: Add vpuapi layer [not found] <20221207121350.66217-1-sebastian.fricke@collabora.com> 2022-12-07 12:13 ` [PATCH v11 1/6] media: platform: chips-media: Move Coda to separate folder Sebastian Fricke @ 2022-12-07 12:13 ` Sebastian Fricke 2022-12-07 13:05 ` AngeloGioacchino Del Regno 2022-12-07 12:13 ` [PATCH v11 3/6] media: chips-media: wave5: Add the v4l2 layer Sebastian Fricke ` (3 subsequent siblings) 5 siblings, 1 reply; 22+ messages in thread From: Sebastian Fricke @ 2022-12-07 12:13 UTC (permalink / raw) To: linux-media, Nas Chung, Robert Beckett, Sebastian Fricke, Mauro Carvalho Chehab Cc: kernel, hverkuil-cisco, nicolas.dufresne, linux-kernel From: Nas Chung <nas.chung@chipsnmedia.com> Add the vpuapi layer of the wave5 codec driver. This layer is used to configure the hardware according to the parameters. Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com> --- .../platform/chips-media/wave5/wave5-hw.c | 3359 +++++++++++++++++ .../chips-media/wave5/wave5-regdefine.h | 743 ++++ .../platform/chips-media/wave5/wave5-vdi.c | 245 ++ .../platform/chips-media/wave5/wave5-vdi.h | 67 + .../platform/chips-media/wave5/wave5-vpuapi.c | 1040 +++++ .../platform/chips-media/wave5/wave5-vpuapi.h | 1136 ++++++ .../chips-media/wave5/wave5-vpuconfig.h | 90 + .../chips-media/wave5/wave5-vpuerror.h | 454 +++ .../media/platform/chips-media/wave5/wave5.h | 94 + 9 files changed, 7228 insertions(+) create mode 100644 drivers/media/platform/chips-media/wave5/wave5-hw.c create mode 100644 drivers/media/platform/chips-media/wave5/wave5-regdefine.h create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vdi.c create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vdi.h create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpuapi.c create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpuapi.h create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpuerror.h create mode 100644 drivers/media/platform/chips-media/wave5/wave5.h diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c new file mode 100644 index 000000000000..25705e61cdb3 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c @@ -0,0 +1,3359 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Wave5 series multi-standard codec IP - wave5 backend logic + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#include <linux/iopoll.h> +#include "wave5-vpu.h" +#include "wave5.h" +#include "wave5-regdefine.h" + +#define FIO_TIMEOUT 10000000 +#define FIO_CTRL_READY BIT(31) +#define FIO_CTRL_WRITE BIT(16) +#define VPU_BUSY_CHECK_TIMEOUT 10000000 +#define QUEUE_REPORT_MASK 0xffff + +static void wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason) +{ + char *caller = __builtin_return_address(0); + struct device *dev = vpu_dev->dev; + u32 reg_val; + + switch (reg_fail_reason) { + case WAVE5_SYSERR_QUEUEING_FAIL: + reg_val = vpu_read_reg(vpu_dev, W5_RET_QUEUE_FAIL_REASON); + dev_dbg(dev, "%s: queueing failure: 0x%x\n", caller, reg_val); + break; + case WAVE5_SYSERR_RESULT_NOT_READY: + dev_err(dev, "%s: result not ready: 0x%x\n", caller, reg_fail_reason); + break; + case WAVE5_SYSERR_ACCESS_VIOLATION_HW: + dev_err(dev, "%s: access violation: 0x%x\n", caller, reg_fail_reason); + break; + case WAVE5_SYSERR_WATCHDOG_TIMEOUT: + dev_err(dev, "%s: watchdog timeout: 0x%x\n", caller, reg_fail_reason); + break; + case WAVE5_SYSERR_BUS_ERROR: + dev_err(dev, "%s: bus error: 0x%x\n", caller, reg_fail_reason); + break; + case WAVE5_SYSERR_DOUBLE_FAULT: + dev_err(dev, "%s: double fault: 0x%x\n", caller, reg_fail_reason); + break; + case WAVE5_SYSERR_VPU_STILL_RUNNING: + dev_err(dev, "%s: still running: 0x%x\n", caller, reg_fail_reason); + break; + case WAVE5_SYSERR_VLC_BUF_FULL: + dev_err(dev, "%s: vlc buf full: 0x%x\n", caller, reg_fail_reason); + break; + default: + dev_err(dev, "%s: failure:: 0x%x\n", caller, reg_fail_reason); + break; + } +} + +static int wave5_wait_fio_readl(struct vpu_device *vpu_dev, u32 addr, u32 val) +{ + u32 ctrl; + int ret; + + ctrl = addr & 0xffff; + wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl); + ret = read_poll_timeout(wave5_vdi_readl, ctrl, ctrl & FIO_CTRL_READY, + 0, FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR); + if (ret) + return ret; + if (wave5_vdi_readl(vpu_dev, W5_VPU_FIO_DATA) != val) + return -ETIMEDOUT; + return 0; +} + +static void wave5_fio_writel(struct vpu_device *vpu_dev, unsigned int addr, unsigned int data) +{ + int ret; + unsigned int ctrl; + + wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_DATA, data); + ctrl = FIO_CTRL_WRITE | (addr & 0xffff); + wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl); + ret = read_poll_timeout(wave5_vdi_readl, ctrl, ctrl & FIO_CTRL_READY, 0, FIO_TIMEOUT, + false, vpu_dev, W5_VPU_FIO_CTRL_ADDR); + if (ret) { + dev_dbg_ratelimited(vpu_dev->dev, "FIO write timeout: addr=0x%x data=%x\n", + ctrl, data); + } +} + +static int wave5_wait_bus_busy(struct vpu_device *vpu_dev, unsigned int addr) +{ + u32 gdi_status_check_value = 0x3f; + + if (vpu_dev->product_code == WAVE521C_CODE || + vpu_dev->product_code == WAVE521_CODE || + vpu_dev->product_code == WAVE521E1_CODE) + gdi_status_check_value = 0x00ff1f3f; + + return wave5_wait_fio_readl(vpu_dev, addr, gdi_status_check_value); +} + +static int wave5_wait_vpu_busy(struct vpu_device *vpu_dev, unsigned int addr) +{ + u32 data; + + return read_poll_timeout(wave5_vdi_readl, data, data == 0, + 0, VPU_BUSY_CHECK_TIMEOUT, false, vpu_dev, addr); +} + +static int wave5_wait_vcpu_bus_busy(struct vpu_device *vpu_dev, unsigned int addr) +{ + return wave5_wait_fio_readl(vpu_dev, addr, 0); +} + +bool wave5_vpu_is_init(struct vpu_device *vpu_dev) +{ + return vpu_read_reg(vpu_dev, W5_VCPU_CUR_PC) != 0; +} + +unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev) +{ + unsigned int product_id = PRODUCT_ID_NONE; + u32 val; + + val = vpu_read_reg(vpu_dev, W5_PRODUCT_NUMBER); + + switch (val) { + case WAVE521_CODE: + case WAVE521C_CODE: + case WAVE521C_DUAL_CODE: + case WAVE521E1_CODE: + product_id = PRODUCT_ID_521; + break; + case WAVE511_CODE: + product_id = PRODUCT_ID_511; + break; + case WAVE517_CODE: + case WAVE537_CODE: + product_id = PRODUCT_ID_517; + break; + default: + dev_err(vpu_dev->dev, "Invalid product id (%x)\n", val); + break; + } + return product_id; +} + +void wave5_bit_issue_command(struct vpu_instance *inst, u32 cmd) +{ + u32 instance_index = inst->id; + u32 codec_mode = inst->std; + + vpu_write_reg(inst->dev, W5_CMD_INSTANCE_INFO, (codec_mode << 16) | + (instance_index & 0xffff)); + vpu_write_reg(inst->dev, W5_VPU_BUSY_STATUS, 1); + vpu_write_reg(inst->dev, W5_COMMAND, cmd); + + dev_dbg(inst->dev->dev, "%s: cmd=0x%x\n", __func__, cmd); + + vpu_write_reg(inst->dev, W5_VPU_HOST_INT_REQ, 1); +} + +static int wave5_send_query(struct vpu_instance *inst, enum QUERY_OPT query_opt) +{ + int ret; + + vpu_write_reg(inst->dev, W5_QUERY_OPTION, query_opt); + vpu_write_reg(inst->dev, W5_VPU_BUSY_STATUS, 1); + wave5_bit_issue_command(inst, W5_QUERY); + + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_warn(inst->dev->dev, "command: 'W5_QUERY', timed out opt=0x%x\n", query_opt); + return ret; + } + + if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) + return -EIO; + + return 0; +} + +static int setup_wave5_properties(struct device *dev) +{ + struct vpu_device *vpu_dev = dev_get_drvdata(dev); + struct vpu_attr *p_attr = &vpu_dev->attr; + u32 reg_val; + u8 *str; + int ret; + u32 hw_config_def0, hw_config_def1, hw_config_feature, hw_config_rev; + + vpu_write_reg(vpu_dev, W5_QUERY_OPTION, GET_VPU_INFO); + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); + vpu_write_reg(vpu_dev, W5_COMMAND, W5_QUERY); + vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); + ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); + if (ret) + return ret; + + if (!vpu_read_reg(vpu_dev, W5_RET_SUCCESS)) + return -EIO; + + reg_val = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_NAME); + str = (u8 *)®_val; + p_attr->product_name[0] = str[3]; + p_attr->product_name[1] = str[2]; + p_attr->product_name[2] = str[1]; + p_attr->product_name[3] = str[0]; + p_attr->product_name[4] = 0; + + p_attr->product_id = wave5_vpu_get_product_id(vpu_dev); + p_attr->product_version = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_VERSION); + p_attr->fw_version = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); + p_attr->customer_id = vpu_read_reg(vpu_dev, W5_RET_CUSTOMER_ID); + hw_config_def0 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF0); + hw_config_def1 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF1); + hw_config_feature = vpu_read_reg(vpu_dev, W5_RET_CONF_FEATURE); + hw_config_rev = vpu_read_reg(vpu_dev, W5_RET_CONF_REVISION); + + p_attr->support_hevc10bit_enc = (hw_config_feature >> 3) & 1; + if (hw_config_rev > 167455) //20190321 + p_attr->support_avc10bit_enc = (hw_config_feature >> 11) & 1; + else + p_attr->support_avc10bit_enc = p_attr->support_hevc10bit_enc; + + p_attr->support_decoders = 0; + p_attr->support_encoders = 0; + if (p_attr->product_id == PRODUCT_ID_521) { + p_attr->support_dual_core = ((hw_config_def1 >> 26) & 0x01); + if (p_attr->support_dual_core || hw_config_rev < 206116) { + p_attr->support_decoders = BIT(STD_AVC); + p_attr->support_decoders |= BIT(STD_HEVC); + p_attr->support_encoders = BIT(STD_AVC); + p_attr->support_encoders |= BIT(STD_HEVC); + } else { + p_attr->support_decoders |= (((hw_config_def1 >> 3) & 0x01) << STD_AVC); + p_attr->support_decoders |= (((hw_config_def1 >> 2) & 0x01) << STD_HEVC); + p_attr->support_encoders = (((hw_config_def1 >> 1) & 0x01) << STD_AVC); + p_attr->support_encoders |= ((hw_config_def1 & 0x01) << STD_HEVC); + } + } else if (p_attr->product_id == PRODUCT_ID_511) { + p_attr->support_decoders = BIT(STD_HEVC); + p_attr->support_decoders |= BIT(STD_AVC); + } else if (p_attr->product_id == PRODUCT_ID_517) { + p_attr->support_decoders = (((hw_config_def1 >> 4) & 0x01) << STD_AV1); + p_attr->support_decoders |= (((hw_config_def1 >> 3) & 0x01) << STD_AVS2); + p_attr->support_decoders |= (((hw_config_def1 >> 2) & 0x01) << STD_AVC); + p_attr->support_decoders |= (((hw_config_def1 >> 1) & 0x01) << STD_VP9); + p_attr->support_decoders |= ((hw_config_def1 & 0x01) << STD_HEVC); + } + + p_attr->support_backbone = (hw_config_def0 >> 16) & 0x01; + p_attr->support_vcpu_backbone = (hw_config_def0 >> 28) & 0x01; + p_attr->support_vcore_backbone = (hw_config_def0 >> 22) & 0x01; + p_attr->support_dual_core = (hw_config_def1 >> 26) & 0x01; + p_attr->support_endian_mask = BIT(VDI_LITTLE_ENDIAN) | + BIT(VDI_BIG_ENDIAN) | + BIT(VDI_32BIT_LITTLE_ENDIAN) | + BIT(VDI_32BIT_BIG_ENDIAN) | + (0xffffUL << 16); + p_attr->support_bitstream_mode = BIT(BS_MODE_INTERRUPT) | + BIT(BS_MODE_PIC_END); + + return 0; +} + +int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision) +{ + u32 reg_val; + int ret; + + vpu_write_reg(vpu_dev, W5_QUERY_OPTION, GET_VPU_INFO); + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); + vpu_write_reg(vpu_dev, W5_COMMAND, W5_QUERY); + vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); + ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_err(vpu_dev->dev, "%s: timeout\n", __func__); + return ret; + } + + if (!vpu_read_reg(vpu_dev, W5_RET_SUCCESS)) { + dev_err(vpu_dev->dev, "%s: failed\n", __func__); + return -EIO; + } + + reg_val = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); + if (revision) + *revision = reg_val; + + return 0; +} + +static void remap_page(struct vpu_device *vpu_dev, dma_addr_t code_base, u32 index) +{ + u32 remap_size = (W5_REMAP_MAX_SIZE >> 12) & 0x1ff; + u32 reg_val = 0x80000000 | (WAVE5_UPPER_PROC_AXI_ID << 20) | (index << 12) | BIT(11) + | remap_size; + + vpu_write_reg(vpu_dev, W5_VPU_REMAP_CTRL, reg_val); + vpu_write_reg(vpu_dev, W5_VPU_REMAP_VADDR, index * W5_REMAP_MAX_SIZE); + vpu_write_reg(vpu_dev, W5_VPU_REMAP_PADDR, code_base + index * W5_REMAP_MAX_SIZE); +} + +int wave5_vpu_init(struct device *dev, u8 *fw, size_t size) +{ + struct vpu_buf *common_vb; + struct dma_vpu_buf *sram_vb; + dma_addr_t code_base, temp_base; + u32 code_size, temp_size; + u32 i, reg_val; + int ret; + struct vpu_device *vpu_dev = dev_get_drvdata(dev); + + common_vb = &vpu_dev->common_mem; + + code_base = common_vb->daddr; + /* ALIGN TO 4KB */ + code_size = (WAVE5_MAX_CODE_BUF_SIZE & ~0xfff); + if (code_size < size * 2) + return -EINVAL; + + temp_base = common_vb->daddr + WAVE5_TEMPBUF_OFFSET; + temp_size = WAVE5_TEMPBUF_SIZE; + + ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size, VDI_128BIT_LITTLE_ENDIAN); + if (ret < 0) { + dev_err(vpu_dev->dev, "VPU init, Writing firmware to common buffer, fail: %d\n", + ret); + return ret; + } + + vpu_write_reg(vpu_dev, W5_PO_CONF, 0); + + /* clear registers */ + + for (i = W5_CMD_REG_BASE; i < W5_CMD_REG_END; i += 4) + vpu_write_reg(vpu_dev, i, 0x00); + + remap_page(vpu_dev, code_base, W5_REMAP_INDEX0); + remap_page(vpu_dev, code_base, W5_REMAP_INDEX1); + + vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base); + vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size); + vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0); + vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base); + vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size); + + vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); + + reg_val = (WAVE5_PROC_AXI_EXT_ADDR & 0xFFFF); + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, reg_val); + reg_val = ((WAVE5_PROC_AXI_AXPROT & 0x7) << 4) | + (WAVE5_PROC_AXI_AXCACHE & 0xF); + wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, reg_val); + reg_val = ((WAVE5_SEC_AXI_AXPROT & 0x7) << 20) | + ((WAVE5_SEC_AXI_AXCACHE & 0xF) << 16) | + (WAVE5_SEC_AXI_EXT_ADDR & 0xFFFF); + vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, reg_val); + + /* interrupt */ + // encoder + reg_val = BIT(INT_WAVE5_ENC_SET_PARAM); + reg_val |= BIT(INT_WAVE5_ENC_PIC); + reg_val |= BIT(INT_WAVE5_BSBUF_FULL); + // decoder + reg_val |= BIT(INT_WAVE5_INIT_SEQ); + reg_val |= BIT(INT_WAVE5_DEC_PIC); + reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); + vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); + + reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); + if ((reg_val >> 16) & 1) { + reg_val = ((WAVE5_PROC_AXI_ID << 28) | + (WAVE5_PRP_AXI_ID << 24) | + (WAVE5_FBD_Y_AXI_ID << 20) | + (WAVE5_FBC_Y_AXI_ID << 16) | + (WAVE5_FBD_C_AXI_ID << 12) | + (WAVE5_FBC_C_AXI_ID << 8) | + (WAVE5_PRI_AXI_ID << 4) | + WAVE5_SEC_AXI_ID); + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); + } + + sram_vb = &vpu_dev->sram_buf; + + vpu_write_reg(vpu_dev, W5_ADDR_SEC_AXI, sram_vb->daddr); + vpu_write_reg(vpu_dev, W5_SEC_AXI_SIZE, sram_vb->size); + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); + vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU); + vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); + ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_err(vpu_dev->dev, "VPU init(W5_VPU_REMAP_CORE_START) timeout\n"); + return ret; + } + + reg_val = vpu_read_reg(vpu_dev, W5_RET_SUCCESS); + if (!reg_val) { + u32 reason_code = vpu_read_reg(vpu_dev, W5_RET_FAIL_REASON); + + wave5_print_reg_err(vpu_dev, reason_code); + return -EIO; + } + + return setup_wave5_properties(dev); +} + +int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, + struct dec_open_param *param) +{ + int ret; + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + u32 bs_endian; + struct dma_vpu_buf *sram_vb; + struct vpu_device *vpu_dev = inst->dev; + + p_dec_info->cycle_per_tick = 256; + switch (inst->std) { + case W_HEVC_DEC: + p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_HEVC; + break; + case W_VP9_DEC: + p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_VP9; + break; + case W_AVS2_DEC: + p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVS2; + break; + case W_AVC_DEC: + p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVC; + break; + case W_AV1_DEC: + p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AV1; + break; + default: + return -EINVAL; + } + + if (vpu_dev->product == PRODUCT_ID_517) + p_dec_info->vb_work.size = WAVE517_WORKBUF_SIZE; + else if (vpu_dev->product == PRODUCT_ID_521) + p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; + else if (vpu_dev->product == PRODUCT_ID_511) + p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; + + ret = wave5_vdi_allocate_dma_memory(inst->dev, &p_dec_info->vb_work); + if (ret) + return ret; + + vpu_write_reg(inst->dev, W5_CMD_DEC_VCORE_INFO, 1); + + sram_vb = &vpu_dev->sram_buf; + p_dec_info->sec_axi_info.buf_base = sram_vb->daddr; + p_dec_info->sec_axi_info.buf_size = sram_vb->size; + + wave5_vdi_clear_memory(inst->dev, &p_dec_info->vb_work); + + vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_dec_info->vb_work.daddr); + vpu_write_reg(inst->dev, W5_WORK_SIZE, p_dec_info->vb_work.size); + + vpu_write_reg(inst->dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info->stream_buf_start_addr); + vpu_write_reg(inst->dev, W5_CMD_DEC_BS_SIZE, p_dec_info->stream_buf_size); + + /* NOTE: when endian mode is 0, SDMA reads MSB first */ + bs_endian = wave5_vdi_convert_endian(inst->dev, param->stream_endian); + bs_endian = (~bs_endian & VDI_128BIT_ENDIAN_MASK); + vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, bs_endian); + vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, (param->pri_axprot << 20) | + (param->pri_axcache << 16) | param->pri_ext_addr); + vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, (COMMAND_QUEUE_DEPTH - 1)); + vpu_write_reg(inst->dev, W5_CMD_ERR_CONCEAL, (param->error_conceal_unit << 2) | + (param->error_conceal_mode)); + + wave5_bit_issue_command(inst, W5_CREATE_INSTANCE); + // check QUEUE_DONE + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_warn(inst->dev->dev, "command: 'W5_CREATE_INSTANCE' timed out\n"); + goto free_vb_work; + } + + // Check if we were able to add the parameters into the VCPU QUEUE + if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { + ret = -EIO; + goto free_vb_work; + } + + p_dec_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); + + return 0; +free_vb_work: + wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); + return ret; +} + +int wave5_vpu_dec_init_seq(struct vpu_instance *inst) +{ + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + u32 cmd_option = INIT_SEQ_NORMAL; + u32 reg_val, bs_option; + int ret; + + if (!inst->codec_info) + return -EINVAL; + + if (p_dec_info->thumbnail_mode) + cmd_option = INIT_SEQ_W_THUMBNAIL; + + /* set attributes of bitstream buffer controller */ + switch (p_dec_info->open_param.bitstream_mode) { + case BS_MODE_INTERRUPT: + bs_option = BSOPTION_ENABLE_EXPLICIT_END; + break; + case BS_MODE_PIC_END: + bs_option = BSOPTION_ENABLE_EXPLICIT_END; + break; + default: + return -EINVAL; + } + + vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); + vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); + + if (p_dec_info->stream_endflag) + bs_option = 3; + if (inst->std == W_AV1_DEC) + bs_option |= ((p_dec_info->open_param.av1_format) << 2); + vpu_write_reg(inst->dev, W5_BS_OPTION, BIT(31) | bs_option); + + vpu_write_reg(inst->dev, W5_COMMAND_OPTION, cmd_option); + vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); + + wave5_bit_issue_command(inst, W5_INIT_SEQ); + + // check QUEUE_DONE + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_warn(inst->dev->dev, "command: 'W5_INIT_SEQ', timed out\n"); + return ret; + } + + reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); + + p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; + p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); + + // Check if we were able to add a command into VCPU QUEUE + if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { + reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + wave5_print_reg_err(inst->dev, reg_val); + return -EIO; + } + + return 0; +} + +static void wave5_get_dec_seq_result(struct vpu_instance *inst, struct dec_initial_info *info) +{ + u32 reg_val, sub_layer_info; + u32 profile_compatibility_flag; + u32 output_bit_depth_minus8; + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + + p_dec_info->stream_rd_ptr = wave5_vpu_dec_get_rd_ptr(inst); + info->rd_ptr = p_dec_info->stream_rd_ptr; + + p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); + + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); + info->pic_width = ((reg_val >> 16) & 0xffff); + info->pic_height = (reg_val & 0xffff); + info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REQUIRED_FB); + info->frame_buf_delay = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REORDER_DELAY); + + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_LEFT_RIGHT); + info->pic_crop_rect.left = (reg_val >> 16) & 0xffff; + info->pic_crop_rect.right = reg_val & 0xffff; + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_TOP_BOTTOM); + info->pic_crop_rect.top = (reg_val >> 16) & 0xffff; + info->pic_crop_rect.bottom = reg_val & 0xffff; + + info->f_rate_numerator = vpu_read_reg(inst->dev, W5_RET_DEC_FRAME_RATE_NR); + info->f_rate_denominator = vpu_read_reg(inst->dev, W5_RET_DEC_FRAME_RATE_DR); + + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_COLOR_SAMPLE_INFO); + info->luma_bitdepth = reg_val & 0xf; + info->chroma_bitdepth = (reg_val >> 4) & 0xf; + info->chroma_format_idc = (reg_val >> 8) & 0xf; + info->aspect_rate_info = (reg_val >> 16) & 0xff; + info->is_ext_sar = ((info->aspect_rate_info == 255) ? true : false); + /* [0:15] - vertical size, [16:31] - horizontal size */ + if (info->is_ext_sar) + info->aspect_rate_info = vpu_read_reg(inst->dev, W5_RET_DEC_ASPECT_RATIO); + info->bit_rate = vpu_read_reg(inst->dev, W5_RET_DEC_BIT_RATE); + + sub_layer_info = vpu_read_reg(inst->dev, W5_RET_DEC_SUB_LAYER_INFO); + info->max_temporal_layers = (sub_layer_info >> 8) & 0x7; + + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_SEQ_PARAM); + info->level = reg_val & 0xff; + profile_compatibility_flag = (reg_val >> 12) & 0xff; + info->profile = (reg_val >> 24) & 0x1f; + info->tier = (reg_val >> 29) & 0x01; + output_bit_depth_minus8 = (reg_val >> 30) & 0x03; + + if (inst->std == W_HEVC_DEC) { + /* guessing profile */ + if (!info->profile) { + if ((profile_compatibility_flag & 0x06) == 0x06) + info->profile = HEVC_PROFILE_MAIN; /* main profile */ + else if ((profile_compatibility_flag & 0x04) == 0x04) + info->profile = HEVC_PROFILE_MAIN10; /* main10 profile */ + else if ((profile_compatibility_flag & 0x08) == 0x08) + /* main still picture profile */ + info->profile = HEVC_PROFILE_STILLPICTURE; + else + info->profile = HEVC_PROFILE_MAIN; /* for old version HM */ + } + + } else if (inst->std == W_AVS2_DEC) { + if (info->luma_bitdepth == 10 && output_bit_depth_minus8 == 2) + info->output_bit_depth = 10; + else + info->output_bit_depth = 8; + + } else if (inst->std == W_AVC_DEC) { + info->profile = (reg_val >> 24) & 0x7f; + } + + info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); + info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); + p_dec_info->vlc_buf_size = info->vlc_buf_size; + p_dec_info->param_buf_size = info->param_buf_size; +} + +int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info) +{ + int ret; + u32 reg_val; + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + + vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); + vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); + vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, + VPU_USER_DATA_ENDIAN & VDI_128BIT_ENDIAN_MASK); + + // send QUERY cmd + ret = wave5_send_query(inst, GET_RESULT); + if (ret) { + if (ret == -EIO) { + reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + wave5_print_reg_err(inst->dev, reg_val); + } + return ret; + } + + dev_dbg(inst->dev->dev, "%s: init seq complete\n", __func__); + + reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); + + p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; + p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); + + /* this is not a fatal error, set ret to -EIO but don't return immediately */ + if (vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_SUCCESS) != 1) { + info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_DEC_ERR_INFO); + ret = -EIO; + } else { + info->warn_info = vpu_read_reg(inst->dev, W5_RET_DEC_WARN_INFO); + } + + // get sequence info + info->user_data_size = 0; + info->user_data_buf_full = false; + info->user_data_header = vpu_read_reg(inst->dev, W5_RET_DEC_USERDATA_IDC); + if (info->user_data_header) { + if (info->user_data_header & BIT(USERDATA_FLAG_BUFF_FULL)) + info->user_data_buf_full = true; + info->user_data_size = p_dec_info->user_data_buf_size; + } + + wave5_get_dec_seq_result(inst, info); + + return ret; +} + +static u32 calculate_table_size(u32 bit_depth, u32 frame_width, u32 frame_height, u32 ot_bg_width) +{ + u32 bgs_width = ((bit_depth > 8) ? 256 : 512); + u32 comp_frame_width = ALIGN(ALIGN(frame_width, 16) + 16, 16); + u32 ot_frame_width = ALIGN(comp_frame_width, ot_bg_width); + + // sizeof_offset_table() + u32 ot_bg_height = 32; + u32 bgs_height = BIT(14) / bgs_width / ((bit_depth > 8) ? 2 : 1); + u32 comp_frame_height = ALIGN(ALIGN(frame_height, 4) + 4, bgs_height); + u32 ot_frame_height = ALIGN(comp_frame_height, ot_bg_height); + + return (ot_frame_width / 16) * (ot_frame_height / 4) * 2; +} + +int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_buffer *fb_arr, + enum tiled_map_type map_type, unsigned int count) +{ + int ret; + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + struct dec_initial_info *init_info = &p_dec_info->initial_info; + size_t remain, idx, j, i, cnt_8_chunk; + u32 start_no, end_no; + u32 reg_val, cbcr_interleave, nv21, pic_size; + u32 endian, yuv_format; + u32 addr_y, addr_cb, addr_cr; + u32 table_width = init_info->pic_width; + u32 table_height = init_info->pic_height; + u32 mv_col_size, frame_width, frame_height, fbc_y_tbl_size, fbc_c_tbl_size; + struct vpu_buf vb_buf; + u32 color_format = 0; + u32 pixel_order = 1; + u32 bwb_flag = (map_type == LINEAR_FRAME_MAP) ? 1 : 0; + + cbcr_interleave = inst->cbcr_interleave; + nv21 = inst->nv21; + mv_col_size = 0; + fbc_y_tbl_size = 0; + fbc_c_tbl_size = 0; + + if (map_type >= COMPRESSED_FRAME_MAP) { + cbcr_interleave = 0; + nv21 = 0; + + switch (inst->std) { + case W_HEVC_DEC: + mv_col_size = WAVE5_DEC_HEVC_BUF_SIZE(init_info->pic_width, + init_info->pic_height); + break; + case W_VP9_DEC: + mv_col_size = WAVE5_DEC_VP9_BUF_SIZE(init_info->pic_width, + init_info->pic_height); + table_width = ALIGN(table_width, 64); + table_height = ALIGN(table_height, 64); + break; + case W_AVS2_DEC: + mv_col_size = WAVE5_DEC_AVS2_BUF_SIZE(init_info->pic_width, + init_info->pic_height); + break; + case W_AVC_DEC: + mv_col_size = WAVE5_DEC_AVC_BUF_SIZE(init_info->pic_width, + init_info->pic_height); + break; + case W_AV1_DEC: + mv_col_size = WAVE5_DEC_AV1_BUF_SZ_1(init_info->pic_width, + init_info->pic_height) + + WAVE5_DEC_AV1_BUF_SZ_2(init_info->pic_width, init_info->pic_width, + init_info->pic_height); + table_width = ALIGN(table_width, 16); + table_height = ALIGN(table_height, 8); + break; + default: + return -EINVAL; + } + + mv_col_size = ALIGN(mv_col_size, 16); + vb_buf.daddr = 0; + if (inst->std == W_HEVC_DEC || inst->std == W_AVS2_DEC || inst->std == + W_VP9_DEC || inst->std == W_AVC_DEC || inst->std == + W_AV1_DEC) { + vb_buf.size = ALIGN(mv_col_size, BUFFER_MARGIN) + BUFFER_MARGIN; + + for (i = 0 ; i < count ; i++) { + if (p_dec_info->vb_mv[i].size == 0) { + ret = wave5_vdi_allocate_dma_memory(inst->dev, &vb_buf); + if (ret) + goto free_mv_buffers; + p_dec_info->vb_mv[i] = vb_buf; + } + } + } + + frame_width = ALIGN(init_info->pic_width, 16); + frame_height = ALIGN(init_info->pic_height, 16); + if (p_dec_info->product_code == WAVE521C_DUAL_CODE) { + // Use a offset table BG width of 1024 for all decoders + fbc_y_tbl_size = calculate_table_size(init_info->luma_bitdepth, + frame_width, frame_height, 1024); + } else { + fbc_y_tbl_size = ALIGN(WAVE5_FBC_LUMA_TABLE_SIZE(table_width, + table_height), 16); + } + + vb_buf.daddr = 0; + vb_buf.size = ALIGN(fbc_y_tbl_size, BUFFER_MARGIN) + BUFFER_MARGIN; + for (i = 0 ; i < count ; i++) { + if (p_dec_info->vb_fbc_y_tbl[i].size == 0) { + ret = wave5_vdi_allocate_dma_memory(inst->dev, &vb_buf); + if (ret) + goto free_fbc_y_tbl_buffers; + p_dec_info->vb_fbc_y_tbl[i] = vb_buf; + } + } + + if (p_dec_info->product_code == WAVE521C_DUAL_CODE) { + // Use a offset table BG width of 1024 for all decoders + fbc_c_tbl_size = calculate_table_size(init_info->chroma_bitdepth, + frame_width / 2, frame_height, 1024); + } else { + fbc_c_tbl_size = ALIGN(WAVE5_FBC_CHROMA_TABLE_SIZE(table_width, + table_height), 16); + } + + vb_buf.daddr = 0; + vb_buf.size = ALIGN(fbc_c_tbl_size, BUFFER_MARGIN) + BUFFER_MARGIN; + for (i = 0 ; i < count ; i++) { + if (p_dec_info->vb_fbc_c_tbl[i].size == 0) { + ret = wave5_vdi_allocate_dma_memory(inst->dev, &vb_buf); + if (ret) + goto free_fbc_c_tbl_buffers; + p_dec_info->vb_fbc_c_tbl[i] = vb_buf; + } + } + pic_size = (init_info->pic_width << 16) | (init_info->pic_height); + + // allocate task_buffer + vb_buf.size = (p_dec_info->vlc_buf_size * VLC_BUF_NUM) + + (p_dec_info->param_buf_size * COMMAND_QUEUE_DEPTH); + vb_buf.daddr = 0; + ret = wave5_vdi_allocate_dma_memory(inst->dev, &vb_buf); + if (ret) + goto free_fbc_c_tbl_buffers; + + p_dec_info->vb_task = vb_buf; + + vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, + p_dec_info->vb_task.daddr); + vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_buf.size); + } else { + pic_size = (init_info->pic_width << 16) | (init_info->pic_height); + } + endian = wave5_vdi_convert_endian(inst->dev, fb_arr[0].endian); + vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size); + + yuv_format = 0; + color_format = 0; + + reg_val = + (bwb_flag << 28) | + (pixel_order << 23) | /* PIXEL ORDER in 128bit. first pixel in low address */ + (yuv_format << 20) | + (color_format << 19) | + (nv21 << 17) | + (cbcr_interleave << 16) | + (fb_arr[0].stride); + vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, reg_val); + + remain = count; + cnt_8_chunk = ALIGN(count, 8) / 8; + idx = 0; + for (j = 0; j < cnt_8_chunk; j++) { + reg_val = (endian << 16) | (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); + reg_val |= (p_dec_info->open_param.enable_non_ref_fbc_write << 26); + vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val); + start_no = j * 8; + end_no = start_no + ((remain >= 8) ? 8 : remain) - 1; + + vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no); + + for (i = 0; i < 8 && i < remain; i++) { + if (map_type == LINEAR_FRAME_MAP && p_dec_info->open_param.cbcr_order == + CBCR_ORDER_REVERSED) { + addr_y = fb_arr[i + start_no].buf_y; + addr_cb = fb_arr[i + start_no].buf_cr; + addr_cr = fb_arr[i + start_no].buf_cb; + } else { + addr_y = fb_arr[i + start_no].buf_y; + addr_cb = fb_arr[i + start_no].buf_cb; + addr_cr = fb_arr[i + start_no].buf_cr; + } + vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), addr_y); + vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), addr_cb); + if (map_type >= COMPRESSED_FRAME_MAP) { + /* luma FBC offset table */ + vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4), + p_dec_info->vb_fbc_y_tbl[idx].daddr); + /* chroma FBC offset table */ + vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), + p_dec_info->vb_fbc_c_tbl[idx].daddr); + vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), + p_dec_info->vb_mv[idx].daddr); + } else { + vpu_write_reg(inst->dev, W5_ADDR_CR_BASE0 + (i << 4), addr_cr); + vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), 0); + vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), 0); + } + idx++; + } + remain -= i; + + wave5_bit_issue_command(inst, W5_SET_FB); + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + if (ret) + goto free_buffers; + } + + reg_val = vpu_read_reg(inst->dev, W5_RET_SUCCESS); + if (!reg_val) { + ret = -EIO; + goto free_buffers; + } + + return 0; + +free_buffers: + wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task); +free_fbc_c_tbl_buffers: + for (i = 0; i < count; i++) + wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_c_tbl[i]); +free_fbc_y_tbl_buffers: + for (i = 0; i < count; i++) + wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_y_tbl[i]); +free_mv_buffers: + for (i = 0; i < count; i++) + wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_mv[i]); + return ret; +} + +int wave5_vpu_decode(struct vpu_instance *inst, struct dec_param *option, u32 *fail_res) +{ + u32 mode_option = DEC_PIC_NORMAL, bs_option, reg_val; + u32 force_latency = 0; + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + struct dec_open_param *p_open_param = &p_dec_info->open_param; + int ret; + + if (p_dec_info->thumbnail_mode) { + mode_option = DEC_PIC_W_THUMBNAIL; + } else if (option->skipframe_mode) { + switch (option->skipframe_mode) { + case WAVE_SKIPMODE_NON_IRAP: + mode_option = SKIP_NON_IRAP; + force_latency = 1; + break; + case WAVE_SKIPMODE_NON_REF: + mode_option = SKIP_NON_REF_PIC; + break; + default: + // skip mode off + break; + } + } + + // set disable reorder + if (!p_dec_info->reorder_enable) + force_latency = 1; + + /* set attributes of bitstream buffer controller */ + bs_option = 0; + switch (p_open_param->bitstream_mode) { + case BS_MODE_INTERRUPT: + bs_option = BSOPTION_ENABLE_EXPLICIT_END; + break; + case BS_MODE_PIC_END: + bs_option = BSOPTION_ENABLE_EXPLICIT_END; + break; + default: + return -EINVAL; + } + + vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); + vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); + bs_option = (p_dec_info->stream_endflag << 1) | BS_EXPLICIT_END_MODE_ON; + if (p_open_param->bitstream_mode == BS_MODE_PIC_END) + bs_option |= BIT(31); + if (inst->std == W_AV1_DEC) + bs_option |= ((p_open_param->av1_format) << 2); + vpu_write_reg(inst->dev, W5_BS_OPTION, bs_option); + + /* secondary AXI */ + reg_val = p_dec_info->sec_axi_info.wave.use_bit_enable | + (p_dec_info->sec_axi_info.wave.use_ip_enable << 9) | + (p_dec_info->sec_axi_info.wave.use_lf_row_enable << 15); + vpu_write_reg(inst->dev, W5_USE_SEC_AXI, reg_val); + + /* set attributes of user buffer */ + vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); + + vpu_write_reg(inst->dev, W5_COMMAND_OPTION, + ((option->disable_film_grain << 6) | (option->cra_as_bla_flag << 5) | + mode_option)); + vpu_write_reg(inst->dev, W5_CMD_DEC_TEMPORAL_ID_PLUS1, + (p_dec_info->target_spatial_id << 9) | + (p_dec_info->temp_id_select_mode << 8) | p_dec_info->target_temp_id); + vpu_write_reg(inst->dev, W5_CMD_SEQ_CHANGE_ENABLE_FLAG, p_dec_info->seq_change_mask); + vpu_write_reg(inst->dev, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, force_latency); + + wave5_bit_issue_command(inst, W5_DEC_PIC); + // check QUEUE_DONE + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_warn(inst->dev->dev, "command: 'W5_DEC_PIC', timed out\n"); + return -ETIMEDOUT; + } + + reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); + + p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; + p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); + // Check if we were able to add a command into the VCPU QUEUE + if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { + *fail_res = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + wave5_print_reg_err(inst->dev, *fail_res); + return -EIO; + } + + return 0; +} + +int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result) +{ + int ret; + u32 index, nal_unit_type, reg_val, sub_layer_info; + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + struct vpu_device *vpu_dev = inst->dev; + + vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); + vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); + vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, + VPU_USER_DATA_ENDIAN & VDI_128BIT_ENDIAN_MASK); + + // send QUERY cmd + ret = wave5_send_query(inst, GET_RESULT); + if (ret) { + if (ret == -EIO) { + reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + wave5_print_reg_err(inst->dev, reg_val); + } + + return ret; + } + + dev_dbg(inst->dev->dev, "%s: dec pic complete\n", __func__); + + reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); + + p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; + p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); + + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_TYPE); + + nal_unit_type = (reg_val >> 4) & 0x3f; + + if (inst->std == W_VP9_DEC) { + if (reg_val & 0x01) + result->pic_type = PIC_TYPE_I; + else if (reg_val & 0x02) + result->pic_type = PIC_TYPE_P; + else if (reg_val & 0x04) + result->pic_type = PIC_TYPE_REPEAT; + else + result->pic_type = PIC_TYPE_MAX; + } else if (inst->std == W_HEVC_DEC) { + if (reg_val & 0x04) + result->pic_type = PIC_TYPE_B; + else if (reg_val & 0x02) + result->pic_type = PIC_TYPE_P; + else if (reg_val & 0x01) + result->pic_type = PIC_TYPE_I; + else + result->pic_type = PIC_TYPE_MAX; + if ((nal_unit_type == 19 || nal_unit_type == 20) && result->pic_type == PIC_TYPE_I) + /* IDR_W_RADL, IDR_N_LP */ + result->pic_type = PIC_TYPE_IDR; + } else if (inst->std == W_AVC_DEC) { + if (reg_val & 0x04) + result->pic_type = PIC_TYPE_B; + else if (reg_val & 0x02) + result->pic_type = PIC_TYPE_P; + else if (reg_val & 0x01) + result->pic_type = PIC_TYPE_I; + else + result->pic_type = PIC_TYPE_MAX; + if (nal_unit_type == 5 && result->pic_type == PIC_TYPE_I) + result->pic_type = PIC_TYPE_IDR; + } else if (inst->std == W_AV1_DEC) { + switch (reg_val & 0x07) { + case 0: + result->pic_type = PIC_TYPE_KEY; + break; + case 1: + result->pic_type = PIC_TYPE_INTER; + break; + case 2: + result->pic_type = PIC_TYPE_AV1_INTRA; + break; + case 3: + result->pic_type = PIC_TYPE_AV1_SWITCH; + break; + default: + result->pic_type = PIC_TYPE_MAX; + break; + } + } else { // AVS2 + switch (reg_val & 0x07) { + case 0: + result->pic_type = PIC_TYPE_I; + break; + case 1: + result->pic_type = PIC_TYPE_P; + break; + case 2: + result->pic_type = PIC_TYPE_B; + break; + case 3: + result->pic_type = PIC_TYPE_AVS2_F; + break; + case 4: + result->pic_type = PIC_TYPE_AVS2_S; + break; + case 5: + result->pic_type = PIC_TYPE_AVS2_G; + break; + case 6: + result->pic_type = PIC_TYPE_AVS2_GB; + break; + default: + result->pic_type = PIC_TYPE_MAX; + break; + } + } + index = vpu_read_reg(inst->dev, W5_RET_DEC_DISPLAY_INDEX); + result->index_frame_display = index; + index = vpu_read_reg(inst->dev, W5_RET_DEC_DECODED_INDEX); + result->index_frame_decoded = index; + result->index_frame_decoded_for_tiled = index; + + sub_layer_info = vpu_read_reg(inst->dev, W5_RET_DEC_SUB_LAYER_INFO); + result->temporal_id = sub_layer_info & 0x7; + + if (inst->std == W_HEVC_DEC) { + result->decoded_poc = -1; + if (result->index_frame_decoded >= 0 || + result->index_frame_decoded == DECODED_IDX_FLAG_SKIP) + result->decoded_poc = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC); + } else if (inst->std == W_AVS2_DEC) { + result->avs2_info.decoded_poi = -1; + result->avs2_info.display_poi = -1; + if (result->index_frame_decoded >= 0) + result->avs2_info.decoded_poi = + vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC); + } else if (inst->std == W_AVC_DEC) { + result->decoded_poc = -1; + if (result->index_frame_decoded >= 0 || + result->index_frame_decoded == DECODED_IDX_FLAG_SKIP) + result->decoded_poc = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC); + } else if (inst->std == W_AV1_DEC) { + result->decoded_poc = -1; + if (result->index_frame_decoded >= 0 || + result->index_frame_decoded == DECODED_IDX_FLAG_SKIP) + result->decoded_poc = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC); + } + + result->sequence_changed = vpu_read_reg(inst->dev, W5_RET_DEC_NOTIFICATION); + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); + result->dec_pic_width = reg_val >> 16; + result->dec_pic_height = reg_val & 0xffff; + + if (result->sequence_changed) { + memcpy((void *)&p_dec_info->new_seq_info, (void *)&p_dec_info->initial_info, + sizeof(struct dec_initial_info)); + wave5_get_dec_seq_result(inst, &p_dec_info->new_seq_info); + } + + result->dec_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_DEC_HOST_CMD_TICK); + result->dec_decode_end_tick = vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_ENC_TICK); + + if (!p_dec_info->first_cycle_check) { + result->frame_cycle = + (result->dec_decode_end_tick - result->dec_host_cmd_tick) * + p_dec_info->cycle_per_tick; + vpu_dev->last_performance_cycles = result->dec_decode_end_tick; + p_dec_info->first_cycle_check = true; + } else if (result->index_frame_decoded_for_tiled != -1) { + result->frame_cycle = + (result->dec_decode_end_tick - vpu_dev->last_performance_cycles) * + p_dec_info->cycle_per_tick; + vpu_dev->last_performance_cycles = result->dec_decode_end_tick; + if (vpu_dev->last_performance_cycles < result->dec_host_cmd_tick) + result->frame_cycle = + (result->dec_decode_end_tick - result->dec_host_cmd_tick) * + p_dec_info->cycle_per_tick; + } + + // no remaining command. reset frame cycle. + if (p_dec_info->instance_queue_count == 0 && p_dec_info->report_queue_count == 0) + p_dec_info->first_cycle_check = false; + + return 0; +} + +int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) +{ + struct vpu_buf *common_vb; + dma_addr_t code_base, temp_base; + dma_addr_t old_code_base, temp_size; + u32 code_size; + u32 reg_val; + struct vpu_device *vpu_dev = dev_get_drvdata(dev); + + common_vb = &vpu_dev->common_mem; + + code_base = common_vb->daddr; + /* ALIGN TO 4KB */ + code_size = (WAVE5_MAX_CODE_BUF_SIZE & ~0xfff); + if (code_size < size * 2) + return -EINVAL; + temp_base = common_vb->daddr + WAVE5_TEMPBUF_OFFSET; + temp_size = WAVE5_TEMPBUF_SIZE; + + old_code_base = vpu_read_reg(vpu_dev, W5_VPU_REMAP_PADDR); + + if (old_code_base != code_base + W5_REMAP_INDEX1 * W5_REMAP_MAX_SIZE) { + int ret; + struct dma_vpu_buf *sram_vb; + + ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size, + VDI_128BIT_LITTLE_ENDIAN); + if (ret < 0) { + dev_err(vpu_dev->dev, + "VPU init, Writing firmware to common buffer, fail: %d\n", ret); + return ret; + } + + vpu_write_reg(vpu_dev, W5_PO_CONF, 0); + + ret = wave5_vpu_reset(dev, SW_RESET_ON_BOOT); + if (ret < 0) { + dev_err(vpu_dev->dev, "VPU init, Resetting the VPU, fail: %d\n", ret); + return ret; + } + + remap_page(vpu_dev, code_base, W5_REMAP_INDEX0); + remap_page(vpu_dev, code_base, W5_REMAP_INDEX1); + + vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base); + vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size); + vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0); + vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base); + vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size); + + vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); + + reg_val = (WAVE5_PROC_AXI_EXT_ADDR & 0xFFFF); + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, reg_val); + reg_val = ((WAVE5_PROC_AXI_AXPROT & 0x7) << 4) | + (WAVE5_PROC_AXI_AXCACHE & 0xF); + wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, reg_val); + reg_val = ((WAVE5_SEC_AXI_AXPROT & 0x7) << 20) | + ((WAVE5_SEC_AXI_AXCACHE & 0xF) << 16) | + (WAVE5_SEC_AXI_EXT_ADDR & 0xFFFF); + vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, reg_val); + + /* interrupt */ + // encoder + reg_val = BIT(INT_WAVE5_ENC_SET_PARAM); + reg_val |= BIT(INT_WAVE5_ENC_PIC); + reg_val |= BIT(INT_WAVE5_BSBUF_FULL); + // decoder + reg_val |= BIT(INT_WAVE5_INIT_SEQ); + reg_val |= BIT(INT_WAVE5_DEC_PIC); + reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); + vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); + + reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); + if ((reg_val >> 16) & 1) { + reg_val = ((WAVE5_PROC_AXI_ID << 28) | + (WAVE5_PRP_AXI_ID << 24) | + (WAVE5_FBD_Y_AXI_ID << 20) | + (WAVE5_FBC_Y_AXI_ID << 16) | + (WAVE5_FBD_C_AXI_ID << 12) | + (WAVE5_FBC_C_AXI_ID << 8) | + (WAVE5_PRI_AXI_ID << 4) | + WAVE5_SEC_AXI_ID); + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); + } + + sram_vb = &vpu_dev->sram_buf; + + vpu_write_reg(vpu_dev, W5_ADDR_SEC_AXI, sram_vb->daddr); + vpu_write_reg(vpu_dev, W5_SEC_AXI_SIZE, sram_vb->size); + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); + vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU); + vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); + + ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_err(vpu_dev->dev, "VPU reinit(W5_VPU_REMAP_CORE_START) timeout\n"); + return ret; + } + + reg_val = vpu_read_reg(vpu_dev, W5_RET_SUCCESS); + if (!reg_val) { + u32 reason_code = vpu_read_reg(vpu_dev, W5_RET_FAIL_REASON); + + wave5_print_reg_err(vpu_dev, reason_code); + return -EIO; + } + } + + return setup_wave5_properties(dev); +} + +static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uint16_t *code, + size_t size) +{ + u32 reg_val; + struct vpu_buf *common_vb; + dma_addr_t code_base; + u32 code_size; + struct vpu_device *vpu_dev = dev_get_drvdata(dev); + int ret; + + if (i_sleep_wake) { + ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); + if (ret) + return ret; + + /* + * Declare who has ownership for the host interface access + * 1 = VPU + * 0 = Host processer + */ + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); + vpu_write_reg(vpu_dev, W5_COMMAND, W5_SLEEP_VPU); + /* Send an interrupt named HOST to the VPU */ + vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); + + ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); + if (ret) + return ret; + + if (!vpu_read_reg(vpu_dev, W5_RET_SUCCESS)) { + u32 reason = vpu_read_reg(vpu_dev, W5_RET_FAIL_REASON); + + wave5_print_reg_err(vpu_dev, reason); + return -EIO; + } + } else { /* restore */ + common_vb = &vpu_dev->common_mem; + + code_base = common_vb->daddr; + /* ALIGN TO 4KB */ + code_size = (WAVE5_MAX_CODE_BUF_SIZE & ~0xfff); + if (code_size < size * 2) { + dev_err(dev, "size too small\n"); + return -EINVAL; + } + + /* Power on without DEBUG mode */ + vpu_write_reg(vpu_dev, W5_PO_CONF, 0); + + remap_page(vpu_dev, code_base, W5_REMAP_INDEX0); + remap_page(vpu_dev, code_base, W5_REMAP_INDEX1); + + vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base); + vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size); + vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0); + + vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); + + reg_val = (WAVE5_PROC_AXI_EXT_ADDR & 0xFFFF); + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, reg_val); + reg_val = ((WAVE5_PROC_AXI_AXPROT & 0x7) << 4) | + (WAVE5_PROC_AXI_AXCACHE & 0xF); + wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, reg_val); + reg_val = ((WAVE5_SEC_AXI_AXPROT & 0x7) << 20) | + ((WAVE5_SEC_AXI_AXCACHE & 0xF) << 16) | + (WAVE5_SEC_AXI_EXT_ADDR & 0xFFFF); + vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, reg_val); + + /* interrupt */ + // encoder + reg_val = BIT(INT_WAVE5_ENC_SET_PARAM); + reg_val |= BIT(INT_WAVE5_ENC_PIC); + reg_val |= BIT(INT_WAVE5_BSBUF_FULL); + // decoder + reg_val |= BIT(INT_WAVE5_INIT_SEQ); + reg_val |= BIT(INT_WAVE5_DEC_PIC); + reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); + vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); + + reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); + if ((reg_val >> 16) & 1) { + reg_val = ((WAVE5_PROC_AXI_ID << 28) | + (WAVE5_PRP_AXI_ID << 24) | + (WAVE5_FBD_Y_AXI_ID << 20) | + (WAVE5_FBC_Y_AXI_ID << 16) | + (WAVE5_FBD_C_AXI_ID << 12) | + (WAVE5_FBC_C_AXI_ID << 8) | + (WAVE5_PRI_AXI_ID << 4) | + WAVE5_SEC_AXI_ID); + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); + } + + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); + vpu_write_reg(vpu_dev, W5_COMMAND, W5_WAKEUP_VPU); + /* Start VPU after settings */ + vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); + + ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_err(vpu_dev->dev, "VPU wakeup(W5_VPU_REMAP_CORE_START) timeout\n"); + return ret; + } + + reg_val = vpu_read_reg(vpu_dev, W5_RET_SUCCESS); + if (!reg_val) { + u32 reason_code = vpu_read_reg(vpu_dev, W5_RET_FAIL_REASON); + + wave5_print_reg_err(vpu_dev, reason_code); + return -EIO; + } + } + + return 0; +} + +int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode) +{ + u32 val = 0; + int ret = 0; + struct vpu_device *vpu_dev = dev_get_drvdata(dev); + struct vpu_attr *p_attr = &vpu_dev->attr; + // VPU doesn't send response. force to set BUSY flag to 0. + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 0); + + if (reset_mode == SW_RESET_SAFETY) { + ret = wave5_vpu_sleep_wake(dev, true, NULL, 0); + if (ret) + return ret; + } + + val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); + if ((val >> 16) & 0x1) + p_attr->support_backbone = true; + if ((val >> 22) & 0x1) + p_attr->support_vcore_backbone = true; + if ((val >> 28) & 0x1) + p_attr->support_vcpu_backbone = true; + + val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG1); + if ((val >> 26) & 0x1) + p_attr->support_dual_core = true; + + // waiting for completion of bus transaction + if (p_attr->support_backbone) { + dev_dbg(dev, "%s: backbone supported\n", __func__); + + if (p_attr->support_dual_core) { + // check CORE0 + wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7); + + ret = wave5_wait_bus_busy(vpu_dev, W5_BACKBONE_BUS_STATUS_VCORE0); + if (ret) { + wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00); + return ret; + } + + // check CORE1 + wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE1, 0x7); + + ret = wave5_wait_bus_busy(vpu_dev, W5_BACKBONE_BUS_STATUS_VCORE1); + if (ret) { + wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE1, 0x00); + return ret; + } + + } else if (p_attr->support_vcore_backbone) { + if (p_attr->support_vcpu_backbone) { + // step1 : disable request + wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0xFF); + + // step2 : waiting for completion of bus transaction + ret = wave5_wait_vcpu_bus_busy(vpu_dev, + W5_BACKBONE_BUS_STATUS_VCPU); + if (ret) { + wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0x00); + return ret; + } + } + // step1 : disable request + wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7); + + // step2 : waiting for completion of bus transaction + if (wave5_wait_bus_busy(vpu_dev, W5_BACKBONE_BUS_STATUS_VCORE0)) { + wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00); + return -EBUSY; + } + } else { + // step1 : disable request + wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x7); + + // step2 : waiting for completion of bus transaction + if (wave5_wait_bus_busy(vpu_dev, W5_COMBINED_BACKBONE_BUS_STATUS)) { + wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00); + return -EBUSY; + } + } + } else { + dev_dbg(dev, "%s: backbone NOT supported\n", __func__); + // step1 : disable request + wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x100); + + // step2 : waiting for completion of bus transaction + ret = wave5_wait_bus_busy(vpu_dev, W5_GDI_BUS_STATUS); + if (ret) { + wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x00); + return ret; + } + } + + switch (reset_mode) { + case SW_RESET_ON_BOOT: + case SW_RESET_FORCE: + case SW_RESET_SAFETY: + val = W5_RST_BLOCK_ALL; + break; + default: + return -EINVAL; + } + + if (val) { + vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, val); + + ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_RESET_STATUS); + if (ret) { + vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0); + return ret; + } + vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0); + } + // step3 : must clear GDI_BUS_CTRL after done SW_RESET + if (p_attr->support_backbone) { + if (p_attr->support_dual_core) { + wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00); + wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE1, 0x00); + } else if (p_attr->support_vcore_backbone) { + if (p_attr->support_vcpu_backbone) + wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0x00); + wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00); + } else { + wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00); + } + } else { + wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x00); + } + if (reset_mode == SW_RESET_SAFETY || reset_mode == SW_RESET_FORCE) + ret = wave5_vpu_sleep_wake(dev, false, NULL, 0); + + return ret; +} + +int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res) +{ + int ret; + + wave5_bit_issue_command(inst, W5_DESTROY_INSTANCE); + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + if (ret) + return -ETIMEDOUT; + + if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { + *fail_res = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + wave5_print_reg_err(inst->dev, *fail_res); + return -EIO; + } + + return 0; +} + +int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos) +{ + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + enum bit_stream_mode bs_mode = (enum bit_stream_mode)p_dec_info->open_param.bitstream_mode; + + p_dec_info->stream_endflag = eos ? 1 : 0; + + if (bs_mode == BS_MODE_INTERRUPT) { + int ret; + + vpu_write_reg(inst->dev, W5_BS_OPTION, (p_dec_info->stream_endflag << 1) | + p_dec_info->stream_endflag); + vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); + + wave5_bit_issue_command(inst, W5_UPDATE_BS); + ret = wave5_wait_vpu_busy(inst->dev, + W5_VPU_BUSY_STATUS); + if (ret) + return ret; + + if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) + return -EIO; + } + + return 0; +} + +int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index) +{ + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + int ret; + + vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, BIT(index)); + vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, 0); + ret = wave5_send_query(inst, UPDATE_DISP_FLAG); + + if (ret) { + if (ret == -EIO) { + u32 reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + + wave5_print_reg_err(inst->dev, reg_val); + } + return ret; + } + + p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); + + return 0; +} + +int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index) +{ + int ret; + + vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, 0); + vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, BIT(index)); + ret = wave5_send_query(inst, UPDATE_DISP_FLAG); + + if (ret) { + if (ret == -EIO) { + u32 reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + + wave5_print_reg_err(inst->dev, reg_val); + } + return ret; + } + + return 0; +} + +int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags) +{ + u32 interrupt_reason; + + interrupt_reason = vpu_read_reg(inst->dev, W5_VPU_VINT_REASON_USR); + interrupt_reason &= ~flags; + vpu_write_reg(inst->dev, W5_VPU_VINT_REASON_USR, interrupt_reason); + + return 0; +} + +dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst) +{ + int ret; + + ret = wave5_send_query(inst, GET_BS_RD_PTR); + + if (ret) + return inst->codec_info->dec_info.stream_rd_ptr; + + return vpu_read_reg(inst->dev, W5_RET_QUERY_DEC_BS_RD_PTR); +} + +int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr) +{ + int ret; + + vpu_write_reg(inst->dev, W5_RET_QUERY_DEC_SET_BS_RD_PTR, addr); + + ret = wave5_send_query(inst, SET_BS_RD_PTR); + + return ret; +} + +/************************************************************************/ +/* ENCODER functions */ +/************************************************************************/ + +int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst, + struct enc_open_param *open_param) +{ + int ret; + struct enc_info *p_enc_info = &inst->codec_info->enc_info; + u32 reg_val; + struct dma_vpu_buf *sram_vb; + u32 bs_endian; + struct vpu_device *vpu_dev = dev_get_drvdata(dev); + dma_addr_t buffer_addr; + size_t buffer_size; + + p_enc_info->cycle_per_tick = 256; + sram_vb = &vpu_dev->sram_buf; + p_enc_info->sec_axi_info.buf_base = sram_vb->daddr; + p_enc_info->sec_axi_info.buf_size = sram_vb->size; + + if (vpu_dev->product == PRODUCT_ID_521) + p_enc_info->vb_work.size = WAVE521ENC_WORKBUF_SIZE; + + ret = wave5_vdi_allocate_dma_memory(vpu_dev, &p_enc_info->vb_work); + if (ret) { + memset(&p_enc_info->vb_work, 0, sizeof(p_enc_info->vb_work)); + return ret; + } + + wave5_vdi_clear_memory(vpu_dev, &p_enc_info->vb_work); + + vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_enc_info->vb_work.daddr); + vpu_write_reg(inst->dev, W5_WORK_SIZE, p_enc_info->vb_work.size); + + reg_val = wave5_vdi_convert_endian(vpu_dev, open_param->stream_endian); + bs_endian = (~reg_val & VDI_128BIT_ENDIAN_MASK); + + reg_val = (open_param->line_buf_int_en << 6) | bs_endian; + vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, reg_val); + vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, (open_param->pri_axprot << 20) | + (open_param->pri_axcache << 16) | open_param->pri_ext_addr); + vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, (COMMAND_QUEUE_DEPTH - 1)); + + reg_val = 0; + if (vpu_dev->product == PRODUCT_ID_521) + reg_val |= (open_param->sub_frame_sync_enable | + open_param->sub_frame_sync_mode << 1); + vpu_write_reg(inst->dev, W5_CMD_ENC_SRC_OPTIONS, reg_val); + + vpu_write_reg(inst->dev, W5_CMD_ENC_VCORE_INFO, 1); + + wave5_bit_issue_command(inst, W5_CREATE_INSTANCE); + // check QUEUE_DONE + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_warn(inst->dev->dev, "command: 'W5_CREATE_INSTANCE' timed out\n"); + goto free_vb_work; + } + + // Check if we were able to add the parameters into the VCPU QUEUE + if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { + reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + wave5_print_reg_err(inst->dev, reg_val); + ret = -EIO; + goto free_vb_work; + } + + buffer_addr = open_param->bitstream_buffer; + buffer_size = open_param->bitstream_buffer_size; + p_enc_info->sub_frame_sync_config.sub_frame_sync_mode = open_param->sub_frame_sync_mode; + p_enc_info->sub_frame_sync_config.sub_frame_sync_on = open_param->sub_frame_sync_enable; + p_enc_info->stream_rd_ptr = buffer_addr; + p_enc_info->stream_wr_ptr = buffer_addr; + p_enc_info->line_buf_int_en = open_param->line_buf_int_en; + p_enc_info->stream_buf_start_addr = buffer_addr; + p_enc_info->stream_buf_size = buffer_size; + p_enc_info->stream_buf_end_addr = buffer_addr + buffer_size; + p_enc_info->stride = 0; + p_enc_info->initial_info_obtained = false; + p_enc_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); + + return 0; +free_vb_work: + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_work); + return ret; +} + +static void wave5_set_enc_crop_info(u32 codec, struct enc_wave_param *param, int rot_mode, + int src_width, int src_height) +{ + int aligned_width = (codec == W_HEVC_ENC) ? ALIGN(src_width, 32) : ALIGN(src_width, 16); + int aligned_height = (codec == W_HEVC_ENC) ? ALIGN(src_height, 32) : ALIGN(src_height, 16); + int pad_right, pad_bot; + int crop_right, crop_left, crop_top, crop_bot; + int prp_mode = rot_mode >> 1; // remove prp_enable bit + + if (codec == W_HEVC_ENC && + (!rot_mode || prp_mode == 14)) // prp_mode 14 : hor_mir && ver_mir && rot_180 + return; + + pad_right = aligned_width - src_width; + pad_bot = aligned_height - src_height; + + if (param->conf_win_right > 0) + crop_right = param->conf_win_right + pad_right; + else + crop_right = pad_right; + + if (param->conf_win_bot > 0) + crop_bot = param->conf_win_bot + pad_bot; + else + crop_bot = pad_bot; + + crop_top = param->conf_win_top; + crop_left = param->conf_win_left; + + param->conf_win_top = crop_top; + param->conf_win_left = crop_left; + param->conf_win_bot = crop_bot; + param->conf_win_right = crop_right; + + if (prp_mode == 1 || prp_mode == 15) { + param->conf_win_top = crop_right; + param->conf_win_left = crop_top; + param->conf_win_bot = crop_left; + param->conf_win_right = crop_bot; + } else if (prp_mode == 2 || prp_mode == 12) { + param->conf_win_top = crop_bot; + param->conf_win_left = crop_right; + param->conf_win_bot = crop_top; + param->conf_win_right = crop_left; + } else if (prp_mode == 3 || prp_mode == 13) { + param->conf_win_top = crop_left; + param->conf_win_left = crop_bot; + param->conf_win_bot = crop_right; + param->conf_win_right = crop_top; + } else if (prp_mode == 4 || prp_mode == 10) { + param->conf_win_top = crop_bot; + param->conf_win_bot = crop_top; + } else if (prp_mode == 8 || prp_mode == 6) { + param->conf_win_left = crop_right; + param->conf_win_right = crop_left; + } else if (prp_mode == 5 || prp_mode == 11) { + param->conf_win_top = crop_left; + param->conf_win_left = crop_top; + param->conf_win_bot = crop_right; + param->conf_win_right = crop_bot; + } else if (prp_mode == 7 || prp_mode == 9) { + param->conf_win_top = crop_right; + param->conf_win_left = crop_bot; + param->conf_win_bot = crop_left; + param->conf_win_right = crop_top; + } +} + +int wave5_vpu_enc_init_seq(struct vpu_instance *inst) +{ + u32 reg_val = 0, rot_mir_mode, fixed_cu_size_mode = 0x7; + struct enc_info *p_enc_info = &inst->codec_info->enc_info; + struct enc_open_param *p_open_param = &p_enc_info->open_param; + struct enc_wave_param *p_param = &p_open_param->wave_param; + int ret; + + if (inst->dev->product != PRODUCT_ID_521) + return -EINVAL; + + /*==============================================*/ + /* OPT_CUSTOM_GOP */ + /*==============================================*/ + /* + * SET_PARAM + CUSTOM_GOP + * only when gop_preset_idx == custom_gop, custom_gop related registers should be set + */ + if (p_param->gop_preset_idx == PRESET_IDX_CUSTOM_GOP) { + int i = 0, j = 0; + + vpu_write_reg(inst->dev, W5_CMD_ENC_CUSTOM_GOP_PARAM, + p_param->gop_param.custom_gop_size); + for (i = 0; i < p_param->gop_param.custom_gop_size; i++) { + vpu_write_reg(inst->dev, W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 + (i * 4), + p_param->gop_param.pic_param[i].pic_type | + (p_param->gop_param.pic_param[i].poc_offset << 2) | + (p_param->gop_param.pic_param[i].pic_qp << 6) | + (p_param->gop_param.pic_param[i].use_multi_ref_p << 13) | + ((p_param->gop_param.pic_param[i].ref_poc_l0 & 0x1F) << 14) | + ((p_param->gop_param.pic_param[i].ref_poc_l1 & 0x1F) << 19) | + (p_param->gop_param.pic_param[i].temporal_id << 24)); + } + + for (j = i; j < MAX_GOP_NUM; j++) + vpu_write_reg(inst->dev, + W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 + (j * 4), 0); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_CUSTOM_GOP); + wave5_bit_issue_command(inst, W5_ENC_SET_PARAM); + + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_warn(inst->dev->dev, "command: 'W5_ENC_SET_PARAM', timed out op=0x%x\n", + OPT_CUSTOM_GOP); + return ret; + } + } + + /*======================================================================*/ + /* OPT_COMMON: */ + /* the last SET_PARAM command should be called with OPT_COMMON */ + /*======================================================================*/ + rot_mir_mode = 0; + if (p_enc_info->rotation_enable) { + switch (p_enc_info->rotation_angle) { + case 0: + rot_mir_mode |= NONE_ROTATE; + break; + case 90: + rot_mir_mode |= ROT_CLOCKWISE_90; + break; + case 180: + rot_mir_mode |= ROT_CLOCKWISE_180; + break; + case 270: + rot_mir_mode |= ROT_CLOCKWISE_270; + break; + } + } + + if (p_enc_info->mirror_enable) { + switch (p_enc_info->mirror_direction) { + case MIRDIR_NONE: + rot_mir_mode |= NONE_ROTATE; + break; + case MIRDIR_VER: + rot_mir_mode |= MIR_VER_FLIP; + break; + case MIRDIR_HOR: + rot_mir_mode |= MIR_HOR_FLIP; + break; + case MIRDIR_HOR_VER: + rot_mir_mode |= MIR_HOR_VER_FLIP; + break; + } + } + + wave5_set_enc_crop_info(inst->std, p_param, rot_mir_mode, p_open_param->pic_width, + p_open_param->pic_height); + + /* SET_PARAM + COMMON */ + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_COMMON); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SRC_SIZE, p_open_param->pic_height << 16 + | p_open_param->pic_width); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN, VDI_LITTLE_ENDIAN); + + if (inst->std == W_AVC_ENC) { + reg_val = p_param->profile | (p_param->level << 3) | + (p_param->internal_bit_depth << 14) | (p_param->use_long_term << 21); + if (p_param->scaling_list_enable == 2) { + reg_val |= BIT(22) | BIT(23); // [23]=USE_DEFAULT_SCALING_LIST + } else { // 0 or 1 + reg_val |= (p_param->scaling_list_enable << 22); + } + } else { // HEVC enc + reg_val = p_param->profile | + (p_param->level << 3) | + (p_param->tier << 12) | + (p_param->internal_bit_depth << 14) | + (p_param->use_long_term << 21) | + (p_param->tmvp_enable << 23) | + (p_param->sao_enable << 24) | + (p_param->skip_intra_trans << 25) | + (p_param->strong_intra_smooth_enable << 27) | + (p_param->en_still_picture << 30); + if (p_param->scaling_list_enable == 2) + reg_val |= BIT(22) | BIT(31); // [31]=USE_DEFAULT_SCALING_LIST + else + reg_val |= (p_param->scaling_list_enable << 22); + } + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val); + + reg_val = (p_param->lossless_enable) | + (p_param->const_intra_pred_flag << 1) | + (p_param->lf_cross_slice_boundary_enable << 2) | + (p_param->weight_pred_enable << 3) | + (p_param->wpp_enable << 4) | + (p_param->disable_deblk << 5) | + ((p_param->beta_offset_div2 & 0xF) << 6) | + ((p_param->tc_offset_div2 & 0xF) << 10) | + ((p_param->chroma_cb_qp_offset & 0x1F) << 14) | + ((p_param->chroma_cr_qp_offset & 0x1F) << 19) | + (p_param->transform8x8_enable << 29) | + (p_param->entropy_coding_mode << 30); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_PPS_PARAM, reg_val); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_GOP_PARAM, p_param->gop_preset_idx); + + if (inst->std == W_AVC_ENC) + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp | + ((p_param->intra_period & 0x7ff) << 6) | + ((p_param->avc_idr_period & 0x7ff) << 17) | + ((p_param->forced_idr_header_enable & 3) << 28)); + else + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, + p_param->decoding_refresh_type | (p_param->intra_qp << 3) | + (p_param->forced_idr_header_enable << 9) | + (p_param->intra_period << 16)); + + reg_val = (p_param->use_recommend_enc_param) | + (p_param->rdo_skip << 2) | + (p_param->lambda_scaling_enable << 3) | + (p_param->coef_clear_disable << 4) | + (fixed_cu_size_mode << 5) | + (p_param->intra_nx_n_enable << 8) | + (p_param->max_num_merge << 18) | + (p_param->custom_md_enable << 20) | + (p_param->custom_lambda_enable << 21) | + (p_param->monochrome_enable << 22); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RDO_PARAM, reg_val); + + if (inst->std == W_AVC_ENC) + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH, + p_param->intra_mb_refresh_arg << 16 | p_param->intra_mb_refresh_mode); + else + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH, + p_param->intra_refresh_arg << 16 | p_param->intra_refresh_mode); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_FRAME_RATE, p_open_param->frame_rate_info); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_TARGET_RATE, p_open_param->bit_rate); + + if (inst->std == W_AVC_ENC) + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_PARAM, + p_open_param->rc_enable | (p_param->mb_level_rc_enable << 1) | + (p_param->hvs_qp_enable << 2) | (p_param->hvs_qp_scale << 4) | + (p_param->bit_alloc_mode << 8) | (p_param->roi_enable << 13) | + ((p_param->initial_rc_qp & 0x3F) << 14) | + (p_open_param->vbv_buffer_size << 20)); + else + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_PARAM, + p_open_param->rc_enable | (p_param->cu_level_rc_enable << 1) | + (p_param->hvs_qp_enable << 2) | (p_param->hvs_qp_scale << 4) | + (p_param->bit_alloc_mode << 8) | (p_param->roi_enable << 13) | + ((p_param->initial_rc_qp & 0x3F) << 14) | + (p_open_param->vbv_buffer_size << 20)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM, + p_param->rc_weight_buf << 8 | p_param->rc_weight_param); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, p_param->min_qp_i | + (p_param->max_qp_i << 6) | (p_param->hvs_max_delta_qp << 12)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP, p_param->min_qp_p | + (p_param->max_qp_p << 6) | (p_param->min_qp_b << 12) | + (p_param->max_qp_b << 18)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, + (u32)p_param->fixed_bit_ratio[0] | + ((u32)p_param->fixed_bit_ratio[1] << 8) | + ((u32)p_param->fixed_bit_ratio[2] << 16) | + ((u32)p_param->fixed_bit_ratio[3] << 24)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, + (u32)p_param->fixed_bit_ratio[4] | + ((u32)p_param->fixed_bit_ratio[5] << 8) | + ((u32)p_param->fixed_bit_ratio[6] << 16) | + ((u32)p_param->fixed_bit_ratio[7] << 24)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_ROT_PARAM, rot_mir_mode); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM, (p_param->bg_detect_enable) | + (p_param->bg_thr_diff << 1) | (p_param->bg_thr_mean_diff << 10) | + (p_param->bg_lambda_qp << 18) | ((p_param->bg_delta_qp & 0x1F) << 24) | + ((inst->std == W_AVC_ENC) ? p_param->s2fme_disable << 29 : 0)); + + if (inst->std == W_HEVC_ENC || inst->std == W_AVC_ENC) { + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, + p_param->custom_lambda_addr); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT, + p_param->conf_win_bot << 16 | p_param->conf_win_top); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT, + p_param->conf_win_right << 16 | p_param->conf_win_left); + + if (inst->std == W_AVC_ENC) + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, + p_param->avc_slice_arg << 16 | p_param->avc_slice_mode); + else + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, + p_param->independ_slice_mode_arg << 16 | + p_param->independ_slice_mode); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR, + p_param->user_scaling_list_addr); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK, + p_param->num_units_in_tick); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_TIME_SCALE, p_param->time_scale); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE, + p_param->num_ticks_poc_diff_one); + } + + if (inst->std == W_HEVC_ENC) { + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, + (p_param->pu04_delta_rate & 0xFF) | + ((p_param->pu04_intra_planar_delta_rate & 0xFF) << 8) | + ((p_param->pu04_intra_dc_delta_rate & 0xFF) << 16) | + ((p_param->pu04_intra_angle_delta_rate & 0xFF) << 24)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, + (p_param->pu08_delta_rate & 0xFF) | + ((p_param->pu08_intra_planar_delta_rate & 0xFF) << 8) | + ((p_param->pu08_intra_dc_delta_rate & 0xFF) << 16) | + ((p_param->pu08_intra_angle_delta_rate & 0xFF) << 24)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, + (p_param->pu16_delta_rate & 0xFF) | + ((p_param->pu16_intra_planar_delta_rate & 0xFF) << 8) | + ((p_param->pu16_intra_dc_delta_rate & 0xFF) << 16) | + ((p_param->pu16_intra_angle_delta_rate & 0xFF) << 24)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, + (p_param->pu32_delta_rate & 0xFF) | + ((p_param->pu32_intra_planar_delta_rate & 0xFF) << 8) | + ((p_param->pu32_intra_dc_delta_rate & 0xFF) << 16) | + ((p_param->pu32_intra_angle_delta_rate & 0xFF) << 24)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, + (p_param->cu08_intra_delta_rate & 0xFF) | + ((p_param->cu08_inter_delta_rate & 0xFF) << 8) | + ((p_param->cu08_merge_delta_rate & 0xFF) << 16)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, + (p_param->cu16_intra_delta_rate & 0xFF) | + ((p_param->cu16_inter_delta_rate & 0xFF) << 8) | + ((p_param->cu16_merge_delta_rate & 0xFF) << 16)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, + (p_param->cu32_intra_delta_rate & 0xFF) | + ((p_param->cu32_inter_delta_rate & 0xFF) << 8) | + ((p_param->cu32_merge_delta_rate & 0xFF) << 16)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_DEPENDENT_SLICE, + p_param->depend_slice_mode_arg << 16 | p_param->depend_slice_mode); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_PARAM, p_param->nr_y_enable | + (p_param->nr_cb_enable << 1) | (p_param->nr_cr_enable << 2) | + (p_param->nr_noise_est_enable << 3) | + (p_param->nr_noise_sigma_y << 4) | + (p_param->nr_noise_sigma_cb << 12) | + (p_param->nr_noise_sigma_cr << 20)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_WEIGHT, + p_param->nr_intra_weight_y | + (p_param->nr_intra_weight_cb << 5) | + (p_param->nr_intra_weight_cr << 10) | + (p_param->nr_inter_weight_y << 15) | + (p_param->nr_inter_weight_cb << 20) | + (p_param->nr_inter_weight_cr << 25)); + } + if (p_enc_info->open_param.encode_vui_rbsp || p_enc_info->open_param.enc_hrd_rbsp_in_vps) { + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_HRD_PARAM, + (p_enc_info->open_param.hrd_rbsp_data_size << 18) | + (p_enc_info->open_param.vui_rbsp_data_size << 4) | + (p_enc_info->open_param.enc_hrd_rbsp_in_vps << 2) | + (p_enc_info->open_param.encode_vui_rbsp)); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_RBSP_ADDR, + p_enc_info->open_param.vui_rbsp_data_addr); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_HRD_RBSP_ADDR, + p_enc_info->open_param.hrd_rbsp_data_addr); + } else { + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_HRD_PARAM, 0); + } + + wave5_bit_issue_command(inst, W5_ENC_SET_PARAM); + + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_warn(inst->dev->dev, "command: 'W5_ENC_SET_PARAM', timed out\n"); + return ret; + } + + if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { + reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + wave5_print_reg_err(inst->dev, reg_val); + return -EIO; + } + + return 0; +} + +int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info) +{ + int ret; + u32 reg_val; + struct enc_info *p_enc_info = &inst->codec_info->enc_info; + + if (inst->dev->product != PRODUCT_ID_521) + return -EINVAL; + + // send QUERY cmd + ret = wave5_send_query(inst, GET_RESULT); + if (ret) { + if (ret == -EIO) { + reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + wave5_print_reg_err(inst->dev, reg_val); + } + return ret; + } + + dev_dbg(inst->dev->dev, "%s: init seq\n", __func__); + + reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); + + p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; + p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); + + if (vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS) != 1) { + info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO); + ret = -EIO; + } else { + info->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO); + } + + info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_ENC_NUM_REQUIRED_FB); + info->min_src_frame_count = vpu_read_reg(inst->dev, W5_RET_ENC_MIN_SRC_BUF_NUM); + info->max_latency_pictures = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_MAX_LATENCY_PICS); + info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); + info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); + p_enc_info->vlc_buf_size = info->vlc_buf_size; + p_enc_info->param_buf_size = info->param_buf_size; + + return ret; +} + +static u32 calculate_luma_stride(u32 width, u32 bit_depth) +{ + return ALIGN(ALIGN(width, 16) * ((bit_depth > 8) ? 5 : 4), 32); +} + +static u32 calculate_chroma_stride(u32 width, u32 bit_depth) +{ + return ALIGN(ALIGN(width / 2, 16) * ((bit_depth > 8) ? 5 : 4), 32); +} + +int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst, + struct frame_buffer *fb_arr, enum tiled_map_type map_type, + unsigned int count) +{ + struct vpu_device *vpu_dev = dev_get_drvdata(dev); + int ret = 0; + u32 stride; + u32 start_no, end_no; + size_t remain, idx, j, i, cnt_8_chunk; + u32 reg_val = 0, pic_size = 0, mv_col_size, fbc_y_tbl_size, fbc_c_tbl_size; + u32 sub_sampled_size = 0; + u32 endian, luma_stride, chroma_stride, frame_width, frame_height; + u32 buf_height = 0, buf_width = 0; + u32 bit_depth; + bool avc_encoding = (inst->std == W_AVC_ENC); + struct vpu_buf vb_mv = {0}; + struct vpu_buf vb_fbc_y_tbl = {0}; + struct vpu_buf vb_fbc_c_tbl = {0}; + struct vpu_buf vb_sub_sam_buf = {0}; + struct vpu_buf vb_task = {0}; + struct enc_open_param *p_open_param; + struct enc_info *p_enc_info = &inst->codec_info->enc_info; + + p_open_param = &p_enc_info->open_param; + mv_col_size = 0; + fbc_y_tbl_size = 0; + fbc_c_tbl_size = 0; + stride = p_enc_info->stride; + bit_depth = p_open_param->wave_param.internal_bit_depth; + + if (avc_encoding) { + buf_width = ALIGN(p_open_param->pic_width, 16); + buf_height = ALIGN(p_open_param->pic_height, 16); + + if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && + !(p_enc_info->rotation_angle == 180 && + p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { + buf_width = ALIGN(p_open_param->pic_width, 16); + buf_height = ALIGN(p_open_param->pic_height, 16); + } + + if (p_enc_info->rotation_angle == 90 || p_enc_info->rotation_angle == 270) { + buf_width = ALIGN(p_open_param->pic_height, 16); + buf_height = ALIGN(p_open_param->pic_width, 16); + } + } else { + buf_width = ALIGN(p_open_param->pic_width, 8); + buf_height = ALIGN(p_open_param->pic_height, 8); + + if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && + !(p_enc_info->rotation_angle == 180 && + p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { + buf_width = ALIGN(p_open_param->pic_width, 32); + buf_height = ALIGN(p_open_param->pic_height, 32); + } + + if (p_enc_info->rotation_angle == 90 || p_enc_info->rotation_angle == 270) { + buf_width = ALIGN(p_open_param->pic_height, 32); + buf_height = ALIGN(p_open_param->pic_width, 32); + } + } + + pic_size = (buf_width << 16) | buf_height; + + if (avc_encoding) { + mv_col_size = WAVE5_ENC_AVC_BUF_SIZE(buf_width, buf_height); + vb_mv.daddr = 0; + vb_mv.size = ALIGN(mv_col_size * count, BUFFER_MARGIN) + BUFFER_MARGIN; + } else { + mv_col_size = WAVE5_ENC_HEVC_BUF_SIZE(buf_width, buf_height); + mv_col_size = ALIGN(mv_col_size, 16); + vb_mv.daddr = 0; + vb_mv.size = ALIGN(mv_col_size * count, BUFFER_MARGIN) + BUFFER_MARGIN; + } + + ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_mv); + if (ret) + return ret; + + p_enc_info->vb_mv = vb_mv; + + frame_width = ALIGN(buf_width, 16); + frame_height = ALIGN(buf_height, 16); + if (p_enc_info->product_code == WAVE521C_DUAL_CODE) { + // Use 1024 for H264(AVC) and 512 for H265(HEVC) + fbc_y_tbl_size = calculate_table_size(bit_depth, frame_width, frame_height, + (avc_encoding ? 1024 : 512)); + } else { + fbc_y_tbl_size = WAVE5_FBC_LUMA_TABLE_SIZE(buf_width, buf_height); + fbc_y_tbl_size = ALIGN(fbc_y_tbl_size, 16); + } + + vb_fbc_y_tbl.daddr = 0; + vb_fbc_y_tbl.size = ALIGN(fbc_y_tbl_size * count, BUFFER_MARGIN) + BUFFER_MARGIN; + ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_fbc_y_tbl); + if (ret) + goto free_vb_fbc_y_tbl; + + p_enc_info->vb_fbc_y_tbl = vb_fbc_y_tbl; + + if (p_enc_info->product_code == WAVE521C_DUAL_CODE) { + // Use 1024 for H264(AVC) and 512 for HEVC + fbc_c_tbl_size = calculate_table_size(bit_depth, frame_width, frame_height, + (avc_encoding ? 1024 : 512)); + } else { + fbc_c_tbl_size = WAVE5_FBC_CHROMA_TABLE_SIZE(buf_width, buf_height); + fbc_c_tbl_size = ALIGN(fbc_c_tbl_size, 16); + } + + vb_fbc_c_tbl.daddr = 0; + vb_fbc_c_tbl.size = ALIGN(fbc_c_tbl_size * count, BUFFER_MARGIN) + BUFFER_MARGIN; + ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_fbc_c_tbl); + if (ret) + goto free_vb_fbc_c_tbl; + + p_enc_info->vb_fbc_c_tbl = vb_fbc_c_tbl; + + if (avc_encoding) + sub_sampled_size = WAVE5_SUBSAMPLED_ONE_SIZE_AVC(buf_width, buf_height); + else + sub_sampled_size = WAVE5_SUBSAMPLED_ONE_SIZE(buf_width, buf_height); + vb_sub_sam_buf.size = ALIGN(sub_sampled_size * count, BUFFER_MARGIN) + BUFFER_MARGIN; + vb_sub_sam_buf.daddr = 0; + ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_sub_sam_buf); + if (ret) + goto free_vb_sam_buf; + + p_enc_info->vb_sub_sam_buf = vb_sub_sam_buf; + + vb_task.size = (p_enc_info->vlc_buf_size * VLC_BUF_NUM) + + (p_enc_info->param_buf_size * COMMAND_QUEUE_DEPTH); + vb_task.daddr = 0; + if (p_enc_info->vb_task.size == 0) { + ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_task); + if (ret) + goto free_vb_task; + + p_enc_info->vb_task = vb_task; + + vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, + p_enc_info->vb_task.daddr); + vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_task.size); + } + + // set sub-sampled buffer base addr + vpu_write_reg(inst->dev, W5_ADDR_SUB_SAMPLED_FB_BASE, vb_sub_sam_buf.daddr); + // set sub-sampled buffer size for one frame + vpu_write_reg(inst->dev, W5_SUB_SAMPLED_ONE_FB_SIZE, sub_sampled_size); + + endian = wave5_vdi_convert_endian(vpu_dev, fb_arr[0].endian); + + vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size); + + // set stride of luma/chroma for compressed buffer + if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && + !(p_enc_info->rotation_angle == 180 && + p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { + luma_stride = calculate_luma_stride(buf_width, bit_depth); + chroma_stride = calculate_chroma_stride(buf_width / 2, bit_depth); + } else { + luma_stride = calculate_luma_stride(p_open_param->pic_width, bit_depth); + chroma_stride = calculate_chroma_stride(p_open_param->pic_width / 2, bit_depth); + } + + vpu_write_reg(inst->dev, W5_FBC_STRIDE, luma_stride << 16 | chroma_stride); + vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, stride); + + remain = count; + cnt_8_chunk = ALIGN(count, 8) / 8; + idx = 0; + for (j = 0; j < cnt_8_chunk; j++) { + reg_val = (endian << 16) | (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); + reg_val |= (p_open_param->enable_non_ref_fbc_write << 26); + vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val); + start_no = j * 8; + end_no = start_no + ((remain >= 8) ? 8 : remain) - 1; + + vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no); + + for (i = 0; i < 8 && i < remain; i++) { + vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), fb_arr[i + + start_no].buf_y); + vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), + fb_arr[i + start_no].buf_cb); + /* luma FBC offset table */ + vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4), + vb_fbc_y_tbl.daddr + idx * fbc_y_tbl_size); + /* chroma FBC offset table */ + vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), + vb_fbc_c_tbl.daddr + idx * fbc_c_tbl_size); + + vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), + vb_mv.daddr + idx * mv_col_size); + idx++; + } + remain -= i; + + wave5_bit_issue_command(inst, W5_SET_FB); + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + if (ret) + goto free_vb_mem; + } + + reg_val = vpu_read_reg(inst->dev, W5_RET_SUCCESS); + if (!reg_val) { + ret = -EIO; + goto free_vb_mem; + } + + return ret; + +free_vb_mem: + wave5_vdi_free_dma_memory(vpu_dev, &vb_task); +free_vb_task: + wave5_vdi_free_dma_memory(vpu_dev, &vb_sub_sam_buf); +free_vb_sam_buf: + wave5_vdi_free_dma_memory(vpu_dev, &vb_fbc_c_tbl); +free_vb_fbc_c_tbl: + wave5_vdi_free_dma_memory(vpu_dev, &vb_fbc_y_tbl); +free_vb_fbc_y_tbl: + wave5_vdi_free_dma_memory(vpu_dev, &vb_mv); + return ret; +} + +int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res) +{ + u32 src_frame_format; + u32 reg_val = 0, bs_endian; + u32 src_stride_c = 0; + struct enc_info *p_enc_info = &inst->codec_info->enc_info; + struct frame_buffer *p_src_frame = option->source_frame; + struct enc_open_param *p_open_param = &p_enc_info->open_param; + bool justified = WTL_RIGHT_JUSTIFIED; + u32 format_no = WTL_PIXEL_8BIT; + int ret; + + if (inst->dev->product != PRODUCT_ID_521) + return -EINVAL; + + vpu_write_reg(inst->dev, W5_CMD_ENC_BS_START_ADDR, option->pic_stream_buffer_addr); + vpu_write_reg(inst->dev, W5_CMD_ENC_BS_SIZE, option->pic_stream_buffer_size); + p_enc_info->stream_buf_start_addr = option->pic_stream_buffer_addr; + p_enc_info->stream_buf_size = option->pic_stream_buffer_size; + p_enc_info->stream_buf_end_addr = + option->pic_stream_buffer_addr + option->pic_stream_buffer_size; + + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_AXI_SEL, DEFAULT_SRC_AXI); + /* secondary AXI */ + reg_val = (p_enc_info->sec_axi_info.wave.use_enc_rdo_enable << 11) | + (p_enc_info->sec_axi_info.wave.use_enc_lf_enable << 15); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_USE_SEC_AXI, reg_val); + + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_REPORT_PARAM, 0); + + /* + * CODEOPT_ENC_VCL is used to implicitly encode header/headers to generate bitstream. + * (use ENC_PUT_VIDEO_HEADER for give_command to encode only a header) + */ + if (option->code_option.implicit_header_encode) + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION, + CODEOPT_ENC_HEADER_IMPLICIT | CODEOPT_ENC_VCL | + (option->code_option.encode_aud << 5) | + (option->code_option.encode_eos << 6) | + (option->code_option.encode_eob << 7)); + else + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION, + option->code_option.implicit_header_encode | + (option->code_option.encode_vcl << 1) | + (option->code_option.encode_vps << 2) | + (option->code_option.encode_sps << 3) | + (option->code_option.encode_pps << 4) | + (option->code_option.encode_aud << 5) | + (option->code_option.encode_eos << 6) | + (option->code_option.encode_eob << 7)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PIC_PARAM, option->skip_picture | + (option->force_pic_qp_enable << 1) | (option->force_pic_qp_i << 2) | + (option->force_pic_qp_p << 8) | (option->force_pic_qp_b << 14) | + (option->force_pic_type_enable << 20) | (option->force_pic_type << 21) | + (option->force_all_ctu_coef_drop_enable << 24)); + + if (option->src_end_flag) + // no more source images. + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0xFFFFFFFF); + else + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, option->src_idx); + + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_Y, p_src_frame->buf_y); + if (p_open_param->cbcr_order == CBCR_ORDER_NORMAL) { + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_U, p_src_frame->buf_cb); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_V, p_src_frame->buf_cr); + } else { + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_U, p_src_frame->buf_cr); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_V, p_src_frame->buf_cb); + } + + switch (p_open_param->src_format) { + case FORMAT_420: + case FORMAT_422: + case FORMAT_YUYV: + case FORMAT_YVYU: + case FORMAT_UYVY: + case FORMAT_VYUY: + justified = WTL_LEFT_JUSTIFIED; + format_no = WTL_PIXEL_8BIT; + src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : + (p_src_frame->stride / 2); + src_stride_c = (p_open_param->src_format == FORMAT_422) ? src_stride_c * 2 : + src_stride_c; + break; + case FORMAT_420_P10_16BIT_MSB: + case FORMAT_422_P10_16BIT_MSB: + case FORMAT_YUYV_P10_16BIT_MSB: + case FORMAT_YVYU_P10_16BIT_MSB: + case FORMAT_UYVY_P10_16BIT_MSB: + case FORMAT_VYUY_P10_16BIT_MSB: + justified = WTL_RIGHT_JUSTIFIED; + format_no = WTL_PIXEL_16BIT; + src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : + (p_src_frame->stride / 2); + src_stride_c = (p_open_param->src_format == + FORMAT_422_P10_16BIT_MSB) ? src_stride_c * 2 : src_stride_c; + break; + case FORMAT_420_P10_16BIT_LSB: + case FORMAT_422_P10_16BIT_LSB: + case FORMAT_YUYV_P10_16BIT_LSB: + case FORMAT_YVYU_P10_16BIT_LSB: + case FORMAT_UYVY_P10_16BIT_LSB: + case FORMAT_VYUY_P10_16BIT_LSB: + justified = WTL_LEFT_JUSTIFIED; + format_no = WTL_PIXEL_16BIT; + src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : + (p_src_frame->stride / 2); + src_stride_c = (p_open_param->src_format == + FORMAT_422_P10_16BIT_LSB) ? src_stride_c * 2 : src_stride_c; + break; + case FORMAT_420_P10_32BIT_MSB: + case FORMAT_422_P10_32BIT_MSB: + case FORMAT_YUYV_P10_32BIT_MSB: + case FORMAT_YVYU_P10_32BIT_MSB: + case FORMAT_UYVY_P10_32BIT_MSB: + case FORMAT_VYUY_P10_32BIT_MSB: + justified = WTL_RIGHT_JUSTIFIED; + format_no = WTL_PIXEL_32BIT; + src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : + ALIGN(p_src_frame->stride / 2, 16) * BIT(inst->cbcr_interleave); + src_stride_c = (p_open_param->src_format == + FORMAT_422_P10_32BIT_MSB) ? src_stride_c * 2 : src_stride_c; + break; + case FORMAT_420_P10_32BIT_LSB: + case FORMAT_422_P10_32BIT_LSB: + case FORMAT_YUYV_P10_32BIT_LSB: + case FORMAT_YVYU_P10_32BIT_LSB: + case FORMAT_UYVY_P10_32BIT_LSB: + case FORMAT_VYUY_P10_32BIT_LSB: + justified = WTL_LEFT_JUSTIFIED; + format_no = WTL_PIXEL_32BIT; + src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : + ALIGN(p_src_frame->stride / 2, 16) * BIT(inst->cbcr_interleave); + src_stride_c = (p_open_param->src_format == + FORMAT_422_P10_32BIT_LSB) ? src_stride_c * 2 : src_stride_c; + break; + default: + return -EINVAL; + } + + src_frame_format = (inst->cbcr_interleave << 1) | (inst->nv21); + switch (p_open_param->packed_format) { + case PACKED_YUYV: + src_frame_format = 4; + break; + case PACKED_YVYU: + src_frame_format = 5; + break; + case PACKED_UYVY: + src_frame_format = 6; + break; + case PACKED_VYUY: + src_frame_format = 7; + break; + default: + break; + } + + reg_val = wave5_vdi_convert_endian(inst->dev, p_open_param->source_endian); + bs_endian = (~reg_val & VDI_128BIT_ENDIAN_MASK); + + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_STRIDE, + (p_src_frame->stride << 16) | src_stride_c); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_FORMAT, src_frame_format | + (format_no << 3) | (justified << 5) | (bs_endian << 6)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR, + option->custom_map_opt.addr_custom_map); + + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM, + option->custom_map_opt.custom_roi_map_enable | + (option->custom_map_opt.roi_avg_qp << 1) | + (option->custom_map_opt.custom_lambda_map_enable << 8) | + (option->custom_map_opt.custom_mode_map_enable << 9) | + (option->custom_map_opt.custom_coef_drop_enable << 10)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_LONGTERM_PIC, + option->use_cur_src_as_longterm_pic | (option->use_longterm_ref << 1)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y, option->wp_pix_sigma_y); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C, + (option->wp_pix_sigma_cr << 16) | option->wp_pix_sigma_cb); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y, option->wp_pix_mean_y); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C, + (option->wp_pix_mean_cr << 16) | (option->wp_pix_mean_cb)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_INFO, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_INFO, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR, 0); + + wave5_bit_issue_command(inst, W5_ENC_PIC); + + // check QUEUE_DONE + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_warn(inst->dev->dev, "command: 'W5_ENC_PIC', timed out\n"); + return -ETIMEDOUT; + } + + reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); + + p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; + p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); + + // Check if we were able to add a command into the VCPU QUEUE + if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { + *fail_res = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + wave5_print_reg_err(inst->dev, *fail_res); + return -EIO; + } + + return 0; +} + +int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result) +{ + int ret; + u32 encoding_success; + u32 reg_val; + struct enc_info *p_enc_info = &inst->codec_info->enc_info; + struct vpu_device *vpu_dev = inst->dev; + + if (vpu_dev->product != PRODUCT_ID_521) + return -EINVAL; + + ret = wave5_send_query(inst, GET_RESULT); + if (ret) { + if (ret == -EIO) { + reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + wave5_print_reg_err(inst->dev, reg_val); + } + return ret; + } + dev_dbg(inst->dev->dev, "%s: enc pic complete\n", __func__); + + reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); + + p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; + p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); + + encoding_success = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS); + if (!encoding_success) { + result->error_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO); + return -EIO; + } + + result->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO); + + reg_val = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_TYPE); + result->pic_type = reg_val & 0xFFFF; + + result->enc_vcl_nut = vpu_read_reg(inst->dev, W5_RET_ENC_VCL_NUT); + /* + * To get the reconstructed frame use the following index on + * inst->frame_buf + */ + result->recon_frame_index = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_IDX); + result->enc_pic_byte = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_BYTE); + result->enc_src_idx = vpu_read_reg(inst->dev, W5_RET_ENC_USED_SRC_IDX); + p_enc_info->stream_wr_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_WR_PTR); + p_enc_info->stream_rd_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR); + + result->bitstream_buffer = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR); + result->rd_ptr = p_enc_info->stream_rd_ptr; + result->wr_ptr = p_enc_info->stream_wr_ptr; + + //result for header only(no vcl) encoding + if (result->recon_frame_index == RECON_IDX_FLAG_HEADER_ONLY) + result->bitstream_size = result->enc_pic_byte; + else if (result->recon_frame_index < 0) + result->bitstream_size = 0; + else + result->bitstream_size = result->enc_pic_byte; + + result->enc_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_ENC_HOST_CMD_TICK); + result->enc_encode_end_tick = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_END_TICK); + + if (!p_enc_info->first_cycle_check) { + result->frame_cycle = (result->enc_encode_end_tick - result->enc_host_cmd_tick) * + p_enc_info->cycle_per_tick; + p_enc_info->first_cycle_check = true; + } else { + result->frame_cycle = + (result->enc_encode_end_tick - vpu_dev->last_performance_cycles) * + p_enc_info->cycle_per_tick; + if (vpu_dev->last_performance_cycles < result->enc_host_cmd_tick) + result->frame_cycle = (result->enc_encode_end_tick - + result->enc_host_cmd_tick) * p_enc_info->cycle_per_tick; + } + vpu_dev->last_performance_cycles = result->enc_encode_end_tick; + + return 0; +} + +int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res) +{ + int ret; + + if (inst->dev->product != PRODUCT_ID_521) + return -EINVAL; + + wave5_bit_issue_command(inst, W5_DESTROY_INSTANCE); + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + if (ret) + return -ETIMEDOUT; + + if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { + *fail_res = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); + wave5_print_reg_err(inst->dev, *fail_res); + return -EIO; + } + return 0; +} + +static int wave5_vpu_enc_check_common_param_valid(struct vpu_instance *inst, + struct enc_open_param *open_param) +{ + int i = 0; + bool low_delay = true; + struct enc_wave_param *param = &open_param->wave_param; + struct vpu_device *vpu_dev = inst->dev; + struct device *dev = vpu_dev->dev; + u32 num_ctu_row = (open_param->pic_height + 64 - 1) / 64; + u32 num_ctu_col = (open_param->pic_width + 64 - 1) / 64; + u32 ctu_sz = num_ctu_col * num_ctu_row; + + // check low-delay gop structure + if (param->gop_preset_idx == PRESET_IDX_CUSTOM_GOP) { /* common gop */ + if (param->gop_param.custom_gop_size > 1) { + s32 min_val = param->gop_param.pic_param[0].poc_offset; + + for (i = 1; i < param->gop_param.custom_gop_size; i++) { + if (min_val > param->gop_param.pic_param[i].poc_offset) { + low_delay = false; + break; + } + min_val = param->gop_param.pic_param[i].poc_offset; + } + } + } + + if (inst->std == W_HEVC_ENC && low_delay && + param->decoding_refresh_type == DEC_REFRESH_TYPE_CRA) { + dev_warn(dev, + "dec_refresh_type(CRA) shouldn't be used together with low delay GOP\n"); + dev_warn(dev, "Suggested configuration parameter: decoding refresh type (IDR)\n"); + param->decoding_refresh_type = 2; + } + + if (param->gop_preset_idx == PRESET_IDX_CUSTOM_GOP) { + for (i = 0; i < param->gop_param.custom_gop_size; i++) { + if (param->gop_param.pic_param[i].temporal_id >= MAX_NUM_TEMPORAL_LAYER) { + dev_err(dev, "temporal_id: %d exceeds MAX_NUM_TEMPORAL_LAYER (%u)\n", + param->gop_param.pic_param[i].temporal_id, + MAX_NUM_TEMPORAL_LAYER); + return -EINVAL; + } + + if (param->gop_param.pic_param[i].temporal_id < 0) { + dev_err(dev, "temporal_id: %d must be greater or equal to 0\n", + param->gop_param.pic_param[i].temporal_id); + return -EINVAL; + } + } + } + + if (param->wpp_enable && param->independ_slice_mode) { + unsigned int num_ctb_in_width = ALIGN(open_param->pic_width, 64) >> 6; + + if (param->independ_slice_mode_arg % num_ctb_in_width) { + dev_err(dev, "independ_slice_mode_arg %u must be a multiple of %u\n", + param->independ_slice_mode_arg, num_ctb_in_width); + return -EINVAL; + } + } + + // multi-slice & wpp + if (param->wpp_enable && param->depend_slice_mode) { + dev_err(dev, "wpp_enable && depend_slice_mode cannot be used simultaneously\n"); + return -EINVAL; + } + + if (!param->independ_slice_mode && param->depend_slice_mode) { + dev_err(dev, "depend_slice_mode requires independ_slice_mode\n"); + return -EINVAL; + } else if (param->independ_slice_mode && + param->depend_slice_mode == DEPEND_SLICE_MODE_RECOMMENDED && + param->independ_slice_mode_arg < param->depend_slice_mode_arg) { + dev_err(dev, "independ_slice_mode_arg: %u must be smaller than %u\n", + param->independ_slice_mode_arg, param->depend_slice_mode_arg); + return -EINVAL; + } + + if (param->independ_slice_mode && param->independ_slice_mode_arg > 65535) { + dev_err(dev, "independ_slice_mode_arg: %u must be smaller than 65535\n", + param->independ_slice_mode_arg); + return -EINVAL; + } + + if (param->depend_slice_mode && param->depend_slice_mode_arg > 65535) { + dev_err(dev, "depend_slice_mode_arg: %u must be smaller than 65535\n", + param->depend_slice_mode_arg); + return -EINVAL; + } + + if (param->conf_win_top % 2) { + dev_err(dev, "conf_win_top: %u, must be a multiple of 2\n", param->conf_win_top); + return -EINVAL; + } + + if (param->conf_win_bot % 2) { + dev_err(dev, "conf_win_bot: %u, must be a multiple of 2\n", param->conf_win_bot); + return -EINVAL; + } + + if (param->conf_win_left % 2) { + dev_err(dev, "conf_win_left: %u, must be a multiple of 2\n", param->conf_win_left); + return -EINVAL; + } + + if (param->conf_win_right % 2) { + dev_err(dev, "conf_win_right: %u, Must be a multiple of 2\n", + param->conf_win_right); + return -EINVAL; + } + + if (param->lossless_enable && (param->nr_y_enable || param->nr_cb_enable || + param->nr_cr_enable)) { + /* Noise reduction => en_nr_y, en_nr_cb, en_nr_cr */ + dev_err(dev, "option noise_reduction cannot be used with lossless_coding\n"); + return -EINVAL; + } + + if (param->lossless_enable && param->bg_detect_enable) { + dev_err(dev, "option bg_detect cannot be used with lossless_coding\n"); + return -EINVAL; + } + + if (param->lossless_enable && open_param->rc_enable) { + dev_err(dev, "option rate_control cannot be used with lossless_coding\n"); + return -EINVAL; + } + + if (param->lossless_enable && param->roi_enable) { + dev_err(dev, "option roi cannot be used with lossless_coding\n"); + return -EINVAL; + } + + if (param->lossless_enable && !param->skip_intra_trans) { + dev_err(dev, "option intra_trans_skip must be enabled with lossless_coding\n"); + return -EINVAL; + } + + // intra refresh + if (param->intra_refresh_mode && param->intra_refresh_arg == 0) { + dev_err(dev, "Invalid refresh argument, mode: %u, refresh: %u must be > 0\n", + param->intra_refresh_mode, param->intra_refresh_arg); + return -EINVAL; + } + switch (param->intra_refresh_mode) { + case REFRESH_MODE_CTU_ROWS: + if (param->intra_mb_refresh_arg > num_ctu_row) + goto invalid_refresh_argument; + break; + case REFRESH_MODE_CTU_COLUMNS: + if (param->intra_refresh_arg > num_ctu_col) + goto invalid_refresh_argument; + break; + case REFRESH_MODE_CTU_STEP_SIZE: + if (param->intra_refresh_arg > ctu_sz) + goto invalid_refresh_argument; + break; + case REFRESH_MODE_CTUS: + if (param->intra_refresh_arg > ctu_sz) + goto invalid_refresh_argument; + if (param->lossless_enable) { + dev_err(dev, "mode: %u cannot be used lossless_enable", + param->intra_refresh_mode); + return -EINVAL; + } + if (param->roi_enable) { + dev_err(dev, "mode: %u cannot be used and roi_enable", + param->intra_refresh_mode); + return -EINVAL; + } + }; + return 0; + +invalid_refresh_argument: + dev_err(dev, "Invalid refresh argument, mode: %u, refresh: %u > W(%u)xH(%u)\n", + param->intra_refresh_mode, param->intra_refresh_arg, + num_ctu_row, num_ctu_col); + return -EINVAL; +} + +static int wave5_vpu_enc_check_param_valid(struct vpu_device *vpu_dev, + struct enc_open_param *open_param) +{ + struct enc_wave_param *param = &open_param->wave_param; + + if (open_param->rc_enable) { + if (param->min_qp_i > param->max_qp_i || param->min_qp_p > param->max_qp_p || + param->min_qp_b > param->max_qp_b) { + dev_err(vpu_dev->dev, "Configuration failed because min_qp is greater than max_qp\n"); + dev_err(vpu_dev->dev, "Suggested configuration parameters: min_qp = max_qp\n"); + return -EINVAL; + } + + if (open_param->bit_rate <= (int)open_param->frame_rate_info) { + dev_err(vpu_dev->dev, + "enc_bit_rate: %u must be greater than the frame_rate: %u\n", + open_param->bit_rate, (int)open_param->frame_rate_info); + return -EINVAL; + } + } + + return 0; +} + +static int wave5_vpu_enc_check_custom_gop(struct vpu_device *vpu_dev, + struct enc_open_param *open_param) +{ + struct custom_gop_param *gop_param; + struct custom_gop_pic_param *gop_pic_param; + struct custom_gop_pic_param new_gop[MAX_GOP_NUM * 2 + 1]; + + unsigned int i, ei, gi; + u32 gop_size; + s32 curr_poc, ref_poc; + s32 enc_tid[MAX_GOP_NUM * 2 + 1]; + + gop_param = &open_param->wave_param.gop_param; + gop_size = gop_param->custom_gop_size; + + new_gop[0].poc_offset = 0; + new_gop[0].temporal_id = 0; + new_gop[0].pic_type = PIC_TYPE_I; + new_gop[0].use_multi_ref_p = 0; + enc_tid[0] = 0; + + for (i = 0; i < gop_size * 2; i++) { + ei = i % gop_size; + gi = i / gop_size; + gop_pic_param = &gop_param->pic_param[ei]; + + curr_poc = gi * gop_size + gop_pic_param->poc_offset; + new_gop[i + 1].poc_offset = curr_poc; + new_gop[i + 1].temporal_id = gop_pic_param->temporal_id; + new_gop[i + 1].pic_type = gop_pic_param->pic_type; + new_gop[i + 1].ref_poc_l0 = gop_pic_param->ref_poc_l0 + gi * gop_size; + new_gop[i + 1].ref_poc_l1 = gop_pic_param->ref_poc_l1 + gi * gop_size; + new_gop[i + 1].use_multi_ref_p = gop_pic_param->use_multi_ref_p; + enc_tid[i + 1] = -1; + } + + for (i = 0; i < gop_size; i++) { + gop_pic_param = &gop_param->pic_param[i]; + + if (gop_pic_param->poc_offset <= 0) { + dev_err(vpu_dev->dev, "POC of the %u-th pic not greater then -1\n", i + 1); + return -EINVAL; + } + if (gop_pic_param->poc_offset > gop_size) { + dev_err(vpu_dev->dev, "POC of %uth pic bigger than gop_size\n", i + 1); + return -EINVAL; + } + if (gop_pic_param->temporal_id < 0) { + dev_err(vpu_dev->dev, "temporal_id of the %d-th < 0\n", i + 1); + return -EINVAL; + } + } + + for (ei = 1; ei < gop_size * 2 + 1; ei++) { + struct custom_gop_pic_param *cur_pic = &new_gop[ei]; + + if (ei <= gop_size) { + enc_tid[cur_pic->poc_offset] = cur_pic->temporal_id; + continue; + } + + if (new_gop[ei].pic_type != PIC_TYPE_I) { + ref_poc = cur_pic->ref_poc_l0; + + /* reference picture is not encoded yet */ + if (enc_tid[ref_poc] < 0) { + dev_err(vpu_dev->dev, "1st ref pic can't be ref of pic (POC: %u)\n", + cur_pic->poc_offset - gop_size); + return -EINVAL; + } + if (enc_tid[ref_poc] > cur_pic->temporal_id) { + dev_err(vpu_dev->dev, "wrong temporal_id of pic (POC: %u)\n", + cur_pic->poc_offset - gop_size); + return -EINVAL; + } + if (ref_poc >= cur_pic->poc_offset) { + dev_err(vpu_dev->dev, "POC of 1st ref pic of %u-th pic is wrong\n", + cur_pic->poc_offset - gop_size); + return -EINVAL; + } + } + if (new_gop[ei].pic_type != PIC_TYPE_P) { + ref_poc = cur_pic->ref_poc_l1; + + /* reference picture is not encoded yet */ + if (enc_tid[ref_poc] < 0) { + dev_err(vpu_dev->dev, "2nd ref pic can't be ref of pic (POC: %u)\n" + , cur_pic->poc_offset - gop_size); + return -EINVAL; + } + if (enc_tid[ref_poc] > cur_pic->temporal_id) { + dev_err(vpu_dev->dev, "temporal_id of %u-th picture is wrong\n", + cur_pic->poc_offset - gop_size); + return -EINVAL; + } + if (new_gop[ei].pic_type == PIC_TYPE_P && new_gop[ei].use_multi_ref_p > 0) { + if (ref_poc >= cur_pic->poc_offset) { + dev_err(vpu_dev->dev, "bad POC of 2nd ref pic of %uth pic\n", + cur_pic->poc_offset - gop_size); + return -EINVAL; + } + } else if (ref_poc == cur_pic->poc_offset) { + /* HOST_PIC_TYPE_B */ + dev_err(vpu_dev->dev, "POC of 2nd ref pic of %uth pic is wrong\n", + cur_pic->poc_offset - gop_size); + return -EINVAL; + } + } + curr_poc = cur_pic->poc_offset; + enc_tid[curr_poc] = cur_pic->temporal_id; + } + return 0; +} + +int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param) +{ + u32 pic_width; + u32 pic_height; + s32 product_id = inst->dev->product; + struct vpu_attr *p_attr = &inst->dev->attr; + struct enc_wave_param *param; + + if (!open_param) + return -EINVAL; + + param = &open_param->wave_param; + pic_width = open_param->pic_width; + pic_height = open_param->pic_height; + + if (inst->id >= MAX_NUM_INSTANCE) { + dev_err(inst->dev->dev, "Too many simultaneous instances: %d (max: %u)\n", + inst->id, MAX_NUM_INSTANCE); + return -EOPNOTSUPP; + } + + if (inst->std != W_HEVC_ENC && + !(inst->std == W_AVC_ENC && product_id == PRODUCT_ID_521)) { + dev_err(inst->dev->dev, "Unsupported encoder-codec & product combination\n"); + return -EOPNOTSUPP; + } + + if (param->internal_bit_depth == 10) { + if (inst->std == W_HEVC_ENC && !p_attr->support_hevc10bit_enc) { + dev_err(inst->dev->dev, + "Flag support_hevc10bit_enc must be set to encode 10bit HEVC\n"); + return -EOPNOTSUPP; + } else if (inst->std == W_AVC_ENC && !p_attr->support_avc10bit_enc) { + dev_err(inst->dev->dev, + "Flag support_avc10bit_enc must be set to encode 10bit AVC\n"); + return -EOPNOTSUPP; + } + } + + if (open_param->ring_buffer_enable) { + if (open_param->bitstream_buffer % 8) { + dev_err(inst->dev->dev, + "Bitstream buffer must be aligned to a multiple of 8\n"); + return -EINVAL; + } + if (open_param->bitstream_buffer_size % 1024 || + open_param->bitstream_buffer_size < MIN_BITSTREAM_BUFFER_SIZE) { + dev_err(inst->dev->dev, + "Bitstream buffer size must be aligned to a multiple of 1024 and have a minimum size of %u\n", + MIN_BITSTREAM_BUFFER_SIZE); + return -EINVAL; + } + if (product_id == PRODUCT_ID_521) { + if (open_param->bitstream_buffer % 16) { + dev_err(inst->dev->dev, + "Bitstream buffer must be aligned to a multiple of 16\n"); + return -EINVAL; + } + if (open_param->bitstream_buffer_size < MIN_BITSTREAM_BUFFER_SIZE_WAVE521) { + dev_err(inst->dev->dev, + "Bitstream buffer too small: %u (minimum: %u)\n", + open_param->bitstream_buffer_size, + MIN_BITSTREAM_BUFFER_SIZE_WAVE521); + return -EINVAL; + } + } + } + + if (!open_param->frame_rate_info) + return -EINVAL; + if (open_param->bit_rate > MAX_BIT_RATE) { + dev_err(inst->dev->dev, "Invalid encoding bit-rate: %u (valid: 0-%u)\n", + open_param->bit_rate, MAX_BIT_RATE); + return -EINVAL; + } + + if (pic_width < W5_MIN_ENC_PIC_WIDTH || pic_width > W5_MAX_ENC_PIC_WIDTH || + pic_height < W5_MIN_ENC_PIC_HEIGHT || pic_height > W5_MAX_ENC_PIC_HEIGHT) { + dev_err(inst->dev->dev, "Invalid encoding dimension: %ux%u\n", + pic_width, pic_height); + return -EINVAL; + } + + if (param->profile) { + if (inst->std == W_HEVC_ENC) { + if ((param->profile != HEVC_PROFILE_MAIN || + (param->profile == HEVC_PROFILE_MAIN && + param->internal_bit_depth > 8)) && + (param->profile != HEVC_PROFILE_MAIN10 || + (param->profile == HEVC_PROFILE_MAIN10 && + param->internal_bit_depth < 10)) && + param->profile != HEVC_PROFILE_STILLPICTURE) { + dev_err(inst->dev->dev, + "Invalid HEVC encoding profile: %u (bit-depth: %u)\n", + param->profile, param->internal_bit_depth); + return -EINVAL; + } + } else if (inst->std == W_AVC_ENC) { + if ((param->internal_bit_depth > 8 && + param->profile != H264_PROFILE_HIGH10)) { + dev_err(inst->dev->dev, + "Invalid AVC encoding profile: %u (bit-depth: %u)\n", + param->profile, param->internal_bit_depth); + return -EINVAL; + } + } + } + + if (param->decoding_refresh_type > DEC_REFRESH_TYPE_IDR) { + dev_err(inst->dev->dev, "Invalid decoding refresh type: %u (valid: 0-2)\n", + param->decoding_refresh_type); + return -EINVAL; + } + + if (param->gop_preset_idx == PRESET_IDX_CUSTOM_GOP) { + if (param->gop_param.custom_gop_size < 1 || + param->gop_param.custom_gop_size > MAX_GOP_NUM) { + dev_err(inst->dev->dev, + "Invalid custom group of pictures size: %u (valid: 1-%u)\n", + param->gop_param.custom_gop_size, MAX_GOP_NUM); + return -EINVAL; + } + } + + if (inst->std == W_AVC_ENC && param->custom_lambda_enable) { + dev_err(inst->dev->dev, + "Cannot combine AVC encoding with the custom lambda option\n"); + return -EINVAL; + } + if (param->intra_refresh_mode > REFRESH_MODE_CTUS) { + dev_err(inst->dev->dev, "Invalid intra refresh mode: %d (valid: 0-4)\n", + param->intra_refresh_mode); + return -EINVAL; + } + + if (inst->std == W_HEVC_ENC && param->independ_slice_mode && + param->depend_slice_mode > DEPEND_SLICE_MODE_BOOST) { + dev_err(inst->dev->dev, + "Can't combine slice modes: independent and fast dependent for HEVC\n"); + return -EINVAL; + } + + if (param->scaling_list_enable > 2) { + dev_err(inst->dev->dev, "Invalid scaling_list_enable: %u (valid: 0-2)\n", + param->scaling_list_enable); + return -EINVAL; + } + + if (!param->disable_deblk) { + if (param->beta_offset_div2 < -6 || param->beta_offset_div2 > 6) { + dev_err(inst->dev->dev, "Invalid beta offset: %d (valid: -6-6)\n", + param->beta_offset_div2); + return -EINVAL; + } + + if (param->tc_offset_div2 < -6 || param->tc_offset_div2 > 6) { + dev_err(inst->dev->dev, "Invalid tc offset: %d (valid: -6-6)\n", + param->tc_offset_div2); + return -EINVAL; + } + } + + if (param->intra_qp > MAX_INTRA_QP) { + dev_err(inst->dev->dev, + "Invalid intra quantization parameter: %u (valid: 0-%u)\n", + param->intra_qp, MAX_INTRA_QP); + return -EINVAL; + } + + if (open_param->rc_enable) { + if (param->min_qp_i > MAX_INTRA_QP || param->max_qp_i > MAX_INTRA_QP || + param->min_qp_p > MAX_INTRA_QP || param->max_qp_p > MAX_INTRA_QP || + param->min_qp_b > MAX_INTRA_QP || param->max_qp_b > MAX_INTRA_QP) { + dev_err(inst->dev->dev, + "Invalid quantization parameter min/max values: " + "I: %u-%u, P: %u-%u, B: %u-%u (valid for each: 0-%u)\n", + param->min_qp_i, param->max_qp_i, param->min_qp_p, param->max_qp_p, + param->min_qp_b, param->max_qp_b, MAX_INTRA_QP); + return -EINVAL; + } + + if (param->hvs_qp_enable && param->hvs_max_delta_qp > MAX_HVS_MAX_DELTA_QP) { + dev_err(inst->dev->dev, + "Invalid HVS max delta quantization parameter: %u (valid: 0-%u)\n", + param->hvs_max_delta_qp, MAX_HVS_MAX_DELTA_QP); + return -EINVAL; + } + + if (param->bit_alloc_mode > BIT_ALLOC_MODE_FIXED_RATIO) { + dev_err(inst->dev->dev, "Invalid bit alloc mode: %u (valid: 0-2)\n", + param->bit_alloc_mode); + return -EINVAL; + } + + if (open_param->vbv_buffer_size < MIN_VBV_BUFFER_SIZE || + open_param->vbv_buffer_size > MAX_VBV_BUFFER_SIZE) { + dev_err(inst->dev->dev, "VBV buffer size: %u (valid: %u-%u)\n", + open_param->vbv_buffer_size, MIN_VBV_BUFFER_SIZE, + MAX_VBV_BUFFER_SIZE); + return -EINVAL; + } + } + + if (wave5_vpu_enc_check_common_param_valid(inst, open_param)) + return -EINVAL; + + if (wave5_vpu_enc_check_param_valid(inst->dev, open_param)) + return -EINVAL; + + if (param->gop_preset_idx == PRESET_IDX_CUSTOM_GOP) { + if (wave5_vpu_enc_check_custom_gop(inst->dev, open_param)) + return -EINVAL; + } + + if (param->chroma_cb_qp_offset < -12 || param->chroma_cb_qp_offset > 12) { + dev_err(inst->dev->dev, + "Invalid chroma Cb quantization parameter offset: %d (valid: -12-12)\n", + param->chroma_cb_qp_offset); + return -EINVAL; + } + + if (param->chroma_cr_qp_offset < -12 || param->chroma_cr_qp_offset > 12) { + dev_err(inst->dev->dev, + "Invalid chroma Cr quantization parameter offset: %d (valid: -12-12)\n", + param->chroma_cr_qp_offset); + return -EINVAL; + } + + if (param->intra_refresh_mode == REFRESH_MODE_CTU_STEP_SIZE && !param->intra_refresh_arg) { + dev_err(inst->dev->dev, + "Intra refresh mode CTU step-size requires an argument\n"); + return -EINVAL; + } + + if (inst->std == W_HEVC_ENC) { + if (param->nr_noise_sigma_y > MAX_NOISE_SIGMA || + param->nr_noise_sigma_cb > MAX_NOISE_SIGMA || + param->nr_noise_sigma_cr > MAX_NOISE_SIGMA) { + dev_err(inst->dev->dev, + "Invalid noise sigma Y(%u) Cb(%u) Cr(%u) (valid: %u)\n", + param->nr_noise_sigma_y, param->nr_noise_sigma_cb, + param->nr_noise_sigma_cr, MAX_NOISE_SIGMA); + return -EINVAL; + } + + if (param->nr_intra_weight_y > MAX_INTRA_WEIGHT || + param->nr_intra_weight_cb > MAX_INTRA_WEIGHT || + param->nr_intra_weight_cr > MAX_INTRA_WEIGHT) { + dev_err(inst->dev->dev, + "Invalid intra weight Y(%u) Cb(%u) Cr(%u) (valid: %u)\n", + param->nr_intra_weight_y, param->nr_intra_weight_cb, + param->nr_intra_weight_cr, MAX_INTRA_WEIGHT); + return -EINVAL; + } + + if (param->nr_inter_weight_y > MAX_INTER_WEIGHT || + param->nr_inter_weight_cb > MAX_INTER_WEIGHT || + param->nr_inter_weight_cr > MAX_INTER_WEIGHT) { + dev_err(inst->dev->dev, + "Invalid inter weight Y(%u) Cb(%u) Cr(%u) (valid: %u)\n", + param->nr_inter_weight_y, param->nr_inter_weight_cb, + param->nr_inter_weight_cr, MAX_INTER_WEIGHT); + return -EINVAL; + } + + if ((param->nr_y_enable || param->nr_cb_enable || param->nr_cr_enable) && + param->lossless_enable) { + dev_err(inst->dev->dev, + "Can't enable lossless mode with either nr_y, nr_cb or nr_cr\n"); + return -EINVAL; + } + } + + return 0; +} diff --git a/drivers/media/platform/chips-media/wave5/wave5-regdefine.h b/drivers/media/platform/chips-media/wave5/wave5-regdefine.h new file mode 100644 index 000000000000..79b2f17dd7f0 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-regdefine.h @@ -0,0 +1,743 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * Wave5 series multi-standard codec IP - wave5 register definitions + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#ifndef __WAVE5_REGISTER_DEFINE_H__ +#define __WAVE5_REGISTER_DEFINE_H__ + +enum W5_VPU_COMMAND { + W5_INIT_VPU = 0x0001, + W5_WAKEUP_VPU = 0x0002, + W5_SLEEP_VPU = 0x0004, + W5_CREATE_INSTANCE = 0x0008, /* queuing command */ + W5_FLUSH_INSTANCE = 0x0010, + W5_DESTROY_INSTANCE = 0x0020, /* queuing command */ + W5_INIT_SEQ = 0x0040, /* queuing command */ + W5_SET_FB = 0x0080, + W5_DEC_PIC = 0x0100, /* queuing command */ + W5_ENC_PIC = 0x0100, /* queuing command */ + W5_ENC_SET_PARAM = 0x0200, /* queuing command */ + W5_QUERY = 0x4000, + W5_UPDATE_BS = 0x8000, + W5_MAX_VPU_COMD = 0x10000, +}; + +enum QUERY_OPT { + GET_VPU_INFO = 0, + SET_WRITE_PROT = 1, + GET_RESULT = 2, + UPDATE_DISP_FLAG = 3, + GET_BW_REPORT = 4, + GET_BS_RD_PTR = 5, // for decoder + GET_BS_WR_PTR = 6, // for encoder + GET_SRC_BUF_FLAG = 7, // for encoder + SET_BS_RD_PTR = 8, // for decoder + GET_DEBUG_INFO = 0x61, +}; + +/* + * A flag of user data buffer full. + * User data buffer full flag equal to 1 specifies that de- + * coded frame has more user data size than VPU internal + * buffer. VPU only dumps the internal buffer size of us- + * er data to USER_DATA_BUF_BASE buffer. In other + * words, VPU is unable to report the rest of the user data to + * USER_DATA_BUF_BASE buffer after the internal buffer + * fullness happens. + */ +#define USERDATA_FLAG_BUFF_FULL 1 + +#define W5_REG_BASE 0x00000000 +#define W5_CMD_REG_BASE 0x00000100 +#define W5_CMD_REG_END 0x00000200 + +/* + * common + */ +/* power on configuration + * PO_DEBUG_MODE [0] 1 - power on with debug mode + * USE_PO_CONF [3] 1 - use power-on-configuration + */ +#define W5_PO_CONF (W5_REG_BASE + 0x0000) +#define W5_VCPU_CUR_PC (W5_REG_BASE + 0x0004) +#define W5_VCPU_CUR_LR (W5_REG_BASE + 0x0008) +#define W5_VPU_PDBG_STEP_MASK_V (W5_REG_BASE + 0x000C) +#define W5_VPU_PDBG_CTRL (W5_REG_BASE + 0x0010) // v_cpu debugger ctrl register +#define W5_VPU_PDBG_IDX_REG (W5_REG_BASE + 0x0014) // v_cpu debugger index register +#define W5_VPU_PDBG_WDATA_REG (W5_REG_BASE + 0x0018) // v_cpu debugger write data register +#define W5_VPU_PDBG_RDATA_REG (W5_REG_BASE + 0x001C) // v_cpu debugger read data register + +#define W5_VPU_FIO_CTRL_ADDR (W5_REG_BASE + 0x0020) +#define W5_VPU_FIO_DATA (W5_REG_BASE + 0x0024) +#define W5_VPU_VINT_REASON_USR (W5_REG_BASE + 0x0030) +#define W5_VPU_VINT_REASON_CLR (W5_REG_BASE + 0x0034) +#define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038) +#define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C) +#define W5_VPU_HINT_CLEAR (W5_REG_BASE + 0x0040) +#define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044) +#define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048) +#define W5_VPU_VINT_REASON (W5_REG_BASE + 0x004C) +#define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050) +#define W5_RST_BLOCK_CCLK(_core) BIT((_core)) +#define W5_RST_BLOCK_CCLK_ALL (0xff) +#define W5_RST_BLOCK_BCLK(_core) (0x100 << (_core)) +#define W5_RST_BLOCK_BCLK_ALL (0xff00) +#define W5_RST_BLOCK_ACLK(_core) (0x10000 << (_core)) +#define W5_RST_BLOCK_ACLK_ALL (0xff0000) +#define W5_RST_BLOCK_VCPU_ALL (0x3f000000) +#define W5_RST_BLOCK_ALL (0x3fffffff) +#define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054) + +#define W5_VCPU_RESTART (W5_REG_BASE + 0x0058) +#define W5_VPU_CLK_MASK (W5_REG_BASE + 0x005C) + +/* REMAP_CTRL + * PAGE SIZE: [8:0] 0x001 - 4K + * 0x002 - 8K + * 0x004 - 16K + * ... + * 0x100 - 1M + * REGION ATTR1 [10] 0 - normal + * 1 - make bus error for the region + * REGION ATTR2 [11] 0 - normal + * 1 - bypass region + * REMAP INDEX [15:12] - 0 ~ 3 + * ENDIAN [19:16] - see endian_mode in vdi.h + * AXI-ID [23:20] - upper AXI-ID + * BUS_ERROR [29] 0 - bypass + * 1 - make BUS_ERROR for unmapped region + * BYPASS_ALL [30] 1 - bypass all + * ENABLE [31] 1 - update control register[30:16] + */ +#define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060) +#define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064) +#define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068) +#define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C) +#define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070) +#define W5_VPU_HALT_STATUS (W5_REG_BASE + 0x0074) +#define W5_VPU_VCPU_STATUS (W5_REG_BASE + 0x0078) +#define W5_VPU_RET_PRODUCT_VERSION (W5_REG_BASE + 0x0094) +/* + * assign vpu_config0 = {conf_map_converter_reg, // [31] + * conf_map_converter_sig, // [30] + * 8'd0, // [29:22] + * conf_std_switch_en, // [21] + * conf_bg_detect, // [20] + * conf_3dnr_en, // [19] + * conf_one_axi_en, // [18] + * conf_sec_axi_en, // [17] + * conf_bus_info, // [16] + * conf_afbc_en, // [15] + * conf_afbc_version_id, // [14:12] + * conf_fbc_en, // [11] + * conf_fbc_version_id, // [10:08] + * conf_scaler_en, // [07] + * conf_scaler_version_id, // [06:04] + * conf_bwb_en, // [03] + * 3'd0}; // [02:00] + */ +#define W5_VPU_RET_VPU_CONFIG0 (W5_REG_BASE + 0x0098) +/* + * assign vpu_config1 = {4'd0, // [31:28] + * conf_perf_timer_en, // [27] + * conf_multi_core_en, // [26] + * conf_gcu_en, // [25] + * conf_cu_report, // [24] + * 4'd0, // [23:20] + * conf_vcore_id_3, // [19] + * conf_vcore_id_2, // [18] + * conf_vcore_id_1, // [17] + * conf_vcore_id_0, // [16] + * conf_bwb_opt, // [15] + * 7'd0, // [14:08] + * conf_cod_std_en_reserved_7, // [7] + * conf_cod_std_en_reserved_6, // [6] + * conf_cod_std_en_reserved_5, // [5] + * conf_cod_std_en_reserved_4, // [4] + * conf_cod_std_en_reserved_3, // [3] + * conf_cod_std_en_reserved_2, // [2] + * conf_cod_std_en_vp9, // [1] + * conf_cod_std_en_hevc}; // [0] + * } + */ +#define W5_VPU_RET_VPU_CONFIG1 (W5_REG_BASE + 0x009C) + +#define W5_VPU_DBG_REG0 (W5_REG_BASE + 0x00f0) +#define W5_VPU_DBG_REG1 (W5_REG_BASE + 0x00f4) +#define W5_VPU_DBG_REG2 (W5_REG_BASE + 0x00f8) +#define W5_VPU_DBG_REG3 (W5_REG_BASE + 0x00fc) + +/************************************************************************/ +/* PRODUCT INFORMATION */ +/************************************************************************/ +#define W5_PRODUCT_NAME (W5_REG_BASE + 0x1040) +#define W5_PRODUCT_NUMBER (W5_REG_BASE + 0x1044) + +/************************************************************************/ +/* DECODER/ENCODER COMMON */ +/************************************************************************/ +#define W5_COMMAND (W5_REG_BASE + 0x0100) +#define W5_COMMAND_OPTION (W5_REG_BASE + 0x0104) +#define W5_QUERY_OPTION (W5_REG_BASE + 0x0104) +#define W5_RET_SUCCESS (W5_REG_BASE + 0x0108) +#define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C) +#define W5_RET_QUEUE_FAIL_REASON (W5_REG_BASE + 0x0110) +#define W5_CMD_INSTANCE_INFO (W5_REG_BASE + 0x0110) + +#define W5_RET_QUEUE_STATUS (W5_REG_BASE + 0x01E0) +#define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4) +#define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8) +#define W5_RET_STAGE0_INSTANCE_INFO (W5_REG_BASE + 0x01EC) +#define W5_RET_STAGE1_INSTANCE_INFO (W5_REG_BASE + 0x01F0) +#define W5_RET_STAGE2_INSTANCE_INFO (W5_REG_BASE + 0x01F4) + +#define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC) + +#define W5_BS_OPTION (W5_REG_BASE + 0x0120) + +// return info when QUERY (GET_RESULT) for en/decoder +#define W5_RET_VLC_BUF_SIZE (W5_REG_BASE + 0x01B0) +// return info when QUERY (GET_RESULT) for en/decoder +#define W5_RET_PARAM_BUF_SIZE (W5_REG_BASE + 0x01B4) + +// set when SET_FB for en/decoder +#define W5_CMD_SET_FB_ADDR_TASK_BUF (W5_REG_BASE + 0x01D4) +#define W5_CMD_SET_FB_TASK_BUF_SIZE (W5_REG_BASE + 0x01D8) +/************************************************************************/ +/* INIT_VPU - COMMON */ +/************************************************************************/ +/* note: W5_ADDR_CODE_BASE should be aligned to 4KB */ +#define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110) +#define W5_CODE_SIZE (W5_REG_BASE + 0x0114) +#define W5_CODE_PARAM (W5_REG_BASE + 0x0118) +#define W5_ADDR_TEMP_BASE (W5_REG_BASE + 0x011C) +#define W5_TEMP_SIZE (W5_REG_BASE + 0x0120) +#define W5_ADDR_SEC_AXI (W5_REG_BASE + 0x0124) +#define W5_SEC_AXI_SIZE (W5_REG_BASE + 0x0128) +#define W5_HW_OPTION (W5_REG_BASE + 0x012C) +#define W5_SEC_AXI_PARAM (W5_REG_BASE + 0x0180) + +/************************************************************************/ +/* CREATE_INSTANCE - COMMON */ +/************************************************************************/ +#define W5_ADDR_WORK_BASE (W5_REG_BASE + 0x0114) +#define W5_WORK_SIZE (W5_REG_BASE + 0x0118) +#define W5_CMD_DEC_BS_START_ADDR (W5_REG_BASE + 0x011C) +#define W5_CMD_DEC_BS_SIZE (W5_REG_BASE + 0x0120) +#define W5_CMD_BS_PARAM (W5_REG_BASE + 0x0124) +#define W5_CMD_EXT_ADDR (W5_REG_BASE + 0x0138) +#define W5_CMD_NUM_CQ_DEPTH_M1 (W5_REG_BASE + 0x013C) +#define W5_CMD_ERR_CONCEAL (W5_REG_BASE + 0x0140) + +/************************************************************************/ +/* DECODER - INIT_SEQ */ +/************************************************************************/ +#define W5_BS_RD_PTR (W5_REG_BASE + 0x0118) +#define W5_BS_WR_PTR (W5_REG_BASE + 0x011C) +/************************************************************************/ +/* SET_FRAME_BUF */ +/************************************************************************/ +/* SET_FB_OPTION 0x00 REGISTER FRAMEBUFFERS + * 0x01 UPDATE FRAMEBUFFER, just one framebuffer(linear, fbc and mvcol) + */ +#define W5_SFB_OPTION (W5_REG_BASE + 0x0104) +#define W5_COMMON_PIC_INFO (W5_REG_BASE + 0x0118) +#define W5_PIC_SIZE (W5_REG_BASE + 0x011C) +#define W5_SET_FB_NUM (W5_REG_BASE + 0x0120) +#define W5_EXTRA_PIC_INFO (W5_REG_BASE + 0x0124) + +#define W5_ADDR_LUMA_BASE0 (W5_REG_BASE + 0x0134) +#define W5_ADDR_CB_BASE0 (W5_REG_BASE + 0x0138) +#define W5_ADDR_CR_BASE0 (W5_REG_BASE + 0x013C) +// compression offset table for luma +#define W5_ADDR_FBC_Y_OFFSET0 (W5_REG_BASE + 0x013C) +// compression offset table for chroma +#define W5_ADDR_FBC_C_OFFSET0 (W5_REG_BASE + 0x0140) +#define W5_ADDR_LUMA_BASE1 (W5_REG_BASE + 0x0144) +#define W5_ADDR_CB_ADDR1 (W5_REG_BASE + 0x0148) +#define W5_ADDR_CR_ADDR1 (W5_REG_BASE + 0x014C) +// compression offset table for luma +#define W5_ADDR_FBC_Y_OFFSET1 (W5_REG_BASE + 0x014C) +// compression offset table for chroma +#define W5_ADDR_FBC_C_OFFSET1 (W5_REG_BASE + 0x0150) +#define W5_ADDR_LUMA_BASE2 (W5_REG_BASE + 0x0154) +#define W5_ADDR_CB_ADDR2 (W5_REG_BASE + 0x0158) +#define W5_ADDR_CR_ADDR2 (W5_REG_BASE + 0x015C) +// compression offset table for luma +#define W5_ADDR_FBC_Y_OFFSET2 (W5_REG_BASE + 0x015C) +// compression offset table for chroma +#define W5_ADDR_FBC_C_OFFSET2 (W5_REG_BASE + 0x0160) +#define W5_ADDR_LUMA_BASE3 (W5_REG_BASE + 0x0164) +#define W5_ADDR_CB_ADDR3 (W5_REG_BASE + 0x0168) +#define W5_ADDR_CR_ADDR3 (W5_REG_BASE + 0x016C) +// compression offset table for luma +#define W5_ADDR_FBC_Y_OFFSET3 (W5_REG_BASE + 0x016C) +// compression offset table for chroma +#define W5_ADDR_FBC_C_OFFSET3 (W5_REG_BASE + 0x0170) +#define W5_ADDR_LUMA_BASE4 (W5_REG_BASE + 0x0174) +#define W5_ADDR_CB_ADDR4 (W5_REG_BASE + 0x0178) +#define W5_ADDR_CR_ADDR4 (W5_REG_BASE + 0x017C) +// compression offset table for luma +#define W5_ADDR_FBC_Y_OFFSET4 (W5_REG_BASE + 0x017C) +// compression offset table for chroma +#define W5_ADDR_FBC_C_OFFSET4 (W5_REG_BASE + 0x0180) +#define W5_ADDR_LUMA_BASE5 (W5_REG_BASE + 0x0184) +#define W5_ADDR_CB_ADDR5 (W5_REG_BASE + 0x0188) +#define W5_ADDR_CR_ADDR5 (W5_REG_BASE + 0x018C) +// compression offset table for luma +#define W5_ADDR_FBC_Y_OFFSET5 (W5_REG_BASE + 0x018C) +// compression offset table for chroma +#define W5_ADDR_FBC_C_OFFSET5 (W5_REG_BASE + 0x0190) +#define W5_ADDR_LUMA_BASE6 (W5_REG_BASE + 0x0194) +#define W5_ADDR_CB_ADDR6 (W5_REG_BASE + 0x0198) +#define W5_ADDR_CR_ADDR6 (W5_REG_BASE + 0x019C) +// compression offset table for luma +#define W5_ADDR_FBC_Y_OFFSET6 (W5_REG_BASE + 0x019C) +// compression offset table for chroma +#define W5_ADDR_FBC_C_OFFSET6 (W5_REG_BASE + 0x01A0) +#define W5_ADDR_LUMA_BASE7 (W5_REG_BASE + 0x01A4) +#define W5_ADDR_CB_ADDR7 (W5_REG_BASE + 0x01A8) +#define W5_ADDR_CR_ADDR7 (W5_REG_BASE + 0x01AC) +// compression offset table for luma +#define W5_ADDR_FBC_Y_OFFSET7 (W5_REG_BASE + 0x01AC) +// compression offset table for chroma +#define W5_ADDR_FBC_C_OFFSET7 (W5_REG_BASE + 0x01B0) +#define W5_ADDR_MV_COL0 (W5_REG_BASE + 0x01B4) +#define W5_ADDR_MV_COL1 (W5_REG_BASE + 0x01B8) +#define W5_ADDR_MV_COL2 (W5_REG_BASE + 0x01BC) +#define W5_ADDR_MV_COL3 (W5_REG_BASE + 0x01C0) +#define W5_ADDR_MV_COL4 (W5_REG_BASE + 0x01C4) +#define W5_ADDR_MV_COL5 (W5_REG_BASE + 0x01C8) +#define W5_ADDR_MV_COL6 (W5_REG_BASE + 0x01CC) +#define W5_ADDR_MV_COL7 (W5_REG_BASE + 0x01D0) + +/* UPDATE_FB */ +/* CMD_SET_FB_STRIDE [15:0] - FBC framebuffer stride + * [31:15] - linear framebuffer stride + */ +#define W5_CMD_SET_FB_STRIDE (W5_REG_BASE + 0x0118) +#define W5_CMD_SET_FB_INDEX (W5_REG_BASE + 0x0120) +#define W5_ADDR_LUMA_BASE (W5_REG_BASE + 0x0134) +#define W5_ADDR_CB_BASE (W5_REG_BASE + 0x0138) +#define W5_ADDR_CR_BASE (W5_REG_BASE + 0x013C) +#define W5_ADDR_MV_COL (W5_REG_BASE + 0x0140) +#define W5_ADDR_FBC_Y_BASE (W5_REG_BASE + 0x0144) +#define W5_ADDR_FBC_C_BASE (W5_REG_BASE + 0x0148) +#define W5_ADDR_FBC_Y_OFFSET (W5_REG_BASE + 0x014C) +#define W5_ADDR_FBC_C_OFFSET (W5_REG_BASE + 0x0150) + +/************************************************************************/ +/* DECODER - DEC_PIC */ +/************************************************************************/ +#define W5_CMD_DEC_VCORE_INFO (W5_REG_BASE + 0x0194) +/* sequence change enable mask register + * CMD_SEQ_CHANGE_ENABLE_FLAG [5] profile_idc + * [16] pic_width/height_in_luma_sample + * [19] sps_max_dec_pic_buffering, max_num_reorder, max_latency_increase + */ +#define W5_CMD_SEQ_CHANGE_ENABLE_FLAG (W5_REG_BASE + 0x0128) +#define W5_CMD_DEC_USER_MASK (W5_REG_BASE + 0x012C) +#define W5_CMD_DEC_TEMPORAL_ID_PLUS1 (W5_REG_BASE + 0x0130) +#define W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1 (W5_REG_BASE + 0x0134) +#define W5_USE_SEC_AXI (W5_REG_BASE + 0x0150) + +/************************************************************************/ +/* DECODER - QUERY : GET_VPU_INFO */ +/************************************************************************/ +#define W5_RET_FW_VERSION (W5_REG_BASE + 0x0118) +#define W5_RET_PRODUCT_NAME (W5_REG_BASE + 0x011C) +#define W5_RET_PRODUCT_VERSION (W5_REG_BASE + 0x0120) +#define W5_RET_STD_DEF0 (W5_REG_BASE + 0x0124) +#define W5_RET_STD_DEF1 (W5_REG_BASE + 0x0128) +#define W5_RET_CONF_FEATURE (W5_REG_BASE + 0x012C) +#define W5_RET_CONF_DATE (W5_REG_BASE + 0x0130) +#define W5_RET_CONF_REVISION (W5_REG_BASE + 0x0134) +#define W5_RET_CONF_TYPE (W5_REG_BASE + 0x0138) +#define W5_RET_PRODUCT_ID (W5_REG_BASE + 0x013C) +#define W5_RET_CUSTOMER_ID (W5_REG_BASE + 0x0140) + +/************************************************************************/ +/* DECODER - QUERY : GET_RESULT */ +/************************************************************************/ +#define W5_CMD_DEC_ADDR_REPORT_BASE (W5_REG_BASE + 0x0114) +#define W5_CMD_DEC_REPORT_SIZE (W5_REG_BASE + 0x0118) +#define W5_CMD_DEC_REPORT_PARAM (W5_REG_BASE + 0x011C) + +#define W5_RET_DEC_BS_RD_PTR (W5_REG_BASE + 0x011C) +#define W5_RET_DEC_SEQ_PARAM (W5_REG_BASE + 0x0120) +#define W5_RET_DEC_COLOR_SAMPLE_INFO (W5_REG_BASE + 0x0124) +#define W5_RET_DEC_ASPECT_RATIO (W5_REG_BASE + 0x0128) +#define W5_RET_DEC_BIT_RATE (W5_REG_BASE + 0x012C) +#define W5_RET_DEC_FRAME_RATE_NR (W5_REG_BASE + 0x0130) +#define W5_RET_DEC_FRAME_RATE_DR (W5_REG_BASE + 0x0134) +#define W5_RET_DEC_NUM_REQUIRED_FB (W5_REG_BASE + 0x0138) +#define W5_RET_DEC_NUM_REORDER_DELAY (W5_REG_BASE + 0x013C) +#define W5_RET_DEC_SUB_LAYER_INFO (W5_REG_BASE + 0x0140) +#define W5_RET_DEC_NOTIFICATION (W5_REG_BASE + 0x0144) +/* + * USER_DATA_FLAGS for HEVC/H264 only. + * Bits: + * [1] - User data buffer full boolean + * [2] - VUI parameter flag + * [4] - Pic_timing SEI flag + * [5] - 1st user_data_registed_itu_t_t35 prefix SEI flag + * [6] - user_data_unregistered prefix SEI flag + * [7] - 1st user_data_registed_itu_t_t35 suffix SEI flag + * [8] - user_data_unregistered suffix SEI flag + * [10]- mastering_display_color_volume prefix SEI flag + * [11]- chroma_resampling_display_color_volume prefix SEI flag + * [12]- knee_function_info SEI flag + * [13]- tone_mapping_info prefix SEI flag + * [14]- film_grain_characteristics_info prefix SEI flag + * [15]- content_light_level_info prefix SEI flag + * [16]- color_remapping_info prefix SEI flag + * [28]- 2nd user_data_registed_itu_t_t35 prefix SEI flag + * [29]- 3rd user_data_registed_itu_t_t35 prefix SEI flag + * [30]- 2nd user_data_registed_itu_t_t35 suffix SEI flag + * [31]- 3rd user_data_registed_itu_t_t35 suffix SEI flag + */ +#define W5_RET_DEC_USERDATA_IDC (W5_REG_BASE + 0x0148) +#define W5_RET_DEC_PIC_SIZE (W5_REG_BASE + 0x014C) +#define W5_RET_DEC_CROP_TOP_BOTTOM (W5_REG_BASE + 0x0150) +#define W5_RET_DEC_CROP_LEFT_RIGHT (W5_REG_BASE + 0x0154) +/* + * #define W5_RET_DEC_AU_START_POS (W5_REG_BASE + 0x0158) + * => Access unit (AU) Bitstream start position + * #define W5_RET_DEC_AU_END_POS (W5_REG_BASE + 0x015C) + * => Access unit (AU) Bitstream end position + */ + +/* + * Decoded picture type: + * reg_val & 0x7 => picture type + * (reg_val >> 4) & 0x3f => VCL NAL unit type + * (reg_val >> 31) & 0x1 => output_flag + * 16 << ((reg_val >> 10) & 0x3) => ctu_size + */ +#define W5_RET_DEC_PIC_TYPE (W5_REG_BASE + 0x0160) +#define W5_RET_DEC_PIC_POC (W5_REG_BASE + 0x0164) +/* + * #define W5_RET_DEC_RECOVERY_POINT (W5_REG_BASE + 0x0168) + * => HEVC recovery point + * reg_val & 0xff => number of signed recovery picture order counts + * (reg_val >> 16) & 0x1 => exact match flag + * (reg_val >> 17) & 0x1 => broken link flag + * (reg_val >> 18) & 0x1 => exist flag + */ +#define W5_RET_DEC_DEBUG_INDEX (W5_REG_BASE + 0x016C) +#define W5_RET_DEC_DECODED_INDEX (W5_REG_BASE + 0x0170) +#define W5_RET_DEC_DISPLAY_INDEX (W5_REG_BASE + 0x0174) +/* + * #define W5_RET_DEC_REALLOC_INDEX (W5_REG_BASE + 0x0178) + * => display picture index in decoded picture buffer + * reg_val & 0xf => display picture index for FBC buffer (by reordering) + */ +#define W5_RET_DEC_DISP_IDC (W5_REG_BASE + 0x017C) +/* + * #define W5_RET_DEC_ERR_CTB_NUM (W5_REG_BASE + 0x0180) + * => Number of error CTUs + * reg_val >> 16 => erroneous CTUs in bitstream + * reg_val & 0xffff => total CTUs in bitstream + * + * #define W5_RET_DEC_PIC_PARAM (W5_REG_BASE + 0x01A0) + * => Bitstream sequence/picture parameter information (AV1 only) + * reg_val & 0x1 => intrabc tool enable + * (reg_val >> 1) & 0x1 => screen content tools enable + */ +#define W5_RET_DEC_HOST_CMD_TICK (W5_REG_BASE + 0x01B8) +/* + * #define W5_RET_DEC_SEEK_START_TICK (W5_REG_BASE + 0x01BC) + * #define W5_RET_DEC_SEEK_END_TICK (W5_REG_BASE + 0x01C0) + * => Start and end ticks for seeking slices of the picture + * #define W5_RET_DEC_PARSING_START_TICK (W5_REG_BASE + 0x01C4) + * #define W5_RET_DEC_PARSING_END_TICK (W5_REG_BASE + 0x01C8) + * => Start and end ticks for parsing slices of the picture + * #define W5_RET_DEC_DECODING_START_TICK (W5_REG_BASE + 0x01CC) + * => Start tick for decoding slices of the picture + */ +#define W5_RET_DEC_DECODING_ENC_TICK (W5_REG_BASE + 0x01D0) +#define W5_RET_DEC_WARN_INFO (W5_REG_BASE + 0x01D4) +#define W5_RET_DEC_ERR_INFO (W5_REG_BASE + 0x01D8) +#define W5_RET_DEC_DECODING_SUCCESS (W5_REG_BASE + 0x01DC) + +/************************************************************************/ +/* DECODER - FLUSH_INSTANCE */ +/************************************************************************/ +#define W5_CMD_FLUSH_INST_OPT (W5_REG_BASE + 0x104) + +/************************************************************************/ +/* DECODER - QUERY : UPDATE_DISP_FLAG */ +/************************************************************************/ +#define W5_CMD_DEC_SET_DISP_IDC (W5_REG_BASE + 0x0118) +#define W5_CMD_DEC_CLR_DISP_IDC (W5_REG_BASE + 0x011C) + +/************************************************************************/ +/* DECODER - QUERY : SET_BS_RD_PTR */ +/************************************************************************/ +#define W5_RET_QUERY_DEC_SET_BS_RD_PTR (W5_REG_BASE + 0x011C) + +/************************************************************************/ +/* DECODER - QUERY : GET_BS_RD_PTR */ +/************************************************************************/ +#define W5_RET_QUERY_DEC_BS_RD_PTR (W5_REG_BASE + 0x011C) + +/************************************************************************/ +/* QUERY : GET_DEBUG_INFO */ +/************************************************************************/ +#define W5_RET_QUERY_DEBUG_PRI_REASON (W5_REG_BASE + 0x114) + +/************************************************************************/ +/* GDI register for debugging */ +/************************************************************************/ +#define W5_GDI_BASE 0x8800 +#define W5_GDI_BUS_CTRL (W5_GDI_BASE + 0x0F0) +#define W5_GDI_BUS_STATUS (W5_GDI_BASE + 0x0F4) + +#define W5_BACKBONE_BASE_VCPU 0xFE00 +#define W5_BACKBONE_BUS_CTRL_VCPU (W5_BACKBONE_BASE_VCPU + 0x010) +#define W5_BACKBONE_BUS_STATUS_VCPU (W5_BACKBONE_BASE_VCPU + 0x014) +#define W5_BACKBONE_PROG_AXI_ID (W5_BACKBONE_BASE_VCPU + 0x00C) + +#define W5_BACKBONE_PROC_EXT_ADDR (W5_BACKBONE_BASE_VCPU + 0x0C0) +#define W5_BACKBONE_AXI_PARAM (W5_BACKBONE_BASE_VCPU + 0x0E0) + +#define W5_BACKBONE_BASE_VCORE0 0x8E00 +#define W5_BACKBONE_BUS_CTRL_VCORE0 (W5_BACKBONE_BASE_VCORE0 + 0x010) +#define W5_BACKBONE_BUS_STATUS_VCORE0 (W5_BACKBONE_BASE_VCORE0 + 0x014) + +#define W5_BACKBONE_BASE_VCORE1 0x9E00 // for dual-core product +#define W5_BACKBONE_BUS_CTRL_VCORE1 (W5_BACKBONE_BASE_VCORE1 + 0x010) +#define W5_BACKBONE_BUS_STATUS_VCORE1 (W5_BACKBONE_BASE_VCORE1 + 0x014) + +#define W5_COMBINED_BACKBONE_BASE 0xFE00 +#define W5_COMBINED_BACKBONE_BUS_CTRL (W5_COMBINED_BACKBONE_BASE + 0x010) +#define W5_COMBINED_BACKBONE_BUS_STATUS (W5_COMBINED_BACKBONE_BASE + 0x014) + +/************************************************************************/ +/* */ +/* for ENCODER */ +/* */ +/************************************************************************/ +#define W5_RET_STAGE3_INSTANCE_INFO (W5_REG_BASE + 0x1F8) +/************************************************************************/ +/* ENCODER - CREATE_INSTANCE */ +/************************************************************************/ +// 0x114 ~ 0x124 : defined above (CREATE_INSTANCE COMMON) +#define W5_CMD_ENC_VCORE_INFO (W5_REG_BASE + 0x0194) +#define W5_CMD_ENC_SRC_OPTIONS (W5_REG_BASE + 0x0128) + +/************************************************************************/ +/* ENCODER - SET_FB */ +/************************************************************************/ +#define W5_FBC_STRIDE (W5_REG_BASE + 0x128) +#define W5_ADDR_SUB_SAMPLED_FB_BASE (W5_REG_BASE + 0x12C) +#define W5_SUB_SAMPLED_ONE_FB_SIZE (W5_REG_BASE + 0x130) + +/************************************************************************/ +/* ENCODER - ENC_SET_PARAM (COMMON & CHANGE_PARAM) */ +/************************************************************************/ +#define W5_CMD_ENC_SEQ_SET_PARAM_OPTION (W5_REG_BASE + 0x104) +#define W5_CMD_ENC_SEQ_SET_PARAM_ENABLE (W5_REG_BASE + 0x118) +#define W5_CMD_ENC_SEQ_SRC_SIZE (W5_REG_BASE + 0x11C) +#define W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN (W5_REG_BASE + 0x120) +#define W5_CMD_ENC_SEQ_SPS_PARAM (W5_REG_BASE + 0x124) +#define W5_CMD_ENC_SEQ_PPS_PARAM (W5_REG_BASE + 0x128) +#define W5_CMD_ENC_SEQ_GOP_PARAM (W5_REG_BASE + 0x12C) +#define W5_CMD_ENC_SEQ_INTRA_PARAM (W5_REG_BASE + 0x130) +#define W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT (W5_REG_BASE + 0x134) +#define W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT (W5_REG_BASE + 0x138) +#define W5_CMD_ENC_SEQ_RDO_PARAM (W5_REG_BASE + 0x13C) +#define W5_CMD_ENC_SEQ_INDEPENDENT_SLICE (W5_REG_BASE + 0x140) +#define W5_CMD_ENC_SEQ_DEPENDENT_SLICE (W5_REG_BASE + 0x144) +#define W5_CMD_ENC_SEQ_INTRA_REFRESH (W5_REG_BASE + 0x148) +#define W5_CMD_ENC_SEQ_INPUT_SRC_PARAM (W5_REG_BASE + 0x14C) + +#define W5_CMD_ENC_SEQ_RC_FRAME_RATE (W5_REG_BASE + 0x150) +#define W5_CMD_ENC_SEQ_RC_TARGET_RATE (W5_REG_BASE + 0x154) +#define W5_CMD_ENC_SEQ_RC_PARAM (W5_REG_BASE + 0x158) +#define W5_CMD_ENC_SEQ_RC_MIN_MAX_QP (W5_REG_BASE + 0x15C) +#define W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3 (W5_REG_BASE + 0x160) +#define W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7 (W5_REG_BASE + 0x164) +#define W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP (W5_REG_BASE + 0x168) +#define W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM (W5_REG_BASE + 0x16C) + +#define W5_CMD_ENC_SEQ_ROT_PARAM (W5_REG_BASE + 0x170) +#define W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK (W5_REG_BASE + 0x174) +#define W5_CMD_ENC_SEQ_TIME_SCALE (W5_REG_BASE + 0x178) +#define W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE (W5_REG_BASE + 0x17C) + +#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU04 (W5_REG_BASE + 0x184) +#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU08 (W5_REG_BASE + 0x188) +#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU16 (W5_REG_BASE + 0x18C) +#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU32 (W5_REG_BASE + 0x190) +#define W5_CMD_ENC_SEQ_CUSTOM_MD_CU08 (W5_REG_BASE + 0x194) +#define W5_CMD_ENC_SEQ_CUSTOM_MD_CU16 (W5_REG_BASE + 0x198) +#define W5_CMD_ENC_SEQ_CUSTOM_MD_CU32 (W5_REG_BASE + 0x19C) +#define W5_CMD_ENC_SEQ_NR_PARAM (W5_REG_BASE + 0x1A0) +#define W5_CMD_ENC_SEQ_NR_WEIGHT (W5_REG_BASE + 0x1A4) +#define W5_CMD_ENC_SEQ_BG_PARAM (W5_REG_BASE + 0x1A8) +#define W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR (W5_REG_BASE + 0x1AC) +#define W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR (W5_REG_BASE + 0x1B0) +#define W5_CMD_ENC_SEQ_VUI_HRD_PARAM (W5_REG_BASE + 0x180) +#define W5_CMD_ENC_SEQ_VUI_RBSP_ADDR (W5_REG_BASE + 0x1B8) +#define W5_CMD_ENC_SEQ_HRD_RBSP_ADDR (W5_REG_BASE + 0x1BC) + +/************************************************************************/ +/* ENCODER - ENC_SET_PARAM (CUSTOM_GOP) */ +/************************************************************************/ +#define W5_CMD_ENC_CUSTOM_GOP_PARAM (W5_REG_BASE + 0x11C) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 (W5_REG_BASE + 0x120) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_1 (W5_REG_BASE + 0x124) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_2 (W5_REG_BASE + 0x128) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_3 (W5_REG_BASE + 0x12C) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_4 (W5_REG_BASE + 0x130) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_5 (W5_REG_BASE + 0x134) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_6 (W5_REG_BASE + 0x138) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_7 (W5_REG_BASE + 0x13C) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_8 (W5_REG_BASE + 0x140) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_9 (W5_REG_BASE + 0x144) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_10 (W5_REG_BASE + 0x148) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_11 (W5_REG_BASE + 0x14C) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_12 (W5_REG_BASE + 0x150) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_13 (W5_REG_BASE + 0x154) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_14 (W5_REG_BASE + 0x158) +#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_15 (W5_REG_BASE + 0x15C) + +/************************************************************************/ +/* ENCODER - ENC_PIC */ +/************************************************************************/ +#define W5_CMD_ENC_BS_START_ADDR (W5_REG_BASE + 0x118) +#define W5_CMD_ENC_BS_SIZE (W5_REG_BASE + 0x11C) +#define W5_CMD_ENC_PIC_USE_SEC_AXI (W5_REG_BASE + 0x124) +#define W5_CMD_ENC_PIC_REPORT_PARAM (W5_REG_BASE + 0x128) + +#define W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM (W5_REG_BASE + 0x138) +#define W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR (W5_REG_BASE + 0x13C) +#define W5_CMD_ENC_PIC_SRC_PIC_IDX (W5_REG_BASE + 0x144) +#define W5_CMD_ENC_PIC_SRC_ADDR_Y (W5_REG_BASE + 0x148) +#define W5_CMD_ENC_PIC_SRC_ADDR_U (W5_REG_BASE + 0x14C) +#define W5_CMD_ENC_PIC_SRC_ADDR_V (W5_REG_BASE + 0x150) +#define W5_CMD_ENC_PIC_SRC_STRIDE (W5_REG_BASE + 0x154) +#define W5_CMD_ENC_PIC_SRC_FORMAT (W5_REG_BASE + 0x158) +#define W5_CMD_ENC_PIC_SRC_AXI_SEL (W5_REG_BASE + 0x160) +#define W5_CMD_ENC_PIC_CODE_OPTION (W5_REG_BASE + 0x164) +#define W5_CMD_ENC_PIC_PIC_PARAM (W5_REG_BASE + 0x168) +#define W5_CMD_ENC_PIC_LONGTERM_PIC (W5_REG_BASE + 0x16C) +#define W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y (W5_REG_BASE + 0x170) +#define W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C (W5_REG_BASE + 0x174) +#define W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y (W5_REG_BASE + 0x178) +#define W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C (W5_REG_BASE + 0x17C) +#define W5_CMD_ENC_PIC_CF50_Y_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x190) +#define W5_CMD_ENC_PIC_CF50_CB_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x194) +#define W5_CMD_ENC_PIC_CF50_CR_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x198) +#define W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR (W5_REG_BASE + 0x180) +#define W5_CMD_ENC_PIC_PREFIX_SEI_INFO (W5_REG_BASE + 0x184) +#define W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR (W5_REG_BASE + 0x188) +#define W5_CMD_ENC_PIC_SUFFIX_SEI_INFO (W5_REG_BASE + 0x18c) + +/************************************************************************/ +/* ENCODER - QUERY (GET_RESULT) */ +/************************************************************************/ +#define W5_RET_ENC_NUM_REQUIRED_FB (W5_REG_BASE + 0x11C) +#define W5_RET_ENC_MIN_SRC_BUF_NUM (W5_REG_BASE + 0x120) +#define W5_RET_ENC_PIC_TYPE (W5_REG_BASE + 0x124) +/* + * #define W5_RET_ENC_PIC_POC (W5_REG_BASE + 0x128) + * => picture order count value of current encoded picture + */ +#define W5_RET_ENC_PIC_IDX (W5_REG_BASE + 0x12C) +/* + * #define W5_RET_ENC_PIC_SLICE_NUM (W5_REG_BASE + 0x130) + * reg_val & 0xffff = total independent slice segment number (16 bits) + * (reg_val >> 16) & 0xffff = total dependent slice segment number (16 bits) + * + * #define W5_RET_ENC_PIC_SKIP (W5_REG_BASE + 0x134) + * reg_val & 0xfe = picture skip flag (7 bits) + * + * #define W5_RET_ENC_PIC_NUM_INTRA (W5_REG_BASE + 0x138) + * => number of intra blocks in 8x8 (32 bits) + * + * #define W5_RET_ENC_PIC_NUM_MERGE (W5_REG_BASE + 0x13C) + * => number of merge blocks in 8x8 (32 bits) + * + * #define W5_RET_ENC_PIC_NUM_SKIP (W5_REG_BASE + 0x144) + * => number of skip blocks in 8x8 (32 bits) + * + * #define W5_RET_ENC_PIC_AVG_CTU_QP (W5_REG_BASE + 0x148) + * => Average CTU QP value (32 bits) + */ +#define W5_RET_ENC_PIC_BYTE (W5_REG_BASE + 0x14C) +/* + * #define W5_RET_ENC_GOP_PIC_IDX (W5_REG_BASE + 0x150) + * => picture index in group of pictures + */ +#define W5_RET_ENC_USED_SRC_IDX (W5_REG_BASE + 0x154) +/* + * #define W5_RET_ENC_PIC_NUM (W5_REG_BASE + 0x158) + * => encoded picture number + */ +#define W5_RET_ENC_VCL_NUT (W5_REG_BASE + 0x15C) +/* + * Only for H264: + * #define W5_RET_ENC_PIC_DIST_LOW (W5_REG_BASE + 0x164) + * => lower 32 bits of the sum of squared difference between source Y picture + * and reconstructed Y picture + * #define W5_RET_ENC_PIC_DIST_HIGH (W5_REG_BASE + 0x168) + * => upper 32 bits of the sum of squared difference between source Y picture + * and reconstructed Y picture + */ +#define W5_RET_ENC_PIC_MAX_LATENCY_PICS (W5_REG_BASE + 0x16C) + +#define W5_RET_ENC_HOST_CMD_TICK (W5_REG_BASE + 0x1B8) +/* + * #define W5_RET_ENC_PREPARE_START_TICK (W5_REG_BASE + 0x1BC) + * #define W5_RET_ENC_PREPARE_END_TICK (W5_REG_BASE + 0x1C0) + * => Start and end ticks for preparing slices of the picture + * #define W5_RET_ENC_PROCESSING_START_TICK (W5_REG_BASE + 0x1C4) + * #define W5_RET_ENC_PROCESSING_END_TICK (W5_REG_BASE + 0x1C8) + * => Start and end ticks for processing slices of the picture + * #define W5_RET_ENC_ENCODING_START_TICK (W5_REG_BASE + 0x1CC) + * => Start tick for encoding slices of the picture + */ +#define W5_RET_ENC_ENCODING_END_TICK (W5_REG_BASE + 0x1D0) + +#define W5_RET_ENC_WARN_INFO (W5_REG_BASE + 0x1D4) +#define W5_RET_ENC_ERR_INFO (W5_REG_BASE + 0x1D8) +#define W5_RET_ENC_ENCODING_SUCCESS (W5_REG_BASE + 0x1DC) + +/************************************************************************/ +/* ENCODER - QUERY (GET_BS_WR_PTR) */ +/************************************************************************/ +#define W5_RET_ENC_RD_PTR (W5_REG_BASE + 0x114) +#define W5_RET_ENC_WR_PTR (W5_REG_BASE + 0x118) +#define W5_CMD_ENC_REASON_SEL (W5_REG_BASE + 0x11C) + +/************************************************************************/ +/* ENCODER - QUERY (GET_BW_REPORT) */ +/************************************************************************/ +#define RET_QUERY_BW_PRP_AXI_READ (W5_REG_BASE + 0x118) +#define RET_QUERY_BW_PRP_AXI_WRITE (W5_REG_BASE + 0x11C) +#define RET_QUERY_BW_FBD_Y_AXI_READ (W5_REG_BASE + 0x120) +#define RET_QUERY_BW_FBC_Y_AXI_WRITE (W5_REG_BASE + 0x124) +#define RET_QUERY_BW_FBD_C_AXI_READ (W5_REG_BASE + 0x128) +#define RET_QUERY_BW_FBC_C_AXI_WRITE (W5_REG_BASE + 0x12C) +#define RET_QUERY_BW_PRI_AXI_READ (W5_REG_BASE + 0x130) +#define RET_QUERY_BW_PRI_AXI_WRITE (W5_REG_BASE + 0x134) +#define RET_QUERY_BW_SEC_AXI_READ (W5_REG_BASE + 0x138) +#define RET_QUERY_BW_SEC_AXI_WRITE (W5_REG_BASE + 0x13C) +#define RET_QUERY_BW_PROC_AXI_READ (W5_REG_BASE + 0x140) +#define RET_QUERY_BW_PROC_AXI_WRITE (W5_REG_BASE + 0x144) +#define RET_QUERY_BW_BWB_AXI_WRITE (W5_REG_BASE + 0x148) +#define W5_CMD_BW_OPTION (W5_REG_BASE + 0x14C) + +/************************************************************************/ +/* ENCODER - QUERY (GET_SRC_FLAG) */ +/************************************************************************/ +#define W5_RET_RELEASED_SRC_INSTANCE (W5_REG_BASE + 0x1EC) + +#define W5_ENC_PIC_SUB_FRAME_SYNC_IF (W5_REG_BASE + 0x0300) + +#endif /* __WAVE5_REGISTER_DEFINE_H__ */ diff --git a/drivers/media/platform/chips-media/wave5/wave5-vdi.c b/drivers/media/platform/chips-media/wave5/wave5-vdi.c new file mode 100644 index 000000000000..8c7c090b4fc2 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-vdi.c @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Wave5 series multi-standard codec IP - low level access functions + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#include <linux/bug.h> +#include "wave5-vdi.h" +#include "wave5-vpu.h" +#include "wave5-regdefine.h" +#include <linux/delay.h> + +#define VDI_SRAM_BASE_ADDR 0x00 + +#define VDI_SYSTEM_ENDIAN VDI_LITTLE_ENDIAN +#define VDI_128BIT_BUS_SYSTEM_ENDIAN VDI_128BIT_LITTLE_ENDIAN + +static int wave5_vdi_allocate_common_memory(struct device *dev) +{ + struct vpu_device *vpu_dev = dev_get_drvdata(dev); + + if (!vpu_dev->common_mem.vaddr) { + int ret; + + vpu_dev->common_mem.size = SIZE_COMMON; + ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vpu_dev->common_mem); + if (ret) { + dev_err(dev, "unable to allocate common buffer\n"); + return ret; + } + } + + dev_dbg(dev, "[VDI] common_mem: daddr=%pad size=%zu vaddr=0x%p\n", + &vpu_dev->common_mem.daddr, vpu_dev->common_mem.size, vpu_dev->common_mem.vaddr); + + return 0; +} + +int wave5_vdi_init(struct device *dev) +{ + struct vpu_device *vpu_dev = dev_get_drvdata(dev); + int ret; + + ret = wave5_vdi_allocate_common_memory(dev); + if (ret < 0) { + dev_err(dev, "[VDI] failed to get vpu common buffer from driver\n"); + return ret; + } + + if (!PRODUCT_CODE_W_SERIES(vpu_dev->product_code)) { + WARN_ONCE(1, "unsupported product code: 0x%x\n", vpu_dev->product_code); + return 0; + } + + // if BIT processor is not running. + if (wave5_vdi_readl(vpu_dev, W5_VCPU_CUR_PC) == 0) { + int i; + + for (i = 0; i < 64; i++) + wave5_vdi_write_register(vpu_dev, (i * 4) + 0x100, 0x0); + } + + dev_dbg(dev, "[VDI] driver initialized successfully\n"); + + return 0; +} + +int wave5_vdi_release(struct device *dev) +{ + struct vpu_device *vpu_dev = dev_get_drvdata(dev); + + vpu_dev->vdb_register = NULL; + wave5_vdi_free_dma_memory(vpu_dev, &vpu_dev->common_mem); + + return 0; +} + +void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data) +{ + writel(data, vpu_dev->vdb_register + addr); +} + +unsigned int wave5_vdi_readl(struct vpu_device *vpu_dev, u32 addr) +{ + return readl(vpu_dev->vdb_register + addr); +} + +int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb) +{ + if (!vb || !vb->vaddr) { + dev_err(vpu_dev->dev, "%s: unable to clear unmapped buffer\n", __func__); + return -EINVAL; + } + + memset(vb->vaddr, 0, vb->size); + return vb->size; +} + +static void wave5_swap_endian(struct vpu_device *vpu_dev, u8 *data, size_t len, + unsigned int endian); + +int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset, + u8 *data, size_t len, unsigned int endian) +{ + if (!vb || !vb->vaddr) { + dev_err(vpu_dev->dev, "%s: unable to write to unmapped buffer\n", __func__); + return -EINVAL; + } + + if (offset > vb->size || len > vb->size || offset + len > vb->size) { + dev_err(vpu_dev->dev, "%s: buffer too small\n", __func__); + return -ENOSPC; + } + + wave5_swap_endian(vpu_dev, data, len, endian); + memcpy(vb->vaddr + offset, data, len); + + return len; +} + +int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb) +{ + void *vaddr; + dma_addr_t daddr; + + if (!vb->size) { + dev_err(vpu_dev->dev, "%s: requested size==0\n", __func__); + return -EINVAL; + } + + vaddr = dma_alloc_coherent(vpu_dev->dev, vb->size, &daddr, GFP_KERNEL); + if (!vaddr) + return -ENOMEM; + vb->vaddr = vaddr; + vb->daddr = daddr; + + return 0; +} + +void wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb) +{ + if (vb->size == 0) + return; + + if (!vb->vaddr) + dev_err(vpu_dev->dev, "%s: requested free of unmapped buffer\n", __func__); + else + dma_free_coherent(vpu_dev->dev, vb->size, vb->vaddr, vb->daddr); + + memset(vb, 0, sizeof(*vb)); +} + +unsigned int wave5_vdi_convert_endian(struct vpu_device *vpu_dev, unsigned int endian) +{ + if (PRODUCT_CODE_W_SERIES(vpu_dev->product_code)) { + switch (endian) { + case VDI_LITTLE_ENDIAN: + endian = 0x00; + break; + case VDI_BIG_ENDIAN: + endian = 0x0f; + break; + case VDI_32BIT_LITTLE_ENDIAN: + endian = 0x04; + break; + case VDI_32BIT_BIG_ENDIAN: + endian = 0x03; + break; + } + } + + return (endian & 0x0f); +} + +static void byte_swap(unsigned char *data, size_t len) +{ + unsigned int i; + + for (i = 0; i < len; i += 2) + swap(data[i], data[i + 1]); +} + +static void word_swap(unsigned char *data, size_t len) +{ + u16 *ptr = (u16 *)data; + unsigned int i; + size_t size = len / sizeof(uint16_t); + + for (i = 0; i < size; i += 2) + swap(ptr[i], ptr[i + 1]); +} + +static void dword_swap(unsigned char *data, size_t len) +{ + u32 *ptr = (u32 *)data; + size_t size = len / sizeof(u32); + unsigned int i; + + for (i = 0; i < size; i += 2) + swap(ptr[i], ptr[i + 1]); +} + +static void lword_swap(unsigned char *data, size_t len) +{ + u64 *ptr = (u64 *)data; + size_t size = len / sizeof(uint64_t); + unsigned int i; + + for (i = 0; i < size; i += 2) + swap(ptr[i], ptr[i + 1]); +} + +static void wave5_swap_endian(struct vpu_device *vpu_dev, u8 *data, size_t len, + unsigned int endian) +{ + int changes; + unsigned int sys_endian = VDI_128BIT_BUS_SYSTEM_ENDIAN; + bool byte_change, word_change, dword_change, lword_change; + + if (!PRODUCT_CODE_W_SERIES(vpu_dev->product_code)) { + dev_err(vpu_dev->dev, "unknown product id: %08x\n", vpu_dev->product_code); + return; + } + + endian = wave5_vdi_convert_endian(vpu_dev, endian); + sys_endian = wave5_vdi_convert_endian(vpu_dev, sys_endian); + if (endian == sys_endian) + return; + + changes = endian ^ sys_endian; + byte_change = changes & 0x01; + word_change = ((changes & 0x02) == 0x02); + dword_change = ((changes & 0x04) == 0x04); + lword_change = ((changes & 0x08) == 0x08); + + if (byte_change) + byte_swap(data, len); + if (word_change) + word_swap(data, len); + if (dword_change) + dword_swap(data, len); + if (lword_change) + lword_swap(data, len); +} diff --git a/drivers/media/platform/chips-media/wave5/wave5-vdi.h b/drivers/media/platform/chips-media/wave5/wave5-vdi.h new file mode 100644 index 000000000000..780be5747332 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-vdi.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * Wave5 series multi-standard codec IP - low level access functions + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#ifndef _VDI_H_ +#define _VDI_H_ + +#include "wave5-vpuconfig.h" +#include <linux/string.h> +#include <linux/slab.h> +#include <linux/device.h> + +/************************************************************************/ +/* COMMON REGISTERS */ +/************************************************************************/ +#define VPU_PRODUCT_CODE_REGISTER 0x1044 + +/* system register write */ +#define vpu_write_reg(VPU_INST, ADDR, DATA) wave5_vdi_write_register(VPU_INST, ADDR, DATA) +/* system register read */ +#define vpu_read_reg(CORE, ADDR) wave5_vdi_readl(CORE, ADDR) + +struct vpu_buf { + size_t size; + dma_addr_t daddr; + void *vaddr; +}; + +struct dma_vpu_buf { + size_t size; + dma_addr_t daddr; +}; + +enum endian_mode { + VDI_LITTLE_ENDIAN = 0, /* 64bit LE */ + VDI_BIG_ENDIAN, /* 64bit BE */ + VDI_32BIT_LITTLE_ENDIAN, + VDI_32BIT_BIG_ENDIAN, + /* WAVE PRODUCTS */ + VDI_128BIT_LITTLE_ENDIAN = 16, + VDI_128BIT_LE_BYTE_SWAP, + VDI_128BIT_LE_WORD_SWAP, + VDI_128BIT_LE_WORD_BYTE_SWAP, + VDI_128BIT_LE_DWORD_SWAP, + VDI_128BIT_LE_DWORD_BYTE_SWAP, + VDI_128BIT_LE_DWORD_WORD_SWAP, + VDI_128BIT_LE_DWORD_WORD_BYTE_SWAP, + VDI_128BIT_BE_DWORD_WORD_BYTE_SWAP, + VDI_128BIT_BE_DWORD_WORD_SWAP, + VDI_128BIT_BE_DWORD_BYTE_SWAP, + VDI_128BIT_BE_DWORD_SWAP, + VDI_128BIT_BE_WORD_BYTE_SWAP, + VDI_128BIT_BE_WORD_SWAP, + VDI_128BIT_BE_BYTE_SWAP, + VDI_128BIT_BIG_ENDIAN = 31, + VDI_ENDIAN_MAX +}; + +#define VDI_128BIT_ENDIAN_MASK 0xf + +int wave5_vdi_init(struct device *dev); +int wave5_vdi_release(struct device *dev); //this function may be called only at system off. + +#endif //#ifndef _VDI_H_ diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c new file mode 100644 index 000000000000..1458c5587dbc --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c @@ -0,0 +1,1040 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Wave5 series multi-standard codec IP - helper functions + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#include <linux/bug.h> +#include "wave5-vpuapi.h" +#include "wave5-regdefine.h" +#include "wave5.h" + +#define DECODE_ALL_TEMPORAL_LAYERS 0 +#define DECODE_ALL_SPATIAL_LAYERS 0 + +void wave5_vpu_clear_interrupt_ex(struct vpu_instance *inst, u32 intr_flag) +{ + wave5_vpu_clear_interrupt(inst, intr_flag); +} + +static int wave5_initialize_vpu(struct device *dev, u8 *code, size_t size) +{ + int ret; + struct vpu_device *vpu_dev = dev_get_drvdata(dev); + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + if (wave5_vpu_is_init(vpu_dev)) { + wave5_vpu_re_init(dev, (void *)code, size); + ret = -EBUSY; + goto err_out; + } + + ret = wave5_vpu_reset(dev, SW_RESET_ON_BOOT); + if (ret) + goto err_out; + + ret = wave5_vpu_init(dev, (void *)code, size); + +err_out: + mutex_unlock(&vpu_dev->hw_lock); + return ret; +} + +int wave5_vpu_init_with_bitcode(struct device *dev, u8 *bitcode, size_t size) +{ + if (!bitcode || size == 0) + return -EINVAL; + + return wave5_initialize_vpu(dev, bitcode, size); +} + +int wave5_vpu_get_version_info(struct device *dev, u32 *revision, unsigned int *product_id) +{ + int ret; + struct vpu_device *vpu_dev = dev_get_drvdata(dev); + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + if (!wave5_vpu_is_init(vpu_dev)) { + ret = -EINVAL; + goto err_out; + } + + if (product_id) + *product_id = vpu_dev->product; + ret = wave5_vpu_get_version(vpu_dev, revision); + +err_out: + mutex_unlock(&vpu_dev->hw_lock); + return ret; +} + +static int wave5_check_dec_open_param(struct vpu_instance *inst, struct dec_open_param *param) +{ + struct vpu_attr *p_attr = &inst->dev->attr; + + if (inst->id >= MAX_NUM_INSTANCE) { + dev_err(inst->dev->dev, "Too many simultaneous instances: %d (max: %u)\n", + inst->id, MAX_NUM_INSTANCE); + return -EOPNOTSUPP; + } + + if (param->bitstream_buffer % 8) { + dev_err(inst->dev->dev, + "Bitstream buffer must be aligned to a multiple of 8\n"); + return -EINVAL; + } + + if (param->bitstream_mode == BS_MODE_INTERRUPT && + (param->bitstream_buffer_size % 1024 || + param->bitstream_buffer_size < MIN_BITSTREAM_BUFFER_SIZE)) { + dev_err(inst->dev->dev, + "Bitstream buffer size must be aligned to a multiple of 1024 and have a minimum size of %d\n", + MIN_BITSTREAM_BUFFER_SIZE); + return -EINVAL; + } + + if (!(BIT(param->bitstream_mode) && p_attr->support_bitstream_mode)) { + dev_err(inst->dev->dev, + "Bitstream mode only configurable with the 'support_bitstream_mode' flag"); + return -EINVAL; + } + + if (!(BIT(param->frame_endian) && p_attr->support_endian_mask)) { + dev_err(inst->dev->dev, + "Frame endianness only configurable with the 'support_endian_mask' flag"); + return -EINVAL; + } + + if (!(BIT(param->stream_endian) && p_attr->support_endian_mask)) { + dev_err(inst->dev->dev, + "Stream endianness only configurable with the 'support_endian_mask' flag"); + return -EINVAL; + } + + return 0; +} + +int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_param) +{ + struct dec_info *p_dec_info; + int ret; + struct vpu_device *vpu_dev = inst->dev; + dma_addr_t buffer_addr; + size_t buffer_size; + + ret = wave5_check_dec_open_param(inst, open_param); + if (ret) + return ret; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + if (!wave5_vpu_is_init(vpu_dev)) { + mutex_unlock(&vpu_dev->hw_lock); + return -ENODEV; + } + + inst->codec_info = kzalloc(sizeof(*inst->codec_info), GFP_KERNEL); + if (!inst->codec_info) { + mutex_unlock(&vpu_dev->hw_lock); + return -ENOMEM; + } + + p_dec_info = &inst->codec_info->dec_info; + memcpy(&p_dec_info->open_param, open_param, sizeof(struct dec_open_param)); + + buffer_addr = open_param->bitstream_buffer; + buffer_size = open_param->bitstream_buffer_size; + p_dec_info->stream_wr_ptr = buffer_addr; + p_dec_info->stream_rd_ptr = buffer_addr; + p_dec_info->stream_buf_start_addr = buffer_addr; + p_dec_info->stream_buf_size = buffer_size; + p_dec_info->stream_buf_end_addr = buffer_addr + buffer_size; + p_dec_info->reorder_enable = TRUE; + p_dec_info->mirror_direction = MIRDIR_NONE; + p_dec_info->temp_id_select_mode = TEMPORAL_ID_MODE_ABSOLUTE; + p_dec_info->target_temp_id = DECODE_ALL_TEMPORAL_LAYERS; + p_dec_info->target_spatial_id = DECODE_ALL_SPATIAL_LAYERS; + + ret = wave5_vpu_build_up_dec_param(inst, open_param); + if (ret) + goto free_codec_info; + + mutex_unlock(&vpu_dev->hw_lock); + + return 0; + +free_codec_info: + kfree(inst->codec_info); + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res) +{ + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + int ret; + struct vpu_device *vpu_dev = inst->dev; + int i; + + *fail_res = 0; + if (!inst->codec_info) + return -EINVAL; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + ret = wave5_vpu_dec_finish_seq(inst, fail_res); + if (ret) { + dev_warn(inst->dev->dev, "dec_finish_seq timed out\n"); + + if (*fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING) { + mutex_unlock(&vpu_dev->hw_lock); + return ret; + } + } + + dev_dbg(inst->dev->dev, "%s: dec_finish_seq complete\n", __func__); + + if (p_dec_info->vb_work.size) + wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); + + for (i = 0 ; i < MAX_REG_FRAME; i++) { + if (p_dec_info->vb_mv[i].size) + wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_mv[i]); + if (p_dec_info->vb_fbc_y_tbl[i].size) + wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_fbc_y_tbl[i]); + if (p_dec_info->vb_fbc_c_tbl[i].size) + wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_fbc_c_tbl[i]); + } + + if (p_dec_info->vb_task.size) + wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_task); + + mutex_unlock(&vpu_dev->hw_lock); + + kfree(inst->codec_info); + + return 0; +} + +int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst) +{ + int ret; + struct vpu_device *vpu_dev = inst->dev; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + ret = wave5_vpu_dec_init_seq(inst); + + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initial_info *info) +{ + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + int ret; + struct vpu_device *vpu_dev = inst->dev; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + ret = wave5_vpu_dec_get_seq_info(inst, info); + if (!ret) + p_dec_info->initial_info_obtained = true; + + info->rd_ptr = wave5_vpu_dec_get_rd_ptr(inst); + info->wr_ptr = p_dec_info->stream_wr_ptr; + + p_dec_info->initial_info = *info; + + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs, + int num_of_display_fbs, int stride, int height, + int map_type) +{ + struct dec_info *p_dec_info; + int ret; + struct vpu_device *vpu_dev = inst->dev; + struct frame_buffer *fb; + + if (num_of_decoding_fbs >= WAVE5_MAX_FBS || num_of_display_fbs >= WAVE5_MAX_FBS) + return -EINVAL; + + p_dec_info = &inst->codec_info->dec_info; + p_dec_info->num_of_decoding_fbs = num_of_decoding_fbs; + p_dec_info->num_of_display_fbs = num_of_display_fbs; + p_dec_info->stride = stride; + + if (!p_dec_info->initial_info_obtained) + return -EINVAL; + + if (stride < p_dec_info->initial_info.pic_width || (stride % 8 != 0) || + height < p_dec_info->initial_info.pic_height) + return -EINVAL; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + fb = inst->frame_buf; + ret = wave5_vpu_dec_register_framebuffer(inst, &fb[p_dec_info->num_of_decoding_fbs], + LINEAR_FRAME_MAP, p_dec_info->num_of_display_fbs); + if (ret) + goto err_out; + + ret = wave5_vpu_dec_register_framebuffer(inst, &fb[0], COMPRESSED_FRAME_MAP, + p_dec_info->num_of_decoding_fbs); + +err_out: + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *prd_ptr, + dma_addr_t *pwr_ptr, size_t *size) +{ + struct dec_info *p_dec_info; + dma_addr_t rd_ptr; + dma_addr_t wr_ptr; + int room; + struct vpu_device *vpu_dev = inst->dev; + int ret; + + p_dec_info = &inst->codec_info->dec_info; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + rd_ptr = wave5_vpu_dec_get_rd_ptr(inst); + mutex_unlock(&vpu_dev->hw_lock); + + wr_ptr = p_dec_info->stream_wr_ptr; + + if (p_dec_info->open_param.bitstream_mode != BS_MODE_PIC_END) { + if (wr_ptr < rd_ptr) + room = rd_ptr - wr_ptr; + else + room = (p_dec_info->stream_buf_end_addr - wr_ptr) + + (rd_ptr - p_dec_info->stream_buf_start_addr); + room--; + } else { + room = (p_dec_info->stream_buf_end_addr - wr_ptr); + } + + if (prd_ptr) + *prd_ptr = rd_ptr; + if (pwr_ptr) + *pwr_ptr = wr_ptr; + if (size) + *size = room; + + return 0; +} + +int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size) +{ + struct dec_info *p_dec_info; + dma_addr_t wr_ptr; + dma_addr_t rd_ptr; + int ret; + struct vpu_device *vpu_dev = inst->dev; + + if (!inst->codec_info) + return -EINVAL; + + p_dec_info = &inst->codec_info->dec_info; + wr_ptr = p_dec_info->stream_wr_ptr; + rd_ptr = p_dec_info->stream_rd_ptr; + + if (size > 0) { + if (wr_ptr < rd_ptr && rd_ptr <= wr_ptr + size) + return -EINVAL; + + wr_ptr += size; + + if (p_dec_info->open_param.bitstream_mode != BS_MODE_PIC_END) { + if (wr_ptr > p_dec_info->stream_buf_end_addr) { + u32 room = wr_ptr - p_dec_info->stream_buf_end_addr; + + wr_ptr = p_dec_info->stream_buf_start_addr; + wr_ptr += room; + } else if (wr_ptr == p_dec_info->stream_buf_end_addr) { + wr_ptr = p_dec_info->stream_buf_start_addr; + } + } + + p_dec_info->stream_wr_ptr = wr_ptr; + p_dec_info->stream_rd_ptr = rd_ptr; + } + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + ret = wave5_vpu_dec_set_bitstream_flag(inst, (size == 0)); + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, struct dec_param *param, u32 *res_fail) +{ + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + int ret; + struct vpu_device *vpu_dev = inst->dev; + + if (p_dec_info->stride == 0) // this means frame buffers have not been registered. + return -EINVAL; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + ret = wave5_vpu_decode(inst, param, res_fail); + + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int update_wr_ptr) +{ + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + int ret; + struct vpu_device *vpu_dev = inst->dev; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + ret = wave5_dec_set_rd_ptr(inst, addr); + + p_dec_info->stream_rd_ptr = addr; + if (update_wr_ptr) + p_dec_info->stream_wr_ptr = addr; + + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info) +{ + struct dec_info *p_dec_info; + int ret; + struct vpu_rect rect_info; + u32 val; + u32 decoded_index; + u32 disp_idx; + u32 max_dec_index; + struct vpu_device *vpu_dev = inst->dev; + struct dec_output_info *disp_info; + + if (!info) + return -EINVAL; + + p_dec_info = &inst->codec_info->dec_info; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + memset(info, 0, sizeof(*info)); + + ret = wave5_vpu_dec_get_result(inst, info); + if (ret) { + info->rd_ptr = p_dec_info->stream_rd_ptr; + info->wr_ptr = p_dec_info->stream_wr_ptr; + goto err_out; + } + + decoded_index = info->index_frame_decoded; + + // calculate display frame region + val = 0; + //default value + rect_info.left = 0; + rect_info.right = 0; + rect_info.top = 0; + rect_info.bottom = 0; + if (decoded_index < WAVE5_MAX_FBS) { + if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) + rect_info = p_dec_info->initial_info.pic_crop_rect; + + if (inst->std == W_HEVC_DEC) + p_dec_info->dec_out_info[decoded_index].decoded_poc = info->decoded_poc; + + if (inst->std == W_AVS2_DEC) + p_dec_info->dec_out_info[decoded_index].avs2_info.decoded_poi = + info->avs2_info.decoded_poi; + + p_dec_info->dec_out_info[decoded_index].rc_decoded = rect_info; + } + info->rc_decoded = rect_info; + + disp_idx = info->index_frame_display; + disp_info = &p_dec_info->dec_out_info[disp_idx]; + if (info->index_frame_display >= 0 && info->index_frame_display < WAVE5_MAX_FBS) { + u32 width = info->dec_pic_width; + u32 height = info->dec_pic_height; + + if (info->index_frame_display != info->index_frame_decoded) { + /* + * when index_frame_decoded < 0, and index_frame_display >= 0 + * info->dec_pic_width and info->dec_pic_height are still valid + * but those of p_dec_info->dec_out_info[disp_idx] are invalid in VP9 + */ + width = disp_info->dec_pic_width; + height = disp_info->dec_pic_height; + } + // TODO no rotation/mirror v4l2 cmd implemented for the decoder + if (p_dec_info->rotation_enable || p_dec_info->mirror_enable) + if (p_dec_info->rotation_angle == 90 || p_dec_info->rotation_angle == 270) + swap(width, height); + + if (p_dec_info->rotation_enable) { + switch (p_dec_info->rotation_angle) { + case 90: + info->rc_display.left = disp_info->rc_decoded.top; + info->rc_display.right = disp_info->rc_decoded.bottom; + info->rc_display.top = disp_info->rc_decoded.right; + info->rc_display.bottom = disp_info->rc_decoded.left; + break; + case 270: + info->rc_display.left = disp_info->rc_decoded.bottom; + info->rc_display.right = disp_info->rc_decoded.top; + info->rc_display.top = disp_info->rc_decoded.left; + info->rc_display.bottom = disp_info->rc_decoded.right; + break; + case 180: + info->rc_display.left = disp_info->rc_decoded.right; + info->rc_display.right = disp_info->rc_decoded.left; + info->rc_display.top = disp_info->rc_decoded.bottom; + info->rc_display.bottom = disp_info->rc_decoded.top; + break; + default: + info->rc_display = disp_info->rc_decoded; + break; + } + } else { + info->rc_display = disp_info->rc_decoded; + } + + if (p_dec_info->mirror_enable) { + if (p_dec_info->mirror_direction & MIRDIR_VER) + swap(info->rc_display.top, info->rc_display.bottom); + if (p_dec_info->mirror_direction & MIRDIR_HOR) + swap(info->rc_display.left, info->rc_display.right); + } + + switch (inst->std) { + case W_AVS2_DEC: + info->avs2_info.display_poi = + disp_info->avs2_info.decoded_poi; + break; + default: + break; + } + + info->disp_pic_width = width; + info->disp_pic_height = height; + } else { + info->rc_display.left = 0; + info->rc_display.right = 0; + info->rc_display.top = 0; + info->rc_display.bottom = 0; + + if (p_dec_info->rotation_enable || p_dec_info->mirror_enable || + p_dec_info->dering_enable) { + info->disp_pic_width = info->dec_pic_width; + info->disp_pic_height = info->dec_pic_height; + } else { + info->disp_pic_width = 0; + info->disp_pic_height = 0; + } + } + + p_dec_info->stream_rd_ptr = wave5_vpu_dec_get_rd_ptr(inst); + p_dec_info->frame_display_flag = vpu_read_reg(vpu_dev, W5_RET_DEC_DISP_IDC); + if (inst->std == W_VP9_DEC) + p_dec_info->frame_display_flag &= 0xFFFF; + + if (p_dec_info->dering_enable || p_dec_info->mirror_enable || p_dec_info->rotation_enable) { + info->disp_frame = p_dec_info->rotator_output; + info->disp_frame.stride = p_dec_info->rotator_stride; + } else { + val = p_dec_info->num_of_decoding_fbs; //fb_offset + + max_dec_index = (p_dec_info->num_of_decoding_fbs > p_dec_info->num_of_display_fbs) ? + p_dec_info->num_of_decoding_fbs : p_dec_info->num_of_display_fbs; + + if (info->index_frame_display >= 0 && + info->index_frame_display < (int)max_dec_index) + info->disp_frame = inst->frame_buf[val + info->index_frame_display]; + } + + info->rd_ptr = p_dec_info->stream_rd_ptr; + info->wr_ptr = p_dec_info->stream_wr_ptr; + info->frame_display_flag = p_dec_info->frame_display_flag; + + info->sequence_no = p_dec_info->initial_info.sequence_no; + if (decoded_index < WAVE5_MAX_FBS) + p_dec_info->dec_out_info[decoded_index] = *info; + + if (disp_idx < WAVE5_MAX_FBS) + info->disp_frame.sequence_no = info->sequence_no; + + if (info->sequence_changed && + !(info->sequence_changed & SEQ_CHANGE_INTER_RES_CHANGE)) { + memcpy((void *)&p_dec_info->initial_info, (void *)&p_dec_info->new_seq_info, + sizeof(struct dec_initial_info)); + p_dec_info->initial_info.sequence_no++; + } + +err_out: + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index) +{ + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + int ret = 0; + struct vpu_device *vpu_dev = inst->dev; + + if (index >= p_dec_info->num_of_display_fbs) + return -EINVAL; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + ret = wave5_dec_clr_disp_flag(inst, index); + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_dec_set_disp_flag(struct vpu_instance *inst, int index) +{ + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + int ret = 0; + struct vpu_device *vpu_dev = inst->dev; + + if (index >= p_dec_info->num_of_display_fbs) + return -EINVAL; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + ret = wave5_dec_set_disp_flag(inst, index); + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter) +{ + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + + switch (cmd) { + case DEC_GET_QUEUE_STATUS: { + struct queue_status_info *queue_info = parameter; + + queue_info->instance_queue_count = p_dec_info->instance_queue_count; + queue_info->report_queue_count = p_dec_info->report_queue_count; + break; + } + case ENABLE_DEC_THUMBNAIL_MODE: + p_dec_info->thumbnail_mode = true; + break; + case DEC_RESET_FRAMEBUF_INFO: { + int i; + + for (i = 0; i < inst->dst_buf_count; i++) { + wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[i]); + wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_mv[i]); + wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_y_tbl[i]); + wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_c_tbl[i]); + } + + wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task); + break; + } + case DEC_GET_SEQ_INFO: { + struct dec_initial_info *seq_info = parameter; + + *seq_info = p_dec_info->initial_info; + break; + } + + default: + return -EINVAL; + } + + return 0; +} + +int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_param) +{ + struct enc_info *p_enc_info; + int ret; + struct vpu_device *vpu_dev = inst->dev; + + ret = wave5_vpu_enc_check_open_param(inst, open_param); + if (ret) + return ret; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + if (!wave5_vpu_is_init(vpu_dev)) { + mutex_unlock(&vpu_dev->hw_lock); + return -ENODEV; + } + + inst->codec_info = kzalloc(sizeof(*inst->codec_info), GFP_KERNEL); + if (!inst->codec_info) { + mutex_unlock(&vpu_dev->hw_lock); + return -ENOMEM; + } + + p_enc_info = &inst->codec_info->enc_info; + p_enc_info->open_param = *open_param; + + ret = wave5_vpu_build_up_enc_param(vpu_dev->dev, inst, open_param); + if (ret) + goto free_codec_info; + mutex_unlock(&vpu_dev->hw_lock); + + return 0; + +free_codec_info: + kfree(inst->codec_info); + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res) +{ + struct enc_info *p_enc_info; + int ret; + struct vpu_device *vpu_dev = inst->dev; + *fail_res = 0; + + if (!inst->codec_info) + return -EINVAL; + p_enc_info = &inst->codec_info->enc_info; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + ret = wave5_vpu_enc_finish_seq(inst, fail_res); + if (ret) { + dev_warn(inst->dev->dev, "enc seq end timed out\n"); + + if (*fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING) { + mutex_unlock(&vpu_dev->hw_lock); + return ret; + } + } + + dev_dbg(inst->dev->dev, "%s: enc seq end timed out\n", __func__); + + if (p_enc_info->vb_work.size) + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_work); + + if (inst->std == W_HEVC_ENC || inst->std == W_AVC_ENC) { + if (p_enc_info->vb_sub_sam_buf.size) + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_sub_sam_buf); + + if (p_enc_info->vb_mv.size) + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_mv); + + if (p_enc_info->vb_fbc_y_tbl.size) + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_fbc_y_tbl); + + if (p_enc_info->vb_fbc_c_tbl.size) + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_fbc_c_tbl); + } + + if (p_enc_info->vb_task.size) + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_task); + + mutex_unlock(&vpu_dev->hw_lock); + + kfree(inst->codec_info); + + return 0; +} + +int wave5_vpu_enc_register_frame_buffer(struct vpu_instance *inst, unsigned int num, + unsigned int stride, int height, + enum tiled_map_type map_type) +{ + struct enc_info *p_enc_info = &inst->codec_info->enc_info; + int ret; + struct vpu_device *vpu_dev = inst->dev; + unsigned int size_luma, size_chroma; + int i; + + if (p_enc_info->stride) + return -EINVAL; + + if (!p_enc_info->initial_info_obtained) + return -EINVAL; + + if (num < p_enc_info->initial_info.min_frame_buffer_count) + return -EINVAL; + + if (stride == 0 || stride % 8 != 0) + return -EINVAL; + + if (height <= 0) + return -EINVAL; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + p_enc_info->num_frame_buffers = num; + p_enc_info->stride = stride; + + size_luma = stride * height; + size_chroma = ALIGN(stride / 2, 16) * height; + + for (i = 0; i < num; i++) { + if (!inst->frame_buf[i].update_fb_info) + continue; + + inst->frame_buf[i].update_fb_info = false; + inst->frame_buf[i].stride = stride; + inst->frame_buf[i].height = height; + inst->frame_buf[i].map_type = COMPRESSED_FRAME_MAP; + inst->frame_buf[i].endian = VDI_128BIT_LITTLE_ENDIAN; + inst->frame_buf[i].buf_y_size = size_luma; + inst->frame_buf[i].buf_cb = inst->frame_buf[i].buf_y + size_luma; + inst->frame_buf[i].buf_cb_size = size_chroma; + inst->frame_buf[i].buf_cr_size = 0; + } + + ret = wave5_vpu_enc_register_framebuffer(inst->dev->dev, inst, &inst->frame_buf[0], + COMPRESSED_FRAME_MAP, + p_enc_info->num_frame_buffers); + + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +static int wave5_check_enc_param(struct vpu_instance *inst, struct enc_param *param) +{ + struct enc_info *p_enc_info = &inst->codec_info->enc_info; + + if (!param) + return -EINVAL; + + if (!param->skip_picture && !param->source_frame) + return -EINVAL; + + if (p_enc_info->open_param.bit_rate == 0 && inst->std == W_HEVC_ENC) { + if (param->force_pic_qp_enable && + (param->force_pic_qp_i > MAX_INTRA_QP || param->force_pic_qp_p > MAX_INTRA_QP || + param->force_pic_qp_b > MAX_INTRA_QP)) + return -EINVAL; + if (!p_enc_info->ring_buffer_enable && + (param->pic_stream_buffer_addr % 16 || param->pic_stream_buffer_size == 0)) + return -EINVAL; + } + if (!p_enc_info->ring_buffer_enable && + (param->pic_stream_buffer_addr % 8 || param->pic_stream_buffer_size == 0)) + return -EINVAL; + + return 0; +} + +static uint64_t wave5_get_timestamp(struct vpu_instance *inst) +{ + struct enc_info *p_enc_info; + u64 pts; + u32 fps; + + if (!inst->codec_info) + return 0; + + p_enc_info = &inst->codec_info->enc_info; + fps = p_enc_info->open_param.frame_rate_info; + if (fps == 0) + fps = 30; + + pts = p_enc_info->cur_pts; + p_enc_info->cur_pts += 90000 / fps; /* 90_k_hz/fps */ + + return pts; +} + +int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *param, u32 *fail_res) +{ + struct enc_info *p_enc_info = &inst->codec_info->enc_info; + int ret; + struct vpu_device *vpu_dev = inst->dev; + + *fail_res = 0; + + if (p_enc_info->stride == 0) // this means frame buffers have not been registered. + return -EINVAL; + + ret = wave5_check_enc_param(inst, param); + if (ret) + return ret; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + p_enc_info->pts_map[param->src_idx] = p_enc_info->open_param.enable_pts ? + wave5_get_timestamp(inst) : param->pts; + + ret = wave5_vpu_encode(inst, param, fail_res); + + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_enc_get_output_info(struct vpu_instance *inst, struct enc_output_info *info) +{ + struct enc_info *p_enc_info = &inst->codec_info->enc_info; + int ret; + struct vpu_device *vpu_dev = inst->dev; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + ret = wave5_vpu_enc_get_result(inst, info); + if (ret) { + info->pts = 0; + goto unlock; + } + + if (info->recon_frame_index >= 0) + info->pts = p_enc_info->pts_map[info->enc_src_idx]; + +unlock: + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_enc_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter) +{ + struct enc_info *p_enc_info = &inst->codec_info->enc_info; + + switch (cmd) { + case ENABLE_ROTATION: + p_enc_info->rotation_enable = true; + break; + case ENABLE_MIRRORING: + p_enc_info->mirror_enable = true; + break; + case SET_MIRROR_DIRECTION: { + enum mirror_direction mir_dir; + + mir_dir = *(enum mirror_direction *)parameter; + if (mir_dir != MIRDIR_NONE && mir_dir != MIRDIR_HOR && + mir_dir != MIRDIR_VER && mir_dir != MIRDIR_HOR_VER) + return -EINVAL; + p_enc_info->mirror_direction = mir_dir; + break; + } + case SET_ROTATION_ANGLE: { + int angle; + + angle = *(int *)parameter; + if (angle && angle != 90 && angle != 180 && angle != 270) + return -EINVAL; + if (p_enc_info->initial_info_obtained && (angle == 90 || angle == 270)) + return -EINVAL; + p_enc_info->rotation_angle = angle; + break; + } + case ENC_GET_QUEUE_STATUS: { + struct queue_status_info *queue_info = parameter; + + queue_info->instance_queue_count = p_enc_info->instance_queue_count; + queue_info->report_queue_count = p_enc_info->report_queue_count; + break; + } + default: + return -EINVAL; + } + return 0; +} + +int wave5_vpu_enc_issue_seq_init(struct vpu_instance *inst) +{ + int ret; + struct vpu_device *vpu_dev = inst->dev; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + ret = wave5_vpu_enc_init_seq(inst); + + mutex_unlock(&vpu_dev->hw_lock); + + return ret; +} + +int wave5_vpu_enc_complete_seq_init(struct vpu_instance *inst, struct enc_initial_info *info) +{ + struct enc_info *p_enc_info = &inst->codec_info->enc_info; + int ret; + struct vpu_device *vpu_dev = inst->dev; + + if (!info) + return -EINVAL; + + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); + if (ret) + return ret; + + ret = wave5_vpu_enc_get_seq_info(inst, info); + if (ret) { + p_enc_info->initial_info_obtained = false; + mutex_unlock(&vpu_dev->hw_lock); + return ret; + } + + p_enc_info->initial_info_obtained = true; + p_enc_info->initial_info = *info; + + mutex_unlock(&vpu_dev->hw_lock); + + return 0; +} diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h new file mode 100644 index 000000000000..1b3ffb737925 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h @@ -0,0 +1,1136 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * Wave5 series multi-standard codec IP - helper definitions + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#ifndef VPUAPI_H_INCLUDED +#define VPUAPI_H_INCLUDED + +#include <linux/kfifo.h> +#include <linux/idr.h> +#include <media/v4l2-device.h> +#include <media/v4l2-mem2mem.h> +#include <media/v4l2-ctrls.h> +#include "wave5-vpuerror.h" +#include "wave5-vpuconfig.h" +#include "wave5-vdi.h" + +enum product_id { + PRODUCT_ID_521, + PRODUCT_ID_511, + PRODUCT_ID_517, + PRODUCT_ID_NONE, +}; + +struct vpu_attr; + +enum vpu_instance_type { + VPU_INST_TYPE_DEC = 0, + VPU_INST_TYPE_ENC = 1 +}; + +enum vpu_instance_state { + VPU_INST_STATE_NONE = 0, + VPU_INST_STATE_OPEN = 1, + VPU_INST_STATE_INIT_SEQ = 2, + VPU_INST_STATE_PIC_RUN = 3, + VPU_INST_STATE_STOP = 4 +}; + +#define WAVE5_MAX_FBS 32 + +#define MAX_REG_FRAME (WAVE5_MAX_FBS * 2) + +#define WAVE5_DEC_HEVC_BUF_SIZE(_w, _h) (DIV_ROUND_UP(_w, 64) * DIV_ROUND_UP(_h, 64) * 256 + 64) +#define WAVE5_DEC_AVC_BUF_SIZE(_w, _h) ((((ALIGN(_w, 256) / 16) * (ALIGN(_h, 16) / 16)) + 16) * 80) +#define WAVE5_DEC_VP9_BUF_SIZE(_w, _h) (((ALIGN(_w, 64) * ALIGN(_h, 64)) >> 2)) +#define WAVE5_DEC_AVS2_BUF_SIZE(_w, _h) (((ALIGN(_w, 64) * ALIGN(_h, 64)) >> 5)) +// AV1 BUF SIZE : MFMV + segment ID + CDF probs table + film grain param Y+ film graim param C +#define WAVE5_DEC_AV1_BUF_SZ_1(_w, _h) \ + (((ALIGN(_w, 64) / 64) * (ALIGN(_h, 64) / 64) * 512) + 41984 + 8192 + 4864) +#define WAVE5_DEC_AV1_BUF_SZ_2(_w1, _w2, _h) \ + (((ALIGN(_w1, 64) / 64) * 256 + (ALIGN(_w2, 256) / 64) * 128) * (ALIGN(_h, 64) / 64)) + +#define WAVE5_FBC_LUMA_TABLE_SIZE(_w, _h) (ALIGN(_h, 64) * ALIGN(_w, 256) / 32) +#define WAVE5_FBC_CHROMA_TABLE_SIZE(_w, _h) (ALIGN((_h), 64) * ALIGN((_w) / 2, 256) / 32) +#define WAVE5_ENC_AVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) * ALIGN(_h, 64) / 32) +#define WAVE5_ENC_HEVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) / 64 * ALIGN(_h, 64) / 64 * 128) + +/* + * common struct and definition + */ +enum cod_std { + STD_AVC = 0, + STD_VC1 = 1, + STD_MPEG2 = 2, + STD_MPEG4 = 3, + STD_H263 = 4, + STD_DIV3 = 5, + STD_RV = 6, + STD_AVS = 7, + STD_THO = 9, + STD_VP3 = 10, + STD_VP8 = 11, + STD_HEVC = 12, + STD_VP9 = 13, + STD_AVS2 = 14, + STD_AV1 = 16, + STD_MAX +}; + +enum wave_std { + W_HEVC_DEC = 0x00, + W_HEVC_ENC = 0x01, + W_AVC_DEC = 0x02, + W_AVC_ENC = 0x03, + W_VP9_DEC = 0x16, + W_AVS2_DEC = 0x18, + W_AV1_DEC = 0x1A, + STD_UNKNOWN = 0xFF +}; + +enum SET_PARAM_OPTION { + OPT_COMMON = 0, /* SET_PARAM command option for encoding sequence */ + OPT_CUSTOM_GOP = 1, /* SET_PARAM command option for setting custom GOP */ + OPT_CUSTOM_HEADER = 2, /* SET_PARAM command option for setting custom VPS/SPS/PPS */ + OPT_VUI = 3, /* SET_PARAM command option for encoding VUI */ + OPT_CHANGE_PARAM = 0x10, +}; + +enum DEC_PIC_HDR_OPTION { + INIT_SEQ_NORMAL = 0x01, + INIT_SEQ_W_THUMBNAIL = 0x11, +}; + +enum DEC_PIC_OPTION { + DEC_PIC_NORMAL = 0x00, /* it is normal mode of DEC_PIC command */ + DEC_PIC_W_THUMBNAIL = 0x10, /* thumbnail mode (skip non-IRAP without reference reg) */ + SKIP_NON_IRAP = 0x11, /* it skips to decode non-IRAP pictures */ + SKIP_NON_REF_PIC = 0x13 +}; + +/************************************************************************/ +/* PROFILE & LEVEL */ +/************************************************************************/ +/* HEVC */ +#define HEVC_PROFILE_MAIN 1 +#define HEVC_PROFILE_MAIN10 2 +#define HEVC_PROFILE_STILLPICTURE 3 +#define HEVC_PROFILE_MAIN10_STILLPICTURE 2 + +/* H.264 profile for encoder*/ +#define H264_PROFILE_BP 1 +#define H264_PROFILE_MP 2 +#define H264_PROFILE_EXTENDED 3 +#define H264_PROFILE_HP 4 +#define H264_PROFILE_HIGH10 5 +#define H264_PROFILE_HIGH422 6 +#define H264_PROFILE_HIGH444 7 + +/************************************************************************/ +/* error codes */ +/************************************************************************/ + +/************************************************************************/ +/* utility macros */ +/************************************************************************/ + +/* bit_alloc_mode */ +#define BIT_ALLOC_MODE_FIXED_RATIO 2 + +/* bit_rate */ +#define MAX_BIT_RATE 700000000 + +/* decoding_refresh_type */ +#define DEC_REFRESH_TYPE_NON_IRAP 0 +#define DEC_REFRESH_TYPE_CRA 1 +#define DEC_REFRESH_TYPE_IDR 2 + +/* depend_slice_mode */ +#define DEPEND_SLICE_MODE_RECOMMENDED 1 +#define DEPEND_SLICE_MODE_BOOST 2 +#define DEPEND_SLICE_MODE_FAST 3 + +/* hvs_max_delta_qp */ +#define MAX_HVS_MAX_DELTA_QP 51 + +/* intra_refresh_mode */ +#define REFRESH_MODE_CTU_ROWS 1 +#define REFRESH_MODE_CTU_COLUMNS 2 +#define REFRESH_MODE_CTU_STEP_SIZE 3 +#define REFRESH_MODE_CTUS 4 + +/* intra_mb_refresh_mode */ +#define REFRESH_MB_MODE_NONE 0 +#define REFRESH_MB_MODE_CTU_ROWS 1 +#define REFRESH_MB_MODE_CTU_COLUMNS 2 +#define REFRESH_MB_MODE_CTU_STEP_SIZE 3 + +/* intra_qp */ +#define MAX_INTRA_QP 63 + +/* nr_inter_weight_* */ +#define MAX_INTER_WEIGHT 31 + +/* nr_intra_weight_* */ +#define MAX_INTRA_WEIGHT 31 + +/* nr_noise_sigma_* */ +#define MAX_NOISE_SIGMA 255 + +/* bitstream_buffer_size */ +#define MIN_BITSTREAM_BUFFER_SIZE 1024 +#define MIN_BITSTREAM_BUFFER_SIZE_WAVE521 (1024 * 64) + +/* vbv_buffer_size */ +#define MIN_VBV_BUFFER_SIZE 10 +#define MAX_VBV_BUFFER_SIZE 3000 + +/* Bitstream buffer option: Explicit End + * When set to 1 the VPU assumes that the bitstream has at least one frame and + * will read until the end of the bitstream buffer. + * When set to 0 the VPU will not read the last few bytes. + * This option can be set anytime but cannot be cleared during processing. + * It can be set to force finish decoding even though there is not enough + * bitstream data for a full frame. + */ +#define BS_EXPLICIT_END_MODE_ON 1 + +#define BUFFER_MARGIN 4096 + +/************************************************************************/ +/* */ +/************************************************************************/ +/** + * \brief parameters of DEC_SET_SEQ_CHANGE_MASK + */ +#define SEQ_CHANGE_ENABLE_PROFILE BIT(5) +#define SEQ_CHANGE_CHROMA_FORMAT_IDC BIT(15) /* AV1 */ +#define SEQ_CHANGE_ENABLE_SIZE BIT(16) +#define SEQ_CHANGE_INTER_RES_CHANGE BIT(17) /* VP9 */ +#define SEQ_CHANGE_ENABLE_BITDEPTH BIT(18) +#define SEQ_CHANGE_ENABLE_DPB_COUNT BIT(19) + +#define SEQ_CHANGE_ENABLE_ALL_VP9 (SEQ_CHANGE_ENABLE_PROFILE | \ + SEQ_CHANGE_ENABLE_SIZE | \ + SEQ_CHANGE_INTER_RES_CHANGE | \ + SEQ_CHANGE_ENABLE_BITDEPTH | \ + SEQ_CHANGE_ENABLE_DPB_COUNT) + +#define SEQ_CHANGE_ENABLE_ALL_HEVC (SEQ_CHANGE_ENABLE_PROFILE | \ + SEQ_CHANGE_ENABLE_SIZE | \ + SEQ_CHANGE_ENABLE_BITDEPTH | \ + SEQ_CHANGE_ENABLE_DPB_COUNT) + +#define SEQ_CHANGE_ENABLE_ALL_AVS2 (SEQ_CHANGE_ENABLE_PROFILE | \ + SEQ_CHANGE_ENABLE_SIZE | \ + SEQ_CHANGE_ENABLE_BITDEPTH | \ + SEQ_CHANGE_ENABLE_DPB_COUNT) + +#define SEQ_CHANGE_ENABLE_ALL_AVC (SEQ_CHANGE_ENABLE_SIZE | \ + SEQ_CHANGE_ENABLE_BITDEPTH | \ + SEQ_CHANGE_ENABLE_DPB_COUNT) + +#define SEQ_CHANGE_ENABLE_ALL_AV1 (SEQ_CHANGE_ENABLE_PROFILE | \ + SEQ_CHANGE_CHROMA_FORMAT_IDC | \ + SEQ_CHANGE_ENABLE_SIZE | \ + SEQ_CHANGE_ENABLE_BITDEPTH | \ + SEQ_CHANGE_ENABLE_DPB_COUNT) + +#define DISPLAY_IDX_FLAG_SEQ_END -1 +#define DISPLAY_IDX_FLAG_NO_FB -3 +#define DECODED_IDX_FLAG_NO_FB -1 +#define DECODED_IDX_FLAG_SKIP -2 + +#define RECON_IDX_FLAG_ENC_END -1 +#define RECON_IDX_FLAG_ENC_DELAY -2 +#define RECON_IDX_FLAG_HEADER_ONLY -3 +#define RECON_IDX_FLAG_CHANGE_PARAM -4 + +enum codec_command { + ENABLE_ROTATION, + ENABLE_MIRRORING, + SET_MIRROR_DIRECTION, + SET_ROTATION_ANGLE, + ENABLE_DEC_THUMBNAIL_MODE, + DEC_GET_QUEUE_STATUS, + ENC_GET_QUEUE_STATUS, + DEC_RESET_FRAMEBUF_INFO, + DEC_GET_SEQ_INFO, +}; + +enum error_conceal_mode { + ERROR_CONCEAL_MODE_OFF = 0, /* conceal off */ + ERROR_CONCEAL_MODE_INTRA_ONLY = 1, /* intra conceal in intra-picture, inter-picture */ + ERROR_CONCEAL_MODE_INTRA_INTER = 2 +}; + +enum error_conceal_unit { + ERROR_CONCEAL_UNIT_PICTURE = 0, /* picture-level error conceal */ + ERROR_CONCEAL_UNIT_SLICE_TILE = 1, /* slice/tile-level error conceal */ + ERROR_CONCEAL_UNIT_BLOCK_ROW = 2, /* block-row-level error conceal */ + ERROR_CONCEAL_UNIT_BLOCK = 3 /* block-level conceal */ +}; + +enum cb_cr_order { + CBCR_ORDER_NORMAL, + CBCR_ORDER_REVERSED +}; + +enum mirror_direction { + MIRDIR_NONE, /* no mirroring */ + MIRDIR_VER, /* vertical mirroring */ + MIRDIR_HOR, /* horizontal mirroring */ + MIRDIR_HOR_VER /* horizontal and vertical mirroring */ +}; + +enum frame_buffer_format { + FORMAT_ERR = -1, + FORMAT_420 = 0, /* 8bit */ + FORMAT_422, /* 8bit */ + FORMAT_224, /* 8bit */ + FORMAT_444, /* 8bit */ + FORMAT_400, /* 8bit */ + + /* little endian perspective */ + /* | addr 0 | addr 1 | */ + FORMAT_420_P10_16BIT_MSB = 5, /* lsb |000000xx|xxxxxxxx | msb */ + FORMAT_420_P10_16BIT_LSB, /* lsb |xxxxxxx |xx000000 | msb */ + FORMAT_420_P10_32BIT_MSB, /* lsb |00xxxxxxxxxxxxxxxxxxxxxxxxxxx| msb */ + FORMAT_420_P10_32BIT_LSB, /* lsb |xxxxxxxxxxxxxxxxxxxxxxxxxxx00| msb */ + + /* 4:2:2 packed format */ + /* little endian perspective */ + /* | addr 0 | addr 1 | */ + FORMAT_422_P10_16BIT_MSB, /* lsb |000000xx |xxxxxxxx | msb */ + FORMAT_422_P10_16BIT_LSB, /* lsb |xxxxxxxx |xx000000 | msb */ + FORMAT_422_P10_32BIT_MSB, /* lsb |00xxxxxxxxxxxxxxxxxxxxxxxxxxx| msb */ + FORMAT_422_P10_32BIT_LSB, /* lsb |xxxxxxxxxxxxxxxxxxxxxxxxxxx00| msb */ + + FORMAT_YUYV, /* 8bit packed format : Y0U0Y1V0 Y2U1Y3V1 ... */ + FORMAT_YUYV_P10_16BIT_MSB, + FORMAT_YUYV_P10_16BIT_LSB, + FORMAT_YUYV_P10_32BIT_MSB, + FORMAT_YUYV_P10_32BIT_LSB, + + FORMAT_YVYU, /* 8bit packed format : Y0V0Y1U0 Y2V1Y3U1 ... */ + FORMAT_YVYU_P10_16BIT_MSB, + FORMAT_YVYU_P10_16BIT_LSB, + FORMAT_YVYU_P10_32BIT_MSB, + FORMAT_YVYU_P10_32BIT_LSB, + + FORMAT_UYVY, /* 8bit packed format : U0Y0V0Y1 U1Y2V1Y3 ... */ + FORMAT_UYVY_P10_16BIT_MSB, + FORMAT_UYVY_P10_16BIT_LSB, + FORMAT_UYVY_P10_32BIT_MSB, + FORMAT_UYVY_P10_32BIT_LSB, + + FORMAT_VYUY, /* 8bit packed format : V0Y0U0Y1 V1Y2U1Y3 ... */ + FORMAT_VYUY_P10_16BIT_MSB, + FORMAT_VYUY_P10_16BIT_LSB, + FORMAT_VYUY_P10_32BIT_MSB, + FORMAT_VYUY_P10_32BIT_LSB, + + FORMAT_MAX, +}; + +enum packed_format_num { + NOT_PACKED = 0, + PACKED_YUYV, + PACKED_YVYU, + PACKED_UYVY, + PACKED_VYUY, +}; + +enum wave5_interrupt_bit { + INT_WAVE5_INIT_VPU = 0, + INT_WAVE5_WAKEUP_VPU = 1, + INT_WAVE5_SLEEP_VPU = 2, + INT_WAVE5_CREATE_INSTANCE = 3, + INT_WAVE5_FLUSH_INSTANCE = 4, + INT_WAVE5_DESTROY_INSTANCE = 5, + INT_WAVE5_INIT_SEQ = 6, + INT_WAVE5_SET_FRAMEBUF = 7, + INT_WAVE5_DEC_PIC = 8, + INT_WAVE5_ENC_PIC = 8, + INT_WAVE5_ENC_SET_PARAM = 9, + INT_WAVE5_DEC_QUERY = 14, + INT_WAVE5_BSBUF_EMPTY = 15, + INT_WAVE5_BSBUF_FULL = 15, +}; + +enum pic_type { + PIC_TYPE_I = 0, /* I picture */ + PIC_TYPE_KEY = 0, /* KEY frame for AV1*/ + PIC_TYPE_P = 1, /* P picture */ + PIC_TYPE_INTER = 1, /* inter frame for AV1*/ + PIC_TYPE_B = 2, /* B picture (except VC1) */ + PIC_TYPE_REPEAT = 2, /* repeat frame (VP9 only) */ + PIC_TYPE_AV1_INTRA = 2, /* intra only frame (AV1 only) */ + PIC_TYPE_VC1_BI = 2, /* VC1 BI picture (VC1 only) */ + PIC_TYPE_VC1_B = 3, /* VC1 B picture (VC1 only) */ + PIC_TYPE_D = 3, + PIC_TYPE_S = 3, + PIC_TYPE_AVS2_F = 3, /* F picture in AVS2 */ + PIC_TYPE_AV1_SWITCH = 3, /* switch frame (AV1 only) */ + PIC_TYPE_VC1_P_SKIP = 4, /* VC1 P skip picture (VC1 only) */ + PIC_TYPE_MP4_P_SKIP_NOT_CODED = 4, /* not coded P picture in MPEG4 packed mode */ + PIC_TYPE_AVS2_S = 4, /* S picture in AVS2 */ + PIC_TYPE_IDR = 5, /* H.264/H.265 IDR picture */ + PIC_TYPE_AVS2_G = 5, /* G picture in AVS2 */ + PIC_TYPE_AVS2_GB = 6, /* GB picture in AVS2 */ + PIC_TYPE_MAX /* no meaning */ +}; + +enum bit_stream_mode { + BS_MODE_INTERRUPT, + BS_MODE_RESERVED, /* reserved for the future */ + BS_MODE_PIC_END, +}; + +enum sw_reset_mode { + SW_RESET_SAFETY, + SW_RESET_FORCE, + SW_RESET_ON_BOOT +}; + +enum tiled_map_type { + LINEAR_FRAME_MAP = 0, /* linear frame map type */ + COMPRESSED_FRAME_MAP = 17, /* compressed frame map type*/ +}; + +enum temporal_id_mode { + TEMPORAL_ID_MODE_ABSOLUTE, + TEMPORAL_ID_MODE_RELATIVE, +}; + +struct vpu_attr { + u32 product_id; /* the product ID */ + char product_name[8]; /* the product name in ascii code */ + u32 product_version; /* the product version number */ + u32 fw_version; /* the F/W version */ + u32 customer_id; /* customer ID number */ + u32 support_decoders; /* bitmask: see <<vpuapi_h_cod_std>> */ + u32 support_encoders; /* bitmask: see <<vpuapi_h_cod_std>> */ + u32 support_endian_mask; /* A variable of supported endian mode in product */ + u32 support_bitstream_mode; + u32 support_backbone: 1; + u32 support_avc10bit_enc: 1; + u32 support_hevc10bit_enc: 1; + u32 support_dual_core: 1; /* this indicates whether a product has two vcores */ + u32 support_vcore_backbone: 1; + u32 support_vcpu_backbone: 1; +}; + +struct frame_buffer { + dma_addr_t buf_y; + dma_addr_t buf_cb; + dma_addr_t buf_cr; + unsigned int buf_y_size; + unsigned int buf_cb_size; + unsigned int buf_cr_size; + unsigned int endian; + enum tiled_map_type map_type; + unsigned int stride; /* A horizontal stride for given frame buffer */ + unsigned int width; /* A width for given frame buffer */ + unsigned int height; /* A height for given frame buffer */ + size_t size; /* A size for given frame buffer */ + unsigned int sequence_no; + bool update_fb_info; +}; + +struct vpu_rect { + unsigned int left; /* horizontal pixel offset from left edge */ + unsigned int top; /* vertical pixel offset from top edge */ + unsigned int right; /* horizontal pixel offset from right edge */ + unsigned int bottom; /* vertical pixel offset from bottom edge */ +}; + +/* + * decode struct and definition + */ + +struct dec_open_param { + dma_addr_t bitstream_buffer; + size_t bitstream_buffer_size; + enum cb_cr_order cbcr_order; + unsigned int frame_endian; + unsigned int stream_endian; + enum bit_stream_mode bitstream_mode; + u32 av1_format; + enum error_conceal_unit error_conceal_unit; + enum error_conceal_mode error_conceal_mode; + u32 pri_ext_addr; + u32 pri_axprot; + u32 pri_axcache; + u32 enable_non_ref_fbc_write: 1; +}; + +struct dec_initial_info { + u32 pic_width; + u32 pic_height; + s32 f_rate_numerator; /* the numerator part of frame rate fraction */ + s32 f_rate_denominator; /* the denominator part of frame rate fraction */ + struct vpu_rect pic_crop_rect; + u32 min_frame_buffer_count; /* between 1 to 16 */ + u32 frame_buf_delay; + + u32 max_temporal_layers; /* it indicates the max number of temporal sub-layers */ + u32 profile; + u32 level; + u32 tier; + bool is_ext_sar; + u32 aspect_rate_info; + u32 bit_rate; + u32 user_data_header; + u32 user_data_size; + bool user_data_buf_full; + u32 chroma_format_idc;/* A chroma format indicator */ + u32 luma_bitdepth; /* A bit-depth of luma sample */ + u32 chroma_bitdepth; /* A bit-depth of chroma sample */ + u32 seq_init_err_reason; + u32 warn_info; + dma_addr_t rd_ptr; /* A read pointer of bitstream buffer */ + dma_addr_t wr_ptr; /* A write pointer of bitstream buffer */ + u32 sequence_no; + u32 output_bit_depth; + u32 vlc_buf_size; /* the size of vlc buffer */ + u32 param_buf_size; /* the size of param buffer */ +}; + +#define WAVE_SKIPMODE_WAVE_NONE 0 +#define WAVE_SKIPMODE_NON_IRAP 1 +#define WAVE_SKIPMODE_NON_REF 2 + +struct dec_param { + u32 skipframe_mode: 2; + u32 cra_as_bla_flag: 1; + u32 disable_film_grain: 1; +}; + +struct avs2_info { + s32 decoded_poi; + int display_poi; +}; + +struct dec_output_info { + /** + * this is a frame buffer index for the picture to be displayed at the moment among + * frame buffers which are registered using vpu_dec_register_frame_buffer(). frame + * data to be displayed are stored into the frame buffer with this index + * when there is no display delay, this index is always + * the same with index_frame_decoded, however, if display delay does exist for display + * reordering in AVC + * or B-frames in VC1), this index might be different with index_frame_decoded. + * by checking this index, HOST application can easily know whether sequence decoding + * has been finished or not. + * + * -3(0xFFFD) or -2(0xFFFE) : it is when a display output cannot be given due to picture + * reordering or skip option + * -1(0xFFFF) : it is when there is no more output for display at the end of sequence + * decoding + */ + s32 index_frame_display; + /** + * this is a frame buffer index of decoded picture among frame buffers which were + * registered using vpu_dec_register_frame_buffer(). the currently decoded frame is stored + * into the frame buffer specified by + * this index. + * + * -2 : it indicates that no decoded output is generated because decoder meets EOS + * (end of sequence) or skip + * -1 : it indicates that decoder fails to decode a picture because there is no available + * frame buffer + */ + s32 index_frame_decoded; + s32 index_frame_decoded_for_tiled; + u32 nal_type; + unsigned int pic_type; + struct vpu_rect rc_display; + unsigned int disp_pic_width; + unsigned int disp_pic_height; + struct vpu_rect rc_decoded; + u32 dec_pic_width; + u32 dec_pic_height; + struct avs2_info avs2_info; + s32 decoded_poc; + int temporal_id; /* A temporal ID of the picture */ + dma_addr_t rd_ptr; /* A stream buffer read pointer for the current decoder instance */ + dma_addr_t wr_ptr; /* A stream buffer write pointer for the current decoder instance */ + struct frame_buffer disp_frame; + u32 frame_display_flag; /* it reports a frame buffer flag to be displayed */ + /** + * this variable reports that sequence has been changed while H.264/AVC stream decoding. + * if it is 1, HOST application can get the new sequence information by calling + * vpu_dec_get_initial_info() or wave5_vpu_dec_issue_seq_init(). + * + * for H.265/HEVC decoder, each bit has a different meaning as follows. + * + * sequence_changed[5] : it indicates that the profile_idc has been changed + * sequence_changed[16] : it indicates that the resolution has been changed + * sequence_changed[19] : it indicates that the required number of frame buffer has + * been changed. + */ + unsigned int frame_cycle; /* reports the number of cycles for processing a frame */ + u32 sequence_no; + + u32 dec_host_cmd_tick; /* tick of DEC_PIC command for the picture */ + u32 dec_decode_end_tick; /* end tick of decoding slices of the picture */ + + u32 sequence_changed; +}; + +struct queue_status_info { + u32 instance_queue_count; + u32 report_queue_count; +}; + +/* + * encode struct and definition + */ + +#define MAX_NUM_TEMPORAL_LAYER 7 +#define MAX_NUM_SPATIAL_LAYER 3 +#define MAX_GOP_NUM 8 + +struct custom_gop_pic_param { + u32 pic_type; /* A picture type of nth picture in the custom GOP */ + u32 poc_offset; /* A POC of nth picture in the custom GOP */ + u32 pic_qp; /* A quantization parameter of nth picture in the custom GOP */ + u32 use_multi_ref_p; /* use multiref pic for P picture. valid only if PIC_TYPE is P */ + u32 ref_poc_l0; /* A POC of reference L0 of nth picture in the custom GOP */ + u32 ref_poc_l1; /* A POC of reference L1 of nth picture in the custom GOP */ + s32 temporal_id; /* A temporal ID of nth picture in the custom GOP */ +}; + +struct custom_gop_param { + u32 custom_gop_size; /* the size of custom GOP (0~8) */ + struct custom_gop_pic_param pic_param[MAX_GOP_NUM]; +}; + +struct wave_custom_map_opt { + u32 roi_avg_qp; /* it sets an average QP of ROI map */ + u32 addr_custom_map; + u32 custom_roi_map_enable: 1; /* it enables ROI map */ + u32 custom_lambda_map_enable: 1; /* it enables custom lambda map */ + u32 custom_mode_map_enable: 1; + u32 custom_coef_drop_enable: 1; +}; + +struct enc_wave_param { + /* + * A profile indicator (HEVC only) + * + * 0 : the firmware determines a profile according to internalbitdepth + * 1 : main profile + * 2 : main10 profile + * 3 : main still picture profile + * in AVC encoder, a profile cannot be set by host application. the firmware decides it + * based on internalbitdepth. it is HIGH profile for bitdepth of 8 and HIGH10 profile for + * bitdepth of 10. + */ + u32 profile; + u32 level; /* A level indicator (level * 10) */ + u32 internal_bit_depth: 4; /* 8/10 */ + u32 gop_preset_idx: 4; /* 0 - 9 */ + u32 decoding_refresh_type: 2; /* 0=non-IRAP, 1=CRA, 2=IDR */ + u32 intra_qp; /* A quantization parameter of intra picture */ + u32 intra_period; /* A period of intra picture in GOP size */ + u32 forced_idr_header_enable: 2; + u32 conf_win_top; /* A top offset of conformance window */ + u32 conf_win_bot; /* A bottom offset of conformance window */ + u32 conf_win_left; /* A left offset of conformance window */ + u32 conf_win_right; /* A right offset of conformance window */ + u32 independ_slice_mode_arg; + u32 depend_slice_mode_arg; + u32 intra_refresh_mode: 3; + /* + * it specifies an intra CTU refresh interval. depending on intra_refresh_mode, + * it can mean one of the following. + * + * the number of consecutive CTU rows for intra_ctu_refresh_mode of 1 + * the number of consecutive CTU columns for intra_ctu_refresh_mode of 2 + * A step size in CTU for intra_ctu_refresh_mode of 3 + * the number of intra ct_us to be encoded in a picture for intra_ctu_refresh_mode of 4 + */ + u32 intra_refresh_arg; + /* + * 0 : custom setting + * 1 : recommended encoder parameters (slow encoding speed, highest picture quality) + * 2 : boost mode (normal encoding speed, moderate picture quality) + * 3 : fast mode (fast encoding speed, low picture quality) + */ + u32 depend_slice_mode : 2; + u32 use_recommend_enc_param: 2; + u32 max_num_merge: 2; + u32 scaling_list_enable: 2; + u32 bit_alloc_mode: 2; /* 0=ref-pic-priority, 1=uniform, 2=fixed_bit_ratio */ + s32 beta_offset_div2: 4; /* it sets beta_offset_div2 for deblocking filter */ + s32 tc_offset_div2: 4; /* it sets tc_offset_div3 for deblocking filter */ + u32 hvs_qp_scale: 4; /* QP scaling factor for CU QP adjust if hvs_qp_scale_enable is 1 */ + u32 hvs_max_delta_qp; /* A maximum delta QP for HVS */ + /* + * A fixed bit ratio (1 ~ 255) for each picture of GOP's bit + * allocation + * + * N = 0 ~ (MAX_GOP_SIZE - 1) + * MAX_GOP_SIZE = 8 + * + * for instance when MAX_GOP_SIZE is 3, fixed_bit_ratio0, fixed_bit_ratio1, and + * fixed_bit_ratio2 can be set as 2, 1, and 1 respectively for + * the fixed bit ratio 2:1:1. this is only valid when bit_alloc_mode is 2. + */ + u8 fixed_bit_ratio[MAX_GOP_NUM]; + struct custom_gop_param gop_param; /* <<vpuapi_h_custom_gop_param>> */ + u32 num_units_in_tick; + u32 time_scale; + u32 num_ticks_poc_diff_one; + s32 chroma_cb_qp_offset; /* the value of chroma(cb) QP offset */ + s32 chroma_cr_qp_offset; /* the value of chroma(cr) QP offset */ + s32 initial_rc_qp; + u32 nr_intra_weight_y; + u32 nr_intra_weight_cb; /* A weight to cb noise level for intra picture (0 ~ 31) */ + u32 nr_intra_weight_cr; /* A weight to cr noise level for intra picture (0 ~ 31) */ + u32 nr_inter_weight_y; + u32 nr_inter_weight_cb; /* A weight to cb noise level for inter picture (0 ~ 31) */ + u32 nr_inter_weight_cr; /* A weight to cr noise level for inter picture (0 ~ 31) */ + u32 nr_noise_sigma_y; /* Y noise standard deviation if nr_noise_est_enable is 0 */ + u32 nr_noise_sigma_cb;/* cb noise standard deviation if nr_noise_est_enable is 0 */ + u32 nr_noise_sigma_cr;/* cr noise standard deviation if nr_noise_est_enable is 0 */ + u32 bg_thr_diff; + u32 bg_thr_mean_diff; + u32 bg_lambda_qp; + u32 bg_delta_qp; + u32 pu04_delta_rate: 8; /* added to the total cost of 4x4 blocks */ + u32 pu08_delta_rate: 8; /* added to the total cost of 8x8 blocks */ + u32 pu16_delta_rate: 8; /* added to the total cost of 16x16 blocks */ + u32 pu32_delta_rate: 8; /* added to the total cost of 32x32 blocks */ + u32 pu04_intra_planar_delta_rate: 8; + u32 pu04_intra_dc_delta_rate: 8; + u32 pu04_intra_angle_delta_rate: 8; + u32 pu08_intra_planar_delta_rate: 8; + u32 pu08_intra_dc_delta_rate: 8; + u32 pu08_intra_angle_delta_rate: 8; + u32 pu16_intra_planar_delta_rate: 8; + u32 pu16_intra_dc_delta_rate: 8; + u32 pu16_intra_angle_delta_rate: 8; + u32 pu32_intra_planar_delta_rate: 8; + u32 pu32_intra_dc_delta_rate: 8; + u32 pu32_intra_angle_delta_rate: 8; + u32 cu08_intra_delta_rate: 8; + u32 cu08_inter_delta_rate: 8; + u32 cu08_merge_delta_rate: 8; + u32 cu16_intra_delta_rate: 8; + u32 cu16_inter_delta_rate: 8; + u32 cu16_merge_delta_rate: 8; + u32 cu32_intra_delta_rate: 8; + u32 cu32_inter_delta_rate: 8; + u32 cu32_merge_delta_rate: 8; + u32 coef_clear_disable: 8; + u32 min_qp_i; /* A minimum QP of I picture for rate control */ + u32 max_qp_i; /* A maximum QP of I picture for rate control */ + u32 min_qp_p; /* A minimum QP of P picture for rate control */ + u32 max_qp_p; /* A maximum QP of P picture for rate control */ + u32 min_qp_b; /* A minimum QP of B picture for rate control */ + u32 max_qp_b; /* A maximum QP of B picture for rate control */ + u32 custom_lambda_addr; /* it specifies the address of custom lambda map */ + u32 user_scaling_list_addr; /* it specifies the address of user scaling list file */ + u32 avc_idr_period;/* A period of IDR picture (0 ~ 1024). 0 - implies an infinite period */ + u32 avc_slice_arg; /* the number of MB for a slice when avc_slice_mode is set with 1 */ + u32 intra_mb_refresh_mode: 2; /* 0=none, 1=row, 2=column, 3=step-size-in-mb */ + /** + * it specifies an intra MB refresh interval. depending on intra_mb_refresh_mode, + * it can mean one of the following. + * + * the number of consecutive MB rows for intra_mb_refresh_mode of 1 + * the number of consecutive MB columns for intra_mb_refresh_mode of 2 + * A step size in MB for intra_mb_refresh_mode of 3 + */ + u32 intra_mb_refresh_arg; + u32 rc_weight_param; + u32 rc_weight_buf; + + /* flags */ + u32 en_still_picture: 1; /* still picture profile */ + u32 tier: 1; /* 0=main, 1=high */ + u32 independ_slice_mode : 1; /* 0=no-multi-slice, 1=slice-in-ctu-number*/ + u32 avc_slice_mode: 1; /* 0=none, 1=slice-in-mb-number */ + u32 entropy_coding_mode: 1; /* 0=CAVLC, 1=CABAC */ + u32 lossless_enable: 1; /* enables lossless coding */ + u32 const_intra_pred_flag: 1; /* enables constrained intra prediction */ + u32 tmvp_enable: 1; /* enables temporal motion vector prediction */ + u32 wpp_enable: 1; + u32 disable_deblk: 1; /* it disables in-loop deblocking filtering */ + u32 lf_cross_slice_boundary_enable: 1; + u32 skip_intra_trans: 1; + u32 sao_enable: 1; /* it enables SAO (sample adaptive offset) */ + u32 intra_nx_n_enable: 1; /* it enables intra nx_n p_us */ + u32 cu_level_rc_enable: 1; /* it enable CU level rate control */ + u32 hvs_qp_enable: 1; /* enable CU QP adjustment for subjective quality enhancement */ + u32 roi_enable: 1; /* it enables ROI map. NOTE: it is valid when rate control is on */ + u32 nr_y_enable: 1; /* it enables noise reduction algorithm to Y component */ + u32 nr_noise_est_enable: 1; + u32 nr_cb_enable: 1; /* it enables noise reduction algorithm to cb component */ + u32 nr_cr_enable: 1; /* it enables noise reduction algorithm to cr component */ + u32 use_long_term: 1; /* it enables long-term reference function */ + u32 monochrome_enable: 1; /* it enables monochrom encoding mode */ + u32 strong_intra_smooth_enable: 1; /* it enables strong intra smoothing */ + u32 weight_pred_enable: 1; /* it enables to use weighted prediction*/ + u32 bg_detect_enable: 1; /* it enables background detection */ + u32 custom_lambda_enable: 1; /* it enables custom lambda table */ + u32 custom_md_enable: 1; /* it enables custom mode decision */ + u32 rdo_skip: 1; /* it skips RDO(rate distortion optimization) */ + u32 lambda_scaling_enable: 1; /* it enables lambda scaling using custom GOP */ + u32 transform8x8_enable: 1; /* it enables 8x8 intra prediction and 8x8 transform */ + u32 mb_level_rc_enable: 1; /* it enables MB-level rate control */ + u32 s2fme_disable: 1; /* it disables s2me_fme (only for AVC encoder) */ +}; + +struct enc_sub_frame_sync_config { + u32 sub_frame_sync_mode; /* 0=wire-based, 1=register-based */ + u32 sub_frame_sync_on; +}; + +struct enc_open_param { + dma_addr_t bitstream_buffer; + unsigned int bitstream_buffer_size; + u32 pic_width; /* the width of a picture to be encoded in unit of sample */ + u32 pic_height; /* the height of a picture to be encoded in unit of sample */ + u32 frame_rate_info;/* desired fps */ + u32 vbv_buffer_size; + u32 bit_rate; /* target bitrate in bps */ + struct enc_wave_param wave_param; + enum cb_cr_order cbcr_order; + unsigned int stream_endian; + unsigned int source_endian; + enum packed_format_num packed_format; /* <<vpuapi_h_packed_format_num>> */ + enum frame_buffer_format src_format; + /* enum frame_buffer_format output_format; not used yet */ + u32 enc_hrd_rbsp_in_vps; /* it encodes the HRD syntax rbsp into VPS */ + u32 hrd_rbsp_data_size; /* the bit size of the HRD rbsp data */ + u32 hrd_rbsp_data_addr; /* the address of the HRD rbsp data */ + u32 encode_vui_rbsp; + u32 vui_rbsp_data_size; /* the bit size of the VUI rbsp data */ + u32 vui_rbsp_data_addr; /* the address of the VUI rbsp data */ + u32 pri_ext_addr; + u32 pri_axprot; + u32 pri_axcache; + bool ring_buffer_enable; + bool line_buf_int_en; + bool enable_pts; /* an enable flag to report PTS(presentation timestamp) */ + u32 rc_enable : 1; /* rate control */ + u32 enable_non_ref_fbc_write: 1; + u32 sub_frame_sync_enable: 1; + u32 sub_frame_sync_mode: 1; +}; + +struct enc_initial_info { + u32 min_frame_buffer_count; /* minimum number of frame buffer */ + u32 min_src_frame_count; /* minimum number of source buffer */ + u32 max_latency_pictures; /* maximum number of picture latency */ + u32 seq_init_err_reason; /* error information */ + u32 warn_info; /* warn information */ + u32 vlc_buf_size; /* the size of task buffer */ + u32 param_buf_size; /* the size of task buffer */ +}; + +struct enc_code_opt { + u32 implicit_header_encode: 1; + u32 encode_vcl: 1; /* A flag to encode VCL nal unit explicitly */ + u32 encode_vps: 1; /* A flag to encode VPS nal unit explicitly */ + u32 encode_sps: 1; /* A flag to encode SPS nal unit explicitly */ + u32 encode_pps: 1; /* A flag to encode PPS nal unit explicitly */ + u32 encode_aud: 1; /* A flag to encode AUD nal unit explicitly */ + u32 encode_eos: 1; + u32 encode_eob: 1; + u32 encode_vui: 1; /* A flag to encode VUI nal unit explicitly */ +}; + +struct enc_param { + struct frame_buffer *source_frame; + u32 pic_stream_buffer_addr; + u64 pic_stream_buffer_size; + u32 force_pic_qp_i; + u32 force_pic_qp_p; + u32 force_pic_qp_b; + u32 force_pic_type: 2; + u32 src_idx; /* A source frame buffer index */ + struct enc_code_opt code_option; + u32 use_cur_src_as_longterm_pic; + u32 use_longterm_ref; + u64 pts; /* the presentation timestamp (PTS) of input source */ + struct wave_custom_map_opt custom_map_opt; + u32 wp_pix_sigma_y; /* pixel variance of Y component for weighted prediction */ + u32 wp_pix_sigma_cb; /* pixel variance of cb component for weighted prediction */ + u32 wp_pix_sigma_cr; /* pixel variance of cr component for weighted prediction */ + u32 wp_pix_mean_y; /* pixel mean value of Y component for weighted prediction */ + u32 wp_pix_mean_cb; /* pixel mean value of cb component for weighted prediction */ + u32 wp_pix_mean_cr; /* pixel mean value of cr component for weighted prediction */ + bool src_end_flag; + u32 skip_picture: 1; + u32 force_pic_qp_enable: 1; /* flag used to force picture quantization parameter */ + u32 force_pic_type_enable: 1; /* A flag to use a force picture type */ + u32 force_all_ctu_coef_drop_enable: 1; /* forces all coefficients to be zero after TQ */ +}; + +struct enc_output_info { + u32 bitstream_buffer; + u32 bitstream_size; /* the byte size of encoded bitstream */ + u32 pic_type: 2; /* <<vpuapi_h_pic_type>> */ + s32 recon_frame_index; + dma_addr_t rd_ptr; + dma_addr_t wr_ptr; + u32 enc_pic_byte; /* the number of encoded picture bytes */ + s32 enc_src_idx; /* the source buffer index of the currently encoded picture */ + u32 enc_vcl_nut; + u32 error_reason; /* the error reason of the currently encoded picture */ + u32 warn_info; /* the warning information of the currently encoded picture */ + unsigned int frame_cycle; /* param for reporting the cycle number of encoding one frame*/ + u64 pts; + u32 enc_host_cmd_tick; /* tick of ENC_PIC command for the picture */ + u32 enc_encode_end_tick; /* end tick of encoding slices of the picture */ +}; + +enum ENC_PIC_CODE_OPTION { + CODEOPT_ENC_HEADER_IMPLICIT = BIT(0), + CODEOPT_ENC_VCL = BIT(1), /* A flag to encode VCL nal unit explicitly */ +}; + +enum GOP_PRESET_IDX { + PRESET_IDX_CUSTOM_GOP = 0, /* user defined GOP structure */ + PRESET_IDX_ALL_I = 1, /* all intra, gopsize = 1 */ + PRESET_IDX_IPP = 2, /* consecutive P, cyclic gopsize = 1 */ + PRESET_IDX_IBBB = 3, /* consecutive B, cyclic gopsize = 1 */ + PRESET_IDX_IBPBP = 4, /* gopsize = 2 */ + PRESET_IDX_IBBBP = 5, /* gopsize = 4 */ + PRESET_IDX_IPPPP = 6, /* consecutive P, cyclic gopsize = 4 */ + PRESET_IDX_IBBBB = 7, /* consecutive B, cyclic gopsize = 4 */ + PRESET_IDX_RA_IB = 8, /* random access, cyclic gopsize = 8 */ + PRESET_IDX_IPP_SINGLE = 9, /* consecutive P, cyclic gopsize = 1, with single ref */ +}; + +struct sec_axi_info { + struct { + u32 use_ip_enable; + u32 use_bit_enable; + u32 use_lf_row_enable: 1; + u32 use_enc_rdo_enable: 1; + u32 use_enc_lf_enable: 1; + } wave; + unsigned int buf_size; + dma_addr_t buf_base; +}; + +struct dec_info { + struct dec_open_param open_param; + struct dec_initial_info initial_info; + struct dec_initial_info new_seq_info; /* temporal new sequence information */ + u32 stream_wr_ptr; + u32 stream_rd_ptr; + u32 frame_display_flag; + dma_addr_t stream_buf_start_addr; + dma_addr_t stream_buf_end_addr; + u32 stream_buf_size; + struct vpu_buf vb_mv[MAX_REG_FRAME]; + struct vpu_buf vb_fbc_y_tbl[MAX_REG_FRAME]; + struct vpu_buf vb_fbc_c_tbl[MAX_REG_FRAME]; + unsigned int num_of_decoding_fbs; + unsigned int num_of_display_fbs; + unsigned int stride; + enum mirror_direction mirror_direction; + unsigned int rotation_angle; + struct frame_buffer rotator_output; + unsigned int rotator_stride; + struct sec_axi_info sec_axi_info; + dma_addr_t user_data_buf_addr; + u32 user_data_enable; + u32 user_data_buf_size; + struct vpu_buf vb_work; + struct vpu_buf vb_task; + struct dec_output_info dec_out_info[WAVE5_MAX_FBS]; + u32 seq_change_mask; + enum temporal_id_mode temp_id_select_mode; + u32 target_temp_id; + u32 target_spatial_id; + u32 instance_queue_count; + u32 report_queue_count; + u32 cycle_per_tick; + u32 product_code; + u32 vlc_buf_size; + u32 param_buf_size; + bool rotation_enable; + bool mirror_enable; + bool dering_enable; + bool initial_info_obtained; + bool reorder_enable; + bool thumbnail_mode; + bool first_cycle_check; + u32 stream_endflag: 1; +}; + +struct enc_info { + struct enc_open_param open_param; + struct enc_initial_info initial_info; + u32 stream_rd_ptr; + u32 stream_wr_ptr; + dma_addr_t stream_buf_start_addr; + dma_addr_t stream_buf_end_addr; + u32 stream_buf_size; + unsigned int num_frame_buffers; + unsigned int stride; + bool rotation_enable; + bool mirror_enable; + enum mirror_direction mirror_direction; + unsigned int rotation_angle; + bool initial_info_obtained; + bool ring_buffer_enable; + struct sec_axi_info sec_axi_info; + struct enc_sub_frame_sync_config sub_frame_sync_config; + bool line_buf_int_en; + struct vpu_buf vb_work; + struct vpu_buf vb_mv; /* col_mv buffer */ + struct vpu_buf vb_fbc_y_tbl; /* FBC luma table buffer */ + struct vpu_buf vb_fbc_c_tbl; /* FBC chroma table buffer */ + struct vpu_buf vb_sub_sam_buf; /* sub-sampled buffer for ME */ + struct vpu_buf vb_task; + u64 cur_pts; /* current timestamp in 90_k_hz */ + u64 pts_map[32]; /* PTS mapped with source frame index */ + u32 instance_queue_count; + u32 report_queue_count; + bool first_cycle_check; + u32 cycle_per_tick; + u32 product_code; + u32 vlc_buf_size; + u32 param_buf_size; +}; + +struct vpu_device { + struct device *dev; + struct v4l2_device v4l2_dev; + struct list_head instances; + struct video_device *video_dev_dec; + struct video_device *video_dev_enc; + struct mutex dev_lock; /* the lock for the src,dst v4l2 queues */ + struct mutex hw_lock; /* lock hw configurations */ + int irq; + enum product_id product; + struct vpu_attr attr; + struct vpu_buf common_mem; + u32 last_performance_cycles; + struct dma_vpu_buf sram_buf; + void __iomem *vdb_register; + u32 product_code; + struct ida inst_ida; + struct clk_bulk_data *clks; + int num_clks; +}; + +struct vpu_instance; + +struct vpu_instance_ops { + void (*start_process)(struct vpu_instance *inst); + void (*stop_process)(struct vpu_instance *inst); + void (*finish_process)(struct vpu_instance *inst); +}; + +struct vpu_instance { + struct list_head list; + struct v4l2_fh v4l2_fh; + struct v4l2_ctrl_handler v4l2_ctrl_hdl; + struct vpu_device *dev; + struct v4l2_m2m_dev *v4l2_m2m_dev; + struct kfifo irq_status; + struct completion irq_done; + + struct v4l2_pix_format_mplane src_fmt; + struct v4l2_pix_format_mplane dst_fmt; + enum v4l2_colorspace colorspace; + enum v4l2_xfer_func xfer_func; + enum v4l2_ycbcr_encoding ycbcr_enc; + enum v4l2_quantization quantization; + enum v4l2_hsv_encoding hsv_enc; + + enum vpu_instance_state state; + enum vpu_instance_type type; + const struct vpu_instance_ops *ops; + + enum wave_std std; + s32 id; + union { + struct enc_info enc_info; + struct dec_info dec_info; + } *codec_info; + struct frame_buffer frame_buf[MAX_REG_FRAME]; + struct vpu_buf frame_vbuf[MAX_REG_FRAME]; + u32 min_dst_buf_count; + u32 dst_buf_count; + u32 queued_src_buf_num; + u32 queued_dst_buf_num; + u32 conf_win_width; + u32 conf_win_height; + u64 timestamp; + bool cbcr_interleave; + bool nv21; + bool eos; + + struct vpu_buf bitstream_vbuf; + bool thumbnail_mode; + + unsigned int min_src_buf_count; + unsigned int src_buf_count; + unsigned int rot_angle; + unsigned int mirror_direction; + unsigned int bit_depth; + unsigned int frame_rate; + unsigned int vbv_buf_size; + unsigned int rc_mode; + unsigned int rc_enable; + unsigned int bit_rate; + struct enc_wave_param enc_param; +}; + +void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data); +u32 wave5_vdi_readl(struct vpu_device *vpu_dev, u32 addr); +int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); +int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); +int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset, + u8 *data, size_t len, unsigned int endian); +unsigned int wave5_vdi_convert_endian(struct vpu_device *vpu_dev, unsigned int endian); +void wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); + +int wave5_vpu_init_with_bitcode(struct device *dev, u8 *bitcode, size_t size); +void wave5_vpu_clear_interrupt_ex(struct vpu_instance *inst, u32 intr_flag); +int wave5_vpu_get_version_info(struct device *dev, u32 *revision, unsigned int *product_id); +int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_param); +int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res); +int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst); +int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initial_info *info); +int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs, + int num_of_display_fbs, int stride, int height, + int map_type); +int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, struct dec_param *param, + u32 *res_fail); +int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info); +int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int update_wr_ptr); +int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter); +int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *prd_ptr, + dma_addr_t *pwr_ptr, size_t *size); +int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size); +int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index); +int wave5_vpu_dec_set_disp_flag(struct vpu_instance *inst, int index); + +int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_param); +int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res); +int wave5_vpu_enc_issue_seq_init(struct vpu_instance *inst); +int wave5_vpu_enc_complete_seq_init(struct vpu_instance *inst, struct enc_initial_info *info); +int wave5_vpu_enc_register_frame_buffer(struct vpu_instance *inst, unsigned int num, + unsigned int stride, int height, + enum tiled_map_type map_type); +int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *param, + u32 *fail_res); +int wave5_vpu_enc_get_output_info(struct vpu_instance *inst, struct enc_output_info *info); +int wave5_vpu_enc_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter); + +#endif diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h new file mode 100644 index 000000000000..4527eaf88848 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * Wave5 series multi-standard codec IP - product config definitions + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#ifndef _VPU_CONFIG_H_ +#define _VPU_CONFIG_H_ + +#define WAVE517_CODE 0x5170 +#define WAVE537_CODE 0x5370 +#define WAVE511_CODE 0x5110 +#define WAVE521_CODE 0x5210 +#define WAVE521C_CODE 0x521c +#define WAVE521C_DUAL_CODE 0x521d // wave521 dual core +#define WAVE521E1_CODE 0x5211 + +#define PRODUCT_CODE_W_SERIES(x) ({ \ + int c = x; \ + ((c) == WAVE517_CODE || (c) == WAVE537_CODE || \ + (c) == WAVE511_CODE || (c) == WAVE521_CODE || \ + (c) == WAVE521E1_CODE || (c) == WAVE521C_CODE || \ + (c) == WAVE521C_DUAL_CODE); \ +}) + +#define WAVE517_WORKBUF_SIZE (2 * 1024 * 1024) +#define WAVE521ENC_WORKBUF_SIZE (128 * 1024) //HEVC 128K, AVC 40K +#define WAVE521DEC_WORKBUF_SIZE (1784 * 1024) + +#define MAX_NUM_INSTANCE 32 + +#define W5_MIN_ENC_PIC_WIDTH 256 +#define W5_MIN_ENC_PIC_HEIGHT 128 +#define W5_MAX_ENC_PIC_WIDTH 8192 +#define W5_MAX_ENC_PIC_HEIGHT 8192 + +// application specific configuration +#define VPU_ENC_TIMEOUT 60000 +#define VPU_DEC_TIMEOUT 60000 + +#define HOST_ENDIAN VDI_128BIT_LITTLE_ENDIAN +#define VPU_FRAME_ENDIAN HOST_ENDIAN +#define VPU_STREAM_ENDIAN HOST_ENDIAN +#define VPU_USER_DATA_ENDIAN HOST_ENDIAN +#define VPU_SOURCE_ENDIAN HOST_ENDIAN + +// for WAVE encoder +#define USE_SRC_PRP_AXI 0 +#define USE_SRC_PRI_AXI 1 +#define DEFAULT_SRC_AXI USE_SRC_PRP_AXI + +/************************************************************************/ +/* VPU COMMON MEMORY */ +/************************************************************************/ +#define VLC_BUF_NUM (3) + +#define COMMAND_QUEUE_DEPTH (4) + +#define W5_REMAP_INDEX0 0 +#define W5_REMAP_INDEX1 1 +#define W5_REMAP_MAX_SIZE (1024 * 1024) + +#define WAVE5_MAX_CODE_BUF_SIZE (2 * 1024 * 1024) +#define WAVE5_TEMPBUF_OFFSET WAVE5_MAX_CODE_BUF_SIZE +#define WAVE5_TEMPBUF_SIZE (1024 * 1024) + +#define SIZE_COMMON (WAVE5_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE) + +//=====4. VPU REPORT MEMORY ======================// + +#define WAVE5_UPPER_PROC_AXI_ID 0x0 + +#define WAVE5_PROC_AXI_ID 0x0 +#define WAVE5_PRP_AXI_ID 0x0 +#define WAVE5_FBD_Y_AXI_ID 0x0 +#define WAVE5_FBC_Y_AXI_ID 0x0 +#define WAVE5_FBD_C_AXI_ID 0x0 +#define WAVE5_FBC_C_AXI_ID 0x0 +#define WAVE5_SEC_AXI_ID 0x0 +#define WAVE5_PRI_AXI_ID 0x0 + +#define WAVE5_PROC_AXI_AXPROT 0x0 +#define WAVE5_PROC_AXI_AXCACHE 0x0 +#define WAVE5_PROC_AXI_EXT_ADDR 0x0 +#define WAVE5_SEC_AXI_AXPROT 0x0 +#define WAVE5_SEC_AXI_AXCACHE 0x0 +#define WAVE5_SEC_AXI_EXT_ADDR 0x0 + +#endif /* _VPU_CONFIG_H_ */ diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuerror.h b/drivers/media/platform/chips-media/wave5/wave5-vpuerror.h new file mode 100644 index 000000000000..6d8c7bb0e8b2 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuerror.h @@ -0,0 +1,454 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * Wave5 series multi-standard codec IP - error values + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#ifndef ERROR_CODE_H_INCLUDED +#define ERROR_CODE_H_INCLUDED + +/* + * WAVE5 + */ + +/************************************************************************/ +/* WAVE5 COMMON SYSTEM ERROR (FAIL_REASON) */ +/************************************************************************/ +#define WAVE5_SYSERR_QUEUEING_FAIL 0x00000001 +#define WAVE5_SYSERR_ACCESS_VIOLATION_HW 0x00000040 +#define WAVE5_SYSERR_BUS_ERROR 0x00000200 +#define WAVE5_SYSERR_DOUBLE_FAULT 0x00000400 +#define WAVE5_SYSERR_RESULT_NOT_READY 0x00000800 +#define WAVE5_SYSERR_VPU_STILL_RUNNING 0x00001000 +#define WAVE5_SYSERR_UNKNOWN_CMD 0x00002000 +#define WAVE5_SYSERR_UNKNOWN_CODEC_STD 0x00004000 +#define WAVE5_SYSERR_UNKNOWN_QUERY_OPTION 0x00008000 +#define WAVE5_SYSERR_VLC_BUF_FULL 0x00010000 +#define WAVE5_SYSERR_WATCHDOG_TIMEOUT 0x00020000 +#define WAVE5_SYSERR_VCPU_TIMEOUT 0x00080000 +#define WAVE5_SYSERR_TEMP_SEC_BUF_OVERFLOW 0x00200000 +#define WAVE5_SYSERR_NEED_MORE_TASK_BUF 0x00400000 +#define WAVE5_SYSERR_PRESCAN_ERR 0x00800000 +#define WAVE5_SYSERR_ENC_GBIN_OVERCONSUME 0x01000000 +#define WAVE5_SYSERR_ENC_MAX_ZERO_DETECT 0x02000000 +#define WAVE5_SYSERR_ENC_LVL_FIRST_ERROR 0x04000000 +#define WAVE5_SYSERR_ENC_EG_RANGE_OVER 0x08000000 +#define WAVE5_SYSERR_ENC_IRB_FRAME_DROP 0x10000000 +#define WAVE5_SYSERR_INPLACE_V 0x20000000 +#define WAVE5_SYSERR_FATAL_VPU_HANGUP 0xf0000000 + +/************************************************************************/ +/* WAVE5 COMMAND QUEUE ERROR (FAIL_REASON) */ +/************************************************************************/ +#define WAVE5_CMDQ_ERR_NOT_QUEABLE_CMD 0x00000001 +#define WAVE5_CMDQ_ERR_SKIP_MODE_ENABLE 0x00000002 +#define WAVE5_CMDQ_ERR_INST_FLUSHING 0x00000003 +#define WAVE5_CMDQ_ERR_INST_INACTIVE 0x00000004 +#define WAVE5_CMDQ_ERR_QUEUE_FAIL 0x00000005 +#define WAVE5_CMDQ_ERR_CMD_BUF_FULL 0x00000006 + +/************************************************************************/ +/* WAVE5 ERROR ON DECODER (ERR_INFO) */ +/************************************************************************/ +// HEVC +#define HEVC_SPSERR_SEQ_PARAMETER_SET_ID 0x00001000 +#define HEVC_SPSERR_CHROMA_FORMAT_IDC 0x00001001 +#define HEVC_SPSERR_PIC_WIDTH_IN_LUMA_SAMPLES 0x00001002 +#define HEVC_SPSERR_PIC_HEIGHT_IN_LUMA_SAMPLES 0x00001003 +#define HEVC_SPSERR_CONF_WIN_LEFT_OFFSET 0x00001004 +#define HEVC_SPSERR_CONF_WIN_RIGHT_OFFSET 0x00001005 +#define HEVC_SPSERR_CONF_WIN_TOP_OFFSET 0x00001006 +#define HEVC_SPSERR_CONF_WIN_BOTTOM_OFFSET 0x00001007 +#define HEVC_SPSERR_BIT_DEPTH_LUMA_MINUS8 0x00001008 +#define HEVC_SPSERR_BIT_DEPTH_CHROMA_MINUS8 0x00001009 +#define HEVC_SPSERR_LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4 0x0000100A +#define HEVC_SPSERR_SPS_MAX_DEC_PIC_BUFFERING 0x0000100B +#define HEVC_SPSERR_SPS_MAX_NUM_REORDER_PICS 0x0000100C +#define HEVC_SPSERR_SPS_MAX_LATENCY_INCREASE 0x0000100D +#define HEVC_SPSERR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3 0x0000100E +#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE 0x0000100F +#define HEVC_SPSERR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2 0x00001010 +#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE 0x00001011 +#define HEVC_SPSERR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER 0x00001012 +#define HEVC_SPSERR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA 0x00001013 +#define HEVC_SPSERR_SCALING_LIST 0x00001014 +#define HEVC_SPSERR_LOG2_DIFF_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3 0x00001015 +#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE 0x00001016 +#define HEVC_SPSERR_NUM_SHORT_TERM_REF_PIC_SETS 0x00001017 +#define HEVC_SPSERR_NUM_LONG_TERM_REF_PICS_SPS 0x00001018 +#define HEVC_SPSERR_GBU_PARSING_ERROR 0x00001019 +#define HEVC_SPSERR_EXTENSION_FLAG 0x0000101A +#define HEVC_SPSERR_VUI_ERROR 0x0000101B +#define HEVC_SPSERR_ACTIVATE_SPS 0x0000101C +#define HEVC_SPSERR_PROFILE_SPACE 0x0000101D +#define HEVC_PPSERR_PPS_PIC_PARAMETER_SET_ID 0x00002000 +#define HEVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID 0x00002001 +#define HEVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1 0x00002002 +#define HEVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1 0x00002003 +#define HEVC_PPSERR_INIT_QP_MINUS26 0x00002004 +#define HEVC_PPSERR_DIFF_CU_QP_DELTA_DEPTH 0x00002005 +#define HEVC_PPSERR_PPS_CB_QP_OFFSET 0x00002006 +#define HEVC_PPSERR_PPS_CR_QP_OFFSET 0x00002007 +#define HEVC_PPSERR_NUM_TILE_COLUMNS_MINUS1 0x00002008 +#define HEVC_PPSERR_NUM_TILE_ROWS_MINUS1 0x00002009 +#define HEVC_PPSERR_COLUMN_WIDTH_MINUS1 0x0000200A +#define HEVC_PPSERR_ROW_HEIGHT_MINUS1 0x0000200B +#define HEVC_PPSERR_PPS_BETA_OFFSET_DIV2 0x0000200C +#define HEVC_PPSERR_PPS_TC_OFFSET_DIV2 0x0000200D +#define HEVC_PPSERR_SCALING_LIST 0x0000200E +#define HEVC_PPSERR_LOG2_PARALLEL_MERGE_LEVEL_MINUS2 0x0000200F +#define HEVC_PPSERR_NUM_TILE_COLUMNS_RANGE_OUT 0x00002010 +#define HEVC_PPSERR_NUM_TILE_ROWS_RANGE_OUT 0x00002011 +#define HEVC_PPSERR_MORE_RBSP_DATA_ERROR 0x00002012 +#define HEVC_PPSERR_PPS_PIC_PARAMETER_SET_ID_RANGE_OUT 0x00002013 +#define HEVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID_RANGE_OUT 0x00002014 +#define HEVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1_RANGE_OUT 0x00002015 +#define HEVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1_RANGE_OUT 0x00002016 +#define HEVC_PPSERR_PPS_CB_QP_OFFSET_RANGE_OUT 0x00002017 +#define HEVC_PPSERR_PPS_CR_QP_OFFSET_RANGE_OUT 0x00002018 +#define HEVC_PPSERR_COLUMN_WIDTH_MINUS1_RANGE_OUT 0x00002019 +#define HEVC_PPSERR_ROW_HEIGHT_MINUS1_RANGE_OUT 0x00002020 +#define HEVC_PPSERR_PPS_BETA_OFFSET_DIV2_RANGE_OUT 0x00002021 +#define HEVC_PPSERR_PPS_TC_OFFSET_DIV2_RANGE_OUT 0x00002022 +#define HEVC_SHERR_SLICE_PIC_PARAMETER_SET_ID 0x00003000 +#define HEVC_SHERR_ACTIVATE_PPS 0x00003001 +#define HEVC_SHERR_ACTIVATE_SPS 0x00003002 +#define HEVC_SHERR_SLICE_TYPE 0x00003003 +#define HEVC_SHERR_FIRST_SLICE_IS_DEPENDENT_SLICE 0x00003004 +#define HEVC_SHERR_SHORT_TERM_REF_PIC_SET_SPS_FLAG 0x00003005 +#define HEVC_SHERR_SHORT_TERM_REF_PIC_SET 0x00003006 +#define HEVC_SHERR_SHORT_TERM_REF_PIC_SET_IDX 0x00003007 +#define HEVC_SHERR_NUM_LONG_TERM_SPS 0x00003008 +#define HEVC_SHERR_NUM_LONG_TERM_PICS 0x00003009 +#define HEVC_SHERR_LT_IDX_SPS_IS_OUT_OF_RANGE 0x0000300A +#define HEVC_SHERR_DELTA_POC_MSB_CYCLE_LT 0x0000300B +#define HEVC_SHERR_NUM_REF_IDX_L0_ACTIVE_MINUS1 0x0000300C +#define HEVC_SHERR_NUM_REF_IDX_L1_ACTIVE_MINUS1 0x0000300D +#define HEVC_SHERR_COLLOCATED_REF_IDX 0x0000300E +#define HEVC_SHERR_PRED_WEIGHT_TABLE 0x0000300F +#define HEVC_SHERR_FIVE_MINUS_MAX_NUM_MERGE_CAND 0x00003010 +#define HEVC_SHERR_SLICE_QP_DELTA 0x00003011 +#define HEVC_SHERR_SLICE_QP_DELTA_IS_OUT_OF_RANGE 0x00003012 +#define HEVC_SHERR_SLICE_CB_QP_OFFSET 0x00003013 +#define HEVC_SHERR_SLICE_CR_QP_OFFSET 0x00003014 +#define HEVC_SHERR_SLICE_BETA_OFFSET_DIV2 0x00003015 +#define HEVC_SHERR_SLICE_TC_OFFSET_DIV2 0x00003016 +#define HEVC_SHERR_NUM_ENTRY_POINT_OFFSETS 0x00003017 +#define HEVC_SHERR_OFFSET_LEN_MINUS1 0x00003018 +#define HEVC_SHERR_SLICE_SEGMENT_HEADER_EXTENSION_LENGTH 0x00003019 +#define HEVC_SHERR_WRONG_POC_IN_STILL_PICTURE_PROFILE 0x0000301A +#define HEVC_SHERR_SLICE_TYPE_ERROR_IN_STILL_PICTURE_PROFILE 0x0000301B +#define HEVC_SHERR_PPS_ID_NOT_EQUAL_PREV_VALUE 0x0000301C +#define HEVC_SPECERR_OVER_PICTURE_WIDTH_SIZE 0x00004000 +#define HEVC_SPECERR_OVER_PICTURE_HEIGHT_SIZE 0x00004001 +#define HEVC_SPECERR_OVER_CHROMA_FORMAT 0x00004002 +#define HEVC_SPECERR_OVER_BIT_DEPTH 0x00004003 +#define HEVC_SPECERR_OVER_BUFFER_OVER_FLOW 0x00004004 +#define HEVC_SPECERR_OVER_WRONG_BUFFER_ACCESS 0x00004005 +#define HEVC_ETCERR_INIT_SEQ_SPS_NOT_FOUND 0x00005000 +#define HEVC_ETCERR_DEC_PIC_VCL_NOT_FOUND 0x00005001 +#define HEVC_ETCERR_NO_VALID_SLICE_IN_AU 0x00005002 +#define HEVC_ETCERR_INPLACE_V 0x0000500F + +// AVC +#define AVC_SPSERR_SEQ_PARAMETER_SET_ID 0x00001000 +#define AVC_SPSERR_CHROMA_FORMAT_IDC 0x00001001 +#define AVC_SPSERR_PIC_WIDTH_IN_LUMA_SAMPLES 0x00001002 +#define AVC_SPSERR_PIC_HEIGHT_IN_LUMA_SAMPLES 0x00001003 +#define AVC_SPSERR_CONF_WIN_LEFT_OFFSET 0x00001004 +#define AVC_SPSERR_CONF_WIN_RIGHT_OFFSET 0x00001005 +#define AVC_SPSERR_CONF_WIN_TOP_OFFSET 0x00001006 +#define AVC_SPSERR_CONF_WIN_BOTTOM_OFFSET 0x00001007 +#define AVC_SPSERR_BIT_DEPTH_LUMA_MINUS8 0x00001008 +#define AVC_SPSERR_BIT_DEPTH_CHROMA_MINUS8 0x00001009 +#define AVC_SPSERR_SPS_MAX_DEC_PIC_BUFFERING 0x0000100B +#define AVC_SPSERR_SPS_MAX_NUM_REORDER_PICS 0x0000100C +#define AVC_SPSERR_SCALING_LIST 0x00001014 +#define AVC_SPSERR_GBU_PARSING_ERROR 0x00001019 +#define AVC_SPSERR_VUI_ERROR 0x0000101B +#define AVC_SPSERR_ACTIVATE_SPS 0x0000101C +#define AVC_PPSERR_PPS_PIC_PARAMETER_SET_ID 0x00002000 +#define AVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID 0x00002001 +#define AVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1 0x00002002 +#define AVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1 0x00002003 +#define AVC_PPSERR_INIT_QP_MINUS26 0x00002004 +#define AVC_PPSERR_PPS_CB_QP_OFFSET 0x00002006 +#define AVC_PPSERR_PPS_CR_QP_OFFSET 0x00002007 +#define AVC_PPSERR_SCALING_LIST 0x0000200E +#define AVC_PPSERR_MORE_RBSP_DATA_ERROR 0x00002012 +#define AVC_PPSERR_PPS_PIC_PARAMETER_SET_ID_RANGE_OUT 0x00002013 +#define AVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID_RANGE_OUT 0x00002014 +#define AVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1_RANGE_OUT 0x00002015 +#define AVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1_RANGE_OUT 0x00002016 +#define AVC_PPSERR_PPS_CB_QP_OFFSET_RANGE_OUT 0x00002017 +#define AVC_PPSERR_PPS_CR_QP_OFFSET_RANGE_OUT 0x00002018 +#define AVC_SHERR_SLICE_PIC_PARAMETER_SET_ID 0x00003000 +#define AVC_SHERR_ACTIVATE_PPS 0x00003001 +#define AVC_SHERR_ACTIVATE_SPS 0x00003002 +#define AVC_SHERR_SLICE_TYPE 0x00003003 +#define AVC_SHERR_FIRST_MB_IN_SLICE 0x00003004 +#define AVC_SHERR_RPLM 0x00003006 +#define AVC_SHERR_LT_IDX_SPS_IS_OUT_OF_RANGE 0x0000300A +#define AVC_SHERR_NUM_REF_IDX_L0_ACTIVE_MINUS1 0x0000300C +#define AVC_SHERR_NUM_REF_IDX_L1_ACTIVE_MINUS1 0x0000300D +#define AVC_SHERR_PRED_WEIGHT_TABLE 0x0000300F +#define AVC_SHERR_SLICE_QP_DELTA 0x00003011 +#define AVC_SHERR_SLICE_BETA_OFFSET_DIV2 0x00003015 +#define AVC_SHERR_SLICE_TC_OFFSET_DIV2 0x00003016 +#define AVC_SHERR_DISABLE_DEBLOCK_FILTER_IDC 0x00003017 +#define AVC_SPECERR_OVER_PICTURE_WIDTH_SIZE 0x00004000 +#define AVC_SPECERR_OVER_PICTURE_HEIGHT_SIZE 0x00004001 +#define AVC_SPECERR_OVER_CHROMA_FORMAT 0x00004002 +#define AVC_SPECERR_OVER_BIT_DEPTH 0x00004003 +#define AVC_SPECERR_OVER_BUFFER_OVER_FLOW 0x00004004 +#define AVC_SPECERR_OVER_WRONG_BUFFER_ACCESS 0x00004005 +#define AVC_ETCERR_INIT_SEQ_SPS_NOT_FOUND 0x00005000 +#define AVC_ETCERR_DEC_PIC_VCL_NOT_FOUND 0x00005001 +#define AVC_ETCERR_NO_VALID_SLICE_IN_AU 0x00005002 +#define AVC_ETCERR_ASO 0x00005004 +#define AVC_ETCERR_FMO 0x00005005 +#define AVC_ETCERR_INPLACE_V 0x0000500F + +// AV1 +#define AV1_SPSERR_MAX_FRAME_WIDTH 0x00001001 +#define AV1_SPSERR_MAX_FRAME_HEIGHT 0x00001002 +#define AV1_SPSERR_ID_LEN_EXCEED_16 0x00001004 +#define AV1_SPSERR_NOT_FOUND_FIRST_SPS 0x0000100A +#define AV1_SPSERR_SEQ_PROFILE 0x0000100B +#define AV1_SPSERR_STILL_PICTURE 0x0000100C +#define AV1_PPSERR_FRAME_SIZE_WIDTH 0x00002001 +#define AV1_PPSERR_FRAME_SIZE_HEIGHT 0x00002002 +#define AV1_PPSERR_SEEN_FRAME_HEADER 0x00002003 +#define AV1_PPSERR_REF_VALID 0x00002007 +#define AV1_PPSERR_LAST_ORDER_HINT 0x0000200B +#define AV1_PPSERR_GOLD_ORDER_HINT 0x0000200C +#define AV1_PPSERR_CODED_LOSSLESS_DELTA_Q 0x0000200E +#define AV1_PPSERR_FILM_GRAIN_PARAM_REF_IDX 0x0000200F +#define AV1_PPSERR_SEQ_CHANGE_BIT_DEPTH 0x00002010 +#define AV1_PPSERR_SEQ_CHANGE_PROFILE 0x00002012 +#define AV1_PPSERR_SEQ_CHANGE_DETECTED_INTER 0x00002013 +#define AV1_PPSERR_NUM_Y_POINTS 0x00002014 +#define AV1_PPSERR_POINT_Y_VALUE 0x00002015 +#define AV1_PPSERR_NUM_CB_POINTS 0x00002016 +#define AV1_PPSERR_POINT_CB_VALUE 0x00002017 +#define AV1_PPSERR_NUM_CR_POINTS 0x00002018 +#define AV1_PPSERR_POINT_CR_VALUE 0x00002019 +#define AV1_PPSERR_SUBSAMPLING_FORMAT 0x0000201A +#define AV1_FRAMEERR_TILE_START_END_PRESENT 0x00003001 +#define AV1_FRAMEERR_SHOW_EXISING_FRAME 0x00003002 +#define AV1_TGERR_NUM_TILES_ZERO 0x00004001 +#define AV1_TGERR_START_NOT_TILE_NUM 0x00004002 +#define AV1_TGERR_END_LESS_THAN_TG_START 0x00004003 +#define AV1_TGERR_TILE_SIZE_GREATER_THAN_32M 0x00004004 +#define AV1_SPECERR_OVER_MAX_H_SIZE 0x00005001 +#define AV1_SPECERR_OVER_MAX_V_SIZE 0x00005002 +#define AV1_SPECERR_OVER_MAX_TILE_COLS 0x00005004 +#define AV1_SPECERR_OVER_MAX_TILE_ROWS 0x00005005 +#define AV1_SPECERR_OVER_TILE_SIZE 0x00005006 +#define AV1_SPECERR_OVER_NUMTILES_GT_MAX_TILES 0x00005007 +#define AV1_ETCERR_OBU_HEADER 0x00006001 +#define AV1_ETCERR_OBU_SIZE 0x00006003 +#define AV1_ETCERR_OVERCONSUME 0x00006004 +#define AV1_ETCERR_NOT_SUPPORTED_FEATURE 0x00006005 +#define AV1_ETCERR_RESILIENCE_FAIL 0x00006006 + +// VP9 +#define VP9_PICERR_FRAME_MARKER 0x00001000 +#define VP9_PICERR_PROFILE 0x00001001 +#define VP9_PICERR_SYNC_CODE 0x00001002 +#define VP9_PICERR_PROFILE_COLOR_SAMPLE 0x00001003 +#define VP9_PICERR_FRAME_SIZE 0x00001004 +#define VP9_PICERR_SEGMENT 0x00001005 +#define VP9_PICERR_TILE 0x00001006 +#define VP9_PICERR_PROFILE_COMP_MISMATCH_WITH_REF 0x00001007 +#define VP9_PICERR_COMP_DAT_OVER_CS 0x00001008 +#define VP9_PICERR_COMP_TRAILING_BIT_ERR 0x00001009 +#define VP9_PICERR_MARKER 0x0000100A +#define VP9_PICERR_NOT_EXIST_REF_FRAME 0x0000100B +#define VP9_PICERR_UNINIT_CTX 0x0000100C +#define VP9_PICERR_FRAME_SIZE_LIMIT_BY_REF 0x0000100D +#define VP9_SPECERR_OVER_PICTURE_WIDTH_SIZE 0x00004000 +#define VP9_SPECERR_OVER_PICTURE_HEIGHT_SIZE 0x00004001 +#define VP9_SPECERR_OVER_CHROMA_FORMAT 0x00004002 +#define VP9_SPECERR_OVER_BIT_DEPTH 0x00004003 +#define VP9_ETCERR_INIT_KEY_FRAME_NOT_FOUND 0x00005000 +#define VP9_ETCERR_FORBIDDEN_BS_MODE 0x00005004 +#define VP9_ETCERR_SPP_OVER_CS_AU 0x00005005 + +// AVS2 +#define AVS2_SPSERR_PROFILE_ID 0x00001000 +#define AVS2_SPSERR_LEVEL_ID 0x00001001 +#define AVS2_SPSERR_HORIZONTAL_SIZE 0x00001002 +#define AVS2_SPSERR_VERTICAL_SIZE 0x00001003 +#define AVS2_SPSERR_CHROMA_FORMAT 0x00001004 +#define AVS2_SPSERR_SAMPLE_PRECISION 0x00001005 +#define AVS2_SPSERR_ENCODING_PRECISION 0x00001006 +#define AVS2_SPSERR_LCU_SIZE 0x00001007 +#define AVS2_SPSERR_WEIGHT_QUANT_MATRIX 0x00001008 +#define AVS2_SPSERR_NUM_OF_RCS 0x00001009 +#define AVS2_SPSERR_REFERENCE_CONFIGURATION_SET 0x0000100A +#define AVS2_SPSERR_OUTPUT_REORDER_DELAY 0x0000100B +#define AVS2_PPSERR_BBV_DELAY 0x00002000 +#define AVS2_PPSERR_TIME_CODE 0x00002001 +#define AVS2_PPSERR_DECODE_ORDER_INDEX 0x00002002 +#define AVS2_PPSERR_TEMPORAL_ID 0x00002003 +#define AVS2_PPSERR_PICTURE_OUTPUT_DELAY 0x00002004 +#define AVS2_PPSERR_RCS_INDEX 0x00002005 +#define AVS2_PPSERR_REFERENCE_CONFIGURATION_SET 0x00002006 +#define AVS2_PPSERR_BBV_CHECK_TIMES 0x00002007 +#define AVS2_PPSERR_PICTURE_QP 0x00002008 +#define AVS2_PPSERR_ALPHA_C_OFFSET 0x00002009 +#define AVS2_PPSERR_BETA_OFFSET 0x0000200A +#define AVS2_PPSERR_CHROMA_QUANT_PARAM_DELTA_CB 0x0000200B +#define AVS2_PPSERR_CHROMA_QUANT_PARAM_DELTA_CR 0x0000200C +#define AVS2_PPSERR_WEIGHT_QUANT_PARAM_DELTA1 0x0000200D +#define AVS2_PPSERR_WEIGHT_QUANT_PARAM_DELTA2 0x0000200E +#define AVS2_PPSERR_PICTURE_CODING_TYPE 0x0000200F +#define AVS2_PPSERR_ALF_FILTER_NUM_MINUS1 0x00002010 +#define AVS2_PPSERR_ALF_REGION_DISTANCE 0x00002011 +#define AVS2_PPSERR_ALF_COEFF_LUMA 0x00002012 +#define AVS2_PPSERR_ALF_COEFF_CHROMA_CB 0x00002013 +#define AVS2_PPSERR_ALF_COEFF_CHROMA_CR 0x00002014 +#define AVS2_SHERR_SLICE_VERTICAL_POSITION 0x00003000 +#define AVS2_SHERR_SLICE_VERTICAL_POSITION_EXTENSION 0x00003001 +#define AVS2_SHERR_SLICE_HORIZONTAL_POSITION 0x00003002 +#define AVS2_SHERR_SLICE_HORIZONTAL_POSITION_EXTENSION 0x00003003 +#define AVS2_SHERR_FIXED_SLICE_QP 0x00003004 +#define AVS2_SHERR_SLICE_QP 0x00003005 +#define AVS2_SHERR_SLICE_SAO_ENABLE_FLAG 0x00003006 +#define AVS2_SHERR_AEC_BYTE_ALIGNMENT_BIT 0x00003007 +#define AVS2_SHERR_STREAM_END 0x00003008 +#define AVS2_SPECERR_OVER_PICTURE_WIDTH_SIZE 0x00004000 +#define AVS2_SPECERR_OVER_PICTURE_HEIGHT_SIZE 0x00004001 +#define AVS2_SPECERR_OVER_CHROMA_FORMAT 0x00004002 +#define AVS2_SPECERR_OVER_BIT_DEPTH 0x00004003 +#define AVS2_SPECERR_OVER_REF_TEMPORAL_ID 0x00004004 +#define AVS2_ETCERR_SPS_NOT_FOUND 0x00005000 +#define AVS2_ETCERR_DEC_PIC_VCL_NOT_FOUND 0x00005001 +#define AVS2_ETCERR_NO_VALID_SLICE_IN_AU 0x00005002 +#define AVS2_ETCERR_PPS_ERROR 0x00005003 +#define AVS2_ETCERR_SLICE_NUM_OVERFLOW 0x00005004 + +/************************************************************************/ +/* WAVE5 WARNING ON DECODER (WARN_INFO) */ +/************************************************************************/ +// HEVC +#define HEVC_SPSWARN_MAX_SUB_LAYERS_MINUS1 0x00000001 +#define HEVC_SPSWARN_GENERAL_RESERVED_ZERO_44BITS 0x00000002 +#define HEVC_SPSWARN_RESERVED_ZERO_2BITS 0x00000004 +#define HEVC_SPSWARN_SUB_LAYER_RESERVED_ZERO_44BITS 0x00000008 +#define HEVC_SPSWARN_GENERAL_LEVEL_IDC 0x00000010 +#define HEVC_SPSWARN_SPS_MAX_DEC_PIC_BUFFERING_VALUE_OVER 0x00000020 +#define HEVC_SPSWARN_RBSP_TRAILING_BITS 0x00000040 +#define HEVC_SPSWARN_ST_RPS_UE_ERROR 0x00000080 +#define HEVC_SPSWARN_EXTENSION_FLAG 0x01000000 +#define HEVC_SPSWARN_REPLACED_WITH_PREV_SPS 0x02000000 +#define HEVC_PPSWARN_RBSP_TRAILING_BITS 0x00000100 +#define HEVC_PPSWARN_REPLACED_WITH_PREV_PPS 0x00000200 +#define HEVC_SHWARN_FIRST_SLICE_SEGMENT_IN_PIC_FLAG 0x00001000 +#define HEVC_SHWARN_NO_OUTPUT_OF_PRIOR_PICS_FLAG 0x00002000 +#define HEVC_SHWARN_PIC_OUTPUT_FLAG 0x00004000 +#define HEVC_SHWARN_DUPLICATED_SLICE_SEGMENT 0x00008000 +#define HEVC_ETCWARN_INIT_SEQ_VCL_NOT_FOUND 0x00010000 +#define HEVC_ETCWARN_MISSING_REFERENCE_PICTURE 0x00020000 +#define HEVC_ETCWARN_WRONG_TEMPORAL_ID 0x00040000 +#define HEVC_ETCWARN_ERROR_PICTURE_IS_REFERENCED 0x00080000 +#define HEVC_SPECWARN_OVER_PROFILE 0x00100000 +#define HEVC_SPECWARN_OVER_LEVEL 0x00200000 +#define HEVC_PRESWARN_PARSING_ERR 0x04000000 +#define HEVC_PRESWARN_MVD_OUT_OF_RANGE 0x08000000 +#define HEVC_PRESWARN_CU_QP_DELTA_VAL_OUT_OF_RANGE 0x09000000 +#define HEVC_PRESWARN_COEFF_LEVEL_REMAINING_OUT_OF_RANGE 0x0A000000 +#define HEVC_PRESWARN_PCM_ERR 0x0B000000 +#define HEVC_PRESWARN_OVERCONSUME 0x0C000000 +#define HEVC_PRESWARN_END_OF_SUBSET_ONE_BIT_ERR 0x10000000 +#define HEVC_PRESWARN_END_OF_SLICE_SEGMENT_FLAG 0x20000000 + +// AVC +#define AVC_SPSWARN_RESERVED_ZERO_2BITS 0x00000004 +#define AVC_SPSWARN_GENERAL_LEVEL_IDC 0x00000010 +#define AVC_SPSWARN_RBSP_TRAILING_BITS 0x00000040 +#define AVC_PPSWARN_RBSP_TRAILING_BITS 0x00000100 +#define AVC_SHWARN_NO_OUTPUT_OF_PRIOR_PICS_FLAG 0x00002000 +#define AVC_ETCWARN_INIT_SEQ_VCL_NOT_FOUND 0x00010000 +#define AVC_ETCWARN_MISSING_REFERENCE_PICTURE 0x00020000 +#define AVC_ETCWARN_ERROR_PICTURE_IS_REFERENCED 0x00080000 +#define AVC_SPECWARN_OVER_PROFILE 0x00100000 +#define AVC_SPECWARN_OVER_LEVEL 0x00200000 +#define AVC_PRESWARN_MVD_RANGE_OUT 0x00400000 +#define AVC_PRESWARN_MB_QPD_RANGE_OUT 0x00500000 +#define AVC_PRESWARN_COEFF_RANGE_OUT 0x00600000 +#define AVC_PRESWARN_MV_RANGE_OUT 0x00700000 +#define AVC_PRESWARN_MB_SKIP_RUN_RANGE_OUT 0x00800000 +#define AVC_PRESWARN_MB_TYPE_RANGE_OUT 0x00900000 +#define AVC_PRESWARN_SUB_MB_TYPE_RANGE_OUT 0x00A00000 +#define AVC_PRESWARN_CBP_RANGE_OUT 0x00B00000 +#define AVC_PRESWARN_INTRA_CHROMA_PRED_MODE_RANGE_OUT 0x00C00000 +#define AVC_PRESWARN_REF_IDX_RANGE_OUT 0x00D00000 +#define AVC_PRESWARN_COEFF_TOKEN_RANGE_OUT 0x00E00000 +#define AVC_PRESWARN_TOTAL_ZERO_RANGE_OUT 0x00F00000 +#define AVC_PRESWARN_RUN_BEFORE_RANGE_OUT 0x01000000 +#define AVC_PRESWARN_OVERCONSUME 0x01100000 +#define AVC_PRESWARN_MISSING_SLICE 0x01200000 + +// AV1 +#define AV1_SPSWARN_OBU_EXTENSION_FLAG_ZERO 0x00001000 +#define AV1_SPSWARN_DUPLICATE_OPERATING_POINT_IDX 0x00001001 +#define AV1_SPSWARN_MC_IDENTIY_SUBSAMPLING_X 0x00001002 +#define AV1_PPSWARN_MC_IDENTIY_SUBSAMPLING_Y 0x00001003 +#define AV1_SPSWARN_NUM_UNITS_IN_DISPLAY_TICK 0x00001004 +#define AV1_SPSWARN_TIME_SCALE_ZERO 0x00001005 +#define AV1_SPSWARN_NUM_TICKS_PER_PICTURE 0x00001006 +#define AV1_PPSWARN_TILE_WIDTH 0x00002001 +#define AV1_PPSWARN_TILE_HEIGHT 0x00002002 +#define AV1_PPSWARN_SHOW_EXISTING_KEY_FRAME_OUTPUT 0x00002004 +#define AV1_PPSWARN_DIFF_FRAME_ID 0x00002008 +#define AV1_PPSWARN_CURRENT_FRAME_ID 0x00002010 +#define AV1_PPSWARN_REFRESH_FRAME_FLAGS 0x00002020 +#define AV1_PPSWARN_DISPLAY_ID 0x00002040 +#define AV1_PPSWARN_PREV_FRAME_SHOWABLE_FLAG_ZERO 0x00002080 +#define AV1_PPSWARN_EXPECTED_FRAME_ID 0x00002100 +#define AV1_SPECWARN_OVER_MAX_TILE_AREA_SB 0x00005000 +#define AV1_SPECWARN_OVER_MAX_PIC_SIZE 0x00005001 +#define AV1_ETCWARN_OBU_EXTENSION_FLAG 0x00006000 +#define AV1_TGWARN_TRAIL_BIT_POS 0x00400000 +#define AV1_TGWARN_TRAIL_PAD_BIT 0x00800000 +#define AV1_TGWARN_SYM_MAX_OVER 0x01000000 +#define AV1_TGWARN_EXP_GOLB_OVER 0x02000000 +#define AV1_TGWARN_MV_NOT_VALID 0x04000000 + +// VP9 +#define VP9_PICWARN_COLOR_SPACE_MISMATCH_WITH_REF 0x00001000 +#define VP9_PRESWARN_OVERCONSUME 0x00400000 +#define VP9_PRESWARN_TRAILING_BITS 0x00800000 +#define VP9_PRESWARN_MARKER 0x01000000 +#define VP9_PRESWARN_MV_RANGE_OVER 0x02000000 +#define VP9_PRESWARN_MISIZE_SEG_LVL_ACTIVE 0x04000000 + +// AVS2 +#define AVS2_ETCWARN_INIT_SEQ_VCL_NOT_FOUND 0x00010000 +#define AVS2_ETCWARN_MISSING_REFERENCE_PICTURE 0x00020000 +#define AVS2_ETCWARN_WRONG_TEMPORAL_ID 0x00040000 +#define AVS2_ETCWARN_ERROR_PICTURE_IS_REFERENCED 0x00080000 +#define AVS2_ETCWARN_REF_WRONG_TEMPORAL_ID 0x00080001 +#define AVS2_ETCWARN_SPS_ERROR 0x00080002 + +/************************************************************************/ +/* WAVE5 ERROR ON ENCODER (ERR_INFO) */ +/************************************************************************/ + +/************************************************************************/ +/* WAVE5 WARNING ON ENCODER (WARN_INFO) */ +/************************************************************************/ +#define WAVE5_ETCWARN_FORCED_SPLIT_BY_CU8X8 0x000000001 + +/************************************************************************/ +/* WAVE5 debug info (PRI_REASON) */ +/************************************************************************/ +#define WAVE5_DEC_VCORE_VCE_HANGUP 0x0001 +#define WAVE5_DEC_VCORE_UNDETECTED_SYNTAX_ERR 0x0002 +#define WAVE5_DEC_VCORE_MIB_BUSY 0x0003 +#define WAVE5_DEC_VCORE_VLC_BUSY 0x0004 + +#endif /* ERROR_CODE_H_INCLUDED */ diff --git a/drivers/media/platform/chips-media/wave5/wave5.h b/drivers/media/platform/chips-media/wave5/wave5.h new file mode 100644 index 000000000000..d3afb541e356 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * Wave5 series multi-standard codec IP - wave5 backend definitions + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#ifndef __WAVE5_FUNCTION_H__ +#define __WAVE5_FUNCTION_H__ + +#define WAVE5_SUBSAMPLED_ONE_SIZE(_w, _h) (ALIGN((_w) / 4, 16) * ALIGN((_h) / 4, 8)) +#define WAVE5_SUBSAMPLED_ONE_SIZE_AVC(_w, _h) (ALIGN((_w) / 4, 32) * ALIGN((_h) / 4, 4)) + +#define BSOPTION_ENABLE_EXPLICIT_END BIT(0) + +#define WTL_RIGHT_JUSTIFIED 0 +#define WTL_LEFT_JUSTIFIED 1 +#define WTL_PIXEL_8BIT 0 +#define WTL_PIXEL_16BIT 1 +#define WTL_PIXEL_32BIT 2 + +/* Mirror & rotation modes of the PRP (pre-processing) module */ +#define NONE_ROTATE 0x0 +#define ROT_CLOCKWISE_90 0x3 +#define ROT_CLOCKWISE_180 0x5 +#define ROT_CLOCKWISE_270 0x7 +#define MIR_HOR_FLIP 0x11 +#define MIR_VER_FLIP 0x9 +#define MIR_HOR_VER_FLIP (MIR_HOR_FLIP | MIR_VER_FLIP) + +bool wave5_vpu_is_init(struct vpu_device *vpu_dev); + +unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev); + +void wave5_bit_issue_command(struct vpu_instance *inst, u32 cmd); + +int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision); + +int wave5_vpu_init(struct device *dev, u8 *fw, size_t size); + +int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode); + +int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, struct dec_open_param *param); + +int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos); + +int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, + struct frame_buffer *fb_arr, enum tiled_map_type map_type, + unsigned int count); + +int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size); + +int wave5_vpu_dec_init_seq(struct vpu_instance *inst); + +int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info); + +int wave5_vpu_decode(struct vpu_instance *inst, struct dec_param *option, u32 *fail_res); + +int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result); + +int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res); + +int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index); + +int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index); + +int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags); + +dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst); + +int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr); + +/***< WAVE5 encoder >******/ + +int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst, + struct enc_open_param *open_param); + +int wave5_vpu_enc_init_seq(struct vpu_instance *inst); + +int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info); + +int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst, + struct frame_buffer *fb_arr, enum tiled_map_type map_type, + unsigned int count); + +int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res); + +int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result); + +int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res); + +int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param); + +#endif /* __WAVE5_FUNCTION_H__ */ -- 2.25.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v11 2/6] media: chips-media: wave5: Add vpuapi layer 2022-12-07 12:13 ` [PATCH v11 2/6] media: chips-media: wave5: Add vpuapi layer Sebastian Fricke @ 2022-12-07 13:05 ` AngeloGioacchino Del Regno 2022-12-15 13:31 ` Sebastian Fricke 0 siblings, 1 reply; 22+ messages in thread From: AngeloGioacchino Del Regno @ 2022-12-07 13:05 UTC (permalink / raw) To: Sebastian Fricke, linux-media, Nas Chung, Robert Beckett, Mauro Carvalho Chehab Cc: kernel, hverkuil-cisco, nicolas.dufresne, linux-kernel Il 07/12/22 13:13, Sebastian Fricke ha scritto: > From: Nas Chung <nas.chung@chipsnmedia.com> > > Add the vpuapi layer of the wave5 codec driver. > This layer is used to configure the hardware according > to the parameters. > > Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> > Signed-off-by: Robert Beckett <bob.beckett@collabora.com> > Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> > Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com> > --- > .../platform/chips-media/wave5/wave5-hw.c | 3359 +++++++++++++++++ > .../chips-media/wave5/wave5-regdefine.h | 743 ++++ > .../platform/chips-media/wave5/wave5-vdi.c | 245 ++ > .../platform/chips-media/wave5/wave5-vdi.h | 67 + > .../platform/chips-media/wave5/wave5-vpuapi.c | 1040 +++++ > .../platform/chips-media/wave5/wave5-vpuapi.h | 1136 ++++++ > .../chips-media/wave5/wave5-vpuconfig.h | 90 + > .../chips-media/wave5/wave5-vpuerror.h | 454 +++ > .../media/platform/chips-media/wave5/wave5.h | 94 + > 9 files changed, 7228 insertions(+) > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-hw.c > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-regdefine.h > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vdi.c > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vdi.h > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpuapi.c > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpuapi.h > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpuerror.h > create mode 100644 drivers/media/platform/chips-media/wave5/wave5.h > > diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c > new file mode 100644 > index 000000000000..25705e61cdb3 > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c > @@ -0,0 +1,3359 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > +/* > + * Wave5 series multi-standard codec IP - wave5 backend logic > + * > + * Copyright (C) 2021 CHIPS&MEDIA INC > + */ > + > +#include <linux/iopoll.h> > +#include "wave5-vpu.h" > +#include "wave5.h" > +#include "wave5-regdefine.h" > + > +#define FIO_TIMEOUT 10000000 FIO_TIMEOUT_US looks better :-) > +#define FIO_CTRL_READY BIT(31) > +#define FIO_CTRL_WRITE BIT(16) > +#define VPU_BUSY_CHECK_TIMEOUT 10000000 > +#define QUEUE_REPORT_MASK 0xffff > + > +static void wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason) > +{ > + char *caller = __builtin_return_address(0); > + struct device *dev = vpu_dev->dev; > + u32 reg_val; > + > + switch (reg_fail_reason) { > + case WAVE5_SYSERR_QUEUEING_FAIL: > + reg_val = vpu_read_reg(vpu_dev, W5_RET_QUEUE_FAIL_REASON); > + dev_dbg(dev, "%s: queueing failure: 0x%x\n", caller, reg_val); > + break; > + case WAVE5_SYSERR_RESULT_NOT_READY: > + dev_err(dev, "%s: result not ready: 0x%x\n", caller, reg_fail_reason); > + break; > + case WAVE5_SYSERR_ACCESS_VIOLATION_HW: > + dev_err(dev, "%s: access violation: 0x%x\n", caller, reg_fail_reason); > + break; > + case WAVE5_SYSERR_WATCHDOG_TIMEOUT: > + dev_err(dev, "%s: watchdog timeout: 0x%x\n", caller, reg_fail_reason); > + break; > + case WAVE5_SYSERR_BUS_ERROR: > + dev_err(dev, "%s: bus error: 0x%x\n", caller, reg_fail_reason); > + break; > + case WAVE5_SYSERR_DOUBLE_FAULT: > + dev_err(dev, "%s: double fault: 0x%x\n", caller, reg_fail_reason); > + break; > + case WAVE5_SYSERR_VPU_STILL_RUNNING: > + dev_err(dev, "%s: still running: 0x%x\n", caller, reg_fail_reason); > + break; > + case WAVE5_SYSERR_VLC_BUF_FULL: > + dev_err(dev, "%s: vlc buf full: 0x%x\n", caller, reg_fail_reason); > + break; > + default: > + dev_err(dev, "%s: failure:: 0x%x\n", caller, reg_fail_reason); > + break; > + } > +} > + > +static int wave5_wait_fio_readl(struct vpu_device *vpu_dev, u32 addr, u32 val) > +{ > + u32 ctrl; > + int ret; > + > + ctrl = addr & 0xffff; > + wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl); > + ret = read_poll_timeout(wave5_vdi_readl, ctrl, ctrl & FIO_CTRL_READY, > + 0, FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR); > + if (ret) > + return ret; > + if (wave5_vdi_readl(vpu_dev, W5_VPU_FIO_DATA) != val) > + return -ETIMEDOUT; Are you sure that this is a timeout? if (read_data != expected_data) => invalid data => return -EINVAL ? > + return 0; > +} > + ..snip.. > + > +static int wave5_wait_bus_busy(struct vpu_device *vpu_dev, unsigned int addr) > +{ > + u32 gdi_status_check_value = 0x3f; > + > + if (vpu_dev->product_code == WAVE521C_CODE || > + vpu_dev->product_code == WAVE521_CODE || > + vpu_dev->product_code == WAVE521E1_CODE) > + gdi_status_check_value = 0x00ff1f3f; #define SOME_VALUE 0x3f #define ANOTHER_VALUE 0xff1f3f > + > + return wave5_wait_fio_readl(vpu_dev, addr, gdi_status_check_value); > +} > + ..snip.. > + > +static int setup_wave5_properties(struct device *dev) > +{ > + struct vpu_device *vpu_dev = dev_get_drvdata(dev); > + struct vpu_attr *p_attr = &vpu_dev->attr; > + u32 reg_val; > + u8 *str; > + int ret; > + u32 hw_config_def0, hw_config_def1, hw_config_feature, hw_config_rev; > + > + vpu_write_reg(vpu_dev, W5_QUERY_OPTION, GET_VPU_INFO); > + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); > + vpu_write_reg(vpu_dev, W5_COMMAND, W5_QUERY); > + vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); > + ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); > + if (ret) > + return ret; > + > + if (!vpu_read_reg(vpu_dev, W5_RET_SUCCESS)) > + return -EIO; > + > + reg_val = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_NAME); > + str = (u8 *)®_val; > + p_attr->product_name[0] = str[3]; > + p_attr->product_name[1] = str[2]; > + p_attr->product_name[2] = str[1]; > + p_attr->product_name[3] = str[0]; > + p_attr->product_name[4] = 0; > + > + p_attr->product_id = wave5_vpu_get_product_id(vpu_dev); > + p_attr->product_version = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_VERSION); > + p_attr->fw_version = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); > + p_attr->customer_id = vpu_read_reg(vpu_dev, W5_RET_CUSTOMER_ID); > + hw_config_def0 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF0); > + hw_config_def1 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF1); > + hw_config_feature = vpu_read_reg(vpu_dev, W5_RET_CONF_FEATURE); > + hw_config_rev = vpu_read_reg(vpu_dev, W5_RET_CONF_REVISION); > + > + p_attr->support_hevc10bit_enc = (hw_config_feature >> 3) & 1; This looks like being BIT(3), and the latter is BIT(11)... #define W5_CONF_FEATURE_HEVC10_ENC BIT(3) #define W5_CONF_FEATURE_AVC10_ENC BIT(11) p_attr->support_hevc10bit_enc = FIELD_GET(W5_CONF_FEATURE_HEVC10_ENC, hw_config_feature); if (hw_config_rev > W5_REVISION_SOMETHING) p_attr->support_avc10bit_enc = FIELD_GET(W5_CONF_FEATURE_AVC10_ENC, hw_config_feature); else p_attr->support_avc10bit_enc = p_attr->support_hevc10bit_enc; > + if (hw_config_rev > 167455) //20190321 > + p_attr->support_avc10bit_enc = (hw_config_feature >> 11) & 1; > + else > + p_attr->support_avc10bit_enc = p_attr->support_hevc10bit_enc; > + > + p_attr->support_decoders = 0; > + p_attr->support_encoders = 0; > + if (p_attr->product_id == PRODUCT_ID_521) { > + p_attr->support_dual_core = ((hw_config_def1 >> 26) & 0x01); p_attr->support_dual_core = FIELD_GET(W5_CONF_DEF_HW_DUAL_CORE, hw_config_def1); ....and there are others below, but I think I gave enough examples... :-) > + if (p_attr->support_dual_core || hw_config_rev < 206116) { > + p_attr->support_decoders = BIT(STD_AVC); > + p_attr->support_decoders |= BIT(STD_HEVC); > + p_attr->support_encoders = BIT(STD_AVC); > + p_attr->support_encoders |= BIT(STD_HEVC); > + } else { > + p_attr->support_decoders |= (((hw_config_def1 >> 3) & 0x01) << STD_AVC); > + p_attr->support_decoders |= (((hw_config_def1 >> 2) & 0x01) << STD_HEVC); > + p_attr->support_encoders = (((hw_config_def1 >> 1) & 0x01) << STD_AVC); > + p_attr->support_encoders |= ((hw_config_def1 & 0x01) << STD_HEVC); > + } > + } else if (p_attr->product_id == PRODUCT_ID_511) { > + p_attr->support_decoders = BIT(STD_HEVC); > + p_attr->support_decoders |= BIT(STD_AVC); > + } else if (p_attr->product_id == PRODUCT_ID_517) { > + p_attr->support_decoders = (((hw_config_def1 >> 4) & 0x01) << STD_AV1); > + p_attr->support_decoders |= (((hw_config_def1 >> 3) & 0x01) << STD_AVS2); > + p_attr->support_decoders |= (((hw_config_def1 >> 2) & 0x01) << STD_AVC); > + p_attr->support_decoders |= (((hw_config_def1 >> 1) & 0x01) << STD_VP9); > + p_attr->support_decoders |= ((hw_config_def1 & 0x01) << STD_HEVC); > + } > + > + p_attr->support_backbone = (hw_config_def0 >> 16) & 0x01; > + p_attr->support_vcpu_backbone = (hw_config_def0 >> 28) & 0x01; > + p_attr->support_vcore_backbone = (hw_config_def0 >> 22) & 0x01; > + p_attr->support_dual_core = (hw_config_def1 >> 26) & 0x01; > + p_attr->support_endian_mask = BIT(VDI_LITTLE_ENDIAN) | > + BIT(VDI_BIG_ENDIAN) | > + BIT(VDI_32BIT_LITTLE_ENDIAN) | > + BIT(VDI_32BIT_BIG_ENDIAN) | > + (0xffffUL << 16); > + p_attr->support_bitstream_mode = BIT(BS_MODE_INTERRUPT) | > + BIT(BS_MODE_PIC_END); > + > + return 0; > +} > + > +int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision) > +{ > + u32 reg_val; > + int ret; > + > + vpu_write_reg(vpu_dev, W5_QUERY_OPTION, GET_VPU_INFO); > + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); > + vpu_write_reg(vpu_dev, W5_COMMAND, W5_QUERY); > + vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); > + ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); > + if (ret) { > + dev_err(vpu_dev->dev, "%s: timeout\n", __func__); > + return ret; > + } > + > + if (!vpu_read_reg(vpu_dev, W5_RET_SUCCESS)) { > + dev_err(vpu_dev->dev, "%s: failed\n", __func__); > + return -EIO; > + } > + > + reg_val = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); > + if (revision) Move the revision pointer null check at the beginning and return an error if that happens to be null: it doesn't make a lot of sense to read many registers before the check as the whole point of this function is to get the version and return it to that variable. > + *revision = reg_val; > + > + return 0; > +} > + > +static void remap_page(struct vpu_device *vpu_dev, dma_addr_t code_base, u32 index) > +{ > + u32 remap_size = (W5_REMAP_MAX_SIZE >> 12) & 0x1ff; > + u32 reg_val = 0x80000000 | (WAVE5_UPPER_PROC_AXI_ID << 20) | (index << 12) | BIT(11) > + | remap_size; > + > + vpu_write_reg(vpu_dev, W5_VPU_REMAP_CTRL, reg_val); > + vpu_write_reg(vpu_dev, W5_VPU_REMAP_VADDR, index * W5_REMAP_MAX_SIZE); > + vpu_write_reg(vpu_dev, W5_VPU_REMAP_PADDR, code_base + index * W5_REMAP_MAX_SIZE); > +} > + ..snip.. > + > +int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, > + struct dec_open_param *param) > +{ > + int ret; > + struct dec_info *p_dec_info = &inst->codec_info->dec_info; > + u32 bs_endian; > + struct dma_vpu_buf *sram_vb; > + struct vpu_device *vpu_dev = inst->dev; > + > + p_dec_info->cycle_per_tick = 256; > + switch (inst->std) { > + case W_HEVC_DEC: > + p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_HEVC; > + break; > + case W_VP9_DEC: > + p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_VP9; > + break; > + case W_AVS2_DEC: > + p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVS2; > + break; > + case W_AVC_DEC: > + p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVC; > + break; > + case W_AV1_DEC: > + p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AV1; > + break; > + default: > + return -EINVAL; > + } > + > + if (vpu_dev->product == PRODUCT_ID_517) Another switch would be good here. > + p_dec_info->vb_work.size = WAVE517_WORKBUF_SIZE; > + else if (vpu_dev->product == PRODUCT_ID_521) > + p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; > + else if (vpu_dev->product == PRODUCT_ID_511) > + p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; > + > + ret = wave5_vdi_allocate_dma_memory(inst->dev, &p_dec_info->vb_work); > + if (ret) > + return ret; > + > + vpu_write_reg(inst->dev, W5_CMD_DEC_VCORE_INFO, 1); > + > + sram_vb = &vpu_dev->sram_buf; > + p_dec_info->sec_axi_info.buf_base = sram_vb->daddr; > + p_dec_info->sec_axi_info.buf_size = sram_vb->size; > + > + wave5_vdi_clear_memory(inst->dev, &p_dec_info->vb_work); > + > + vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_dec_info->vb_work.daddr); > + vpu_write_reg(inst->dev, W5_WORK_SIZE, p_dec_info->vb_work.size); > + > + vpu_write_reg(inst->dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info->stream_buf_start_addr); > + vpu_write_reg(inst->dev, W5_CMD_DEC_BS_SIZE, p_dec_info->stream_buf_size); > + > + /* NOTE: when endian mode is 0, SDMA reads MSB first */ > + bs_endian = wave5_vdi_convert_endian(inst->dev, param->stream_endian); > + bs_endian = (~bs_endian & VDI_128BIT_ENDIAN_MASK); > + vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, bs_endian); > + vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, (param->pri_axprot << 20) | > + (param->pri_axcache << 16) | param->pri_ext_addr); > + vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, (COMMAND_QUEUE_DEPTH - 1)); > + vpu_write_reg(inst->dev, W5_CMD_ERR_CONCEAL, (param->error_conceal_unit << 2) | > + (param->error_conceal_mode)); > + > + wave5_bit_issue_command(inst, W5_CREATE_INSTANCE); > + // check QUEUE_DONE Please be consistent in comments format. Use C-style comments. > + ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); > + if (ret) { > + dev_warn(inst->dev->dev, "command: 'W5_CREATE_INSTANCE' timed out\n"); > + goto free_vb_work; > + } > + > + // Check if we were able to add the parameters into the VCPU QUEUE > + if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { > + ret = -EIO; > + goto free_vb_work; > + } > + > + p_dec_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); > + > + return 0; > +free_vb_work: > + wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); > + return ret; > +} > + ..snip.. > + > +static void wave5_get_dec_seq_result(struct vpu_instance *inst, struct dec_initial_info *info) > +{ > + u32 reg_val, sub_layer_info; > + u32 profile_compatibility_flag; > + u32 output_bit_depth_minus8; > + struct dec_info *p_dec_info = &inst->codec_info->dec_info; > + > + p_dec_info->stream_rd_ptr = wave5_vpu_dec_get_rd_ptr(inst); > + info->rd_ptr = p_dec_info->stream_rd_ptr; > + > + p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); > + > + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); > + info->pic_width = ((reg_val >> 16) & 0xffff); > + info->pic_height = (reg_val & 0xffff); > + info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REQUIRED_FB); > + info->frame_buf_delay = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REORDER_DELAY); > + > + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_LEFT_RIGHT); > + info->pic_crop_rect.left = (reg_val >> 16) & 0xffff; > + info->pic_crop_rect.right = reg_val & 0xffff; > + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_TOP_BOTTOM); > + info->pic_crop_rect.top = (reg_val >> 16) & 0xffff; > + info->pic_crop_rect.bottom = reg_val & 0xffff; > + > + info->f_rate_numerator = vpu_read_reg(inst->dev, W5_RET_DEC_FRAME_RATE_NR); > + info->f_rate_denominator = vpu_read_reg(inst->dev, W5_RET_DEC_FRAME_RATE_DR); > + > + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_COLOR_SAMPLE_INFO); > + info->luma_bitdepth = reg_val & 0xf; > + info->chroma_bitdepth = (reg_val >> 4) & 0xf; > + info->chroma_format_idc = (reg_val >> 8) & 0xf; > + info->aspect_rate_info = (reg_val >> 16) & 0xff; Bitfield macros would make this way more readable. > + info->is_ext_sar = ((info->aspect_rate_info == 255) ? true : false); > + /* [0:15] - vertical size, [16:31] - horizontal size */ > + if (info->is_ext_sar) > + info->aspect_rate_info = vpu_read_reg(inst->dev, W5_RET_DEC_ASPECT_RATIO); > + info->bit_rate = vpu_read_reg(inst->dev, W5_RET_DEC_BIT_RATE); > + > + sub_layer_info = vpu_read_reg(inst->dev, W5_RET_DEC_SUB_LAYER_INFO); > + info->max_temporal_layers = (sub_layer_info >> 8) & 0x7; > + > + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_SEQ_PARAM); > + info->level = reg_val & 0xff; > + profile_compatibility_flag = (reg_val >> 12) & 0xff; > + info->profile = (reg_val >> 24) & 0x1f; > + info->tier = (reg_val >> 29) & 0x01; > + output_bit_depth_minus8 = (reg_val >> 30) & 0x03; > + > + if (inst->std == W_HEVC_DEC) { > + /* guessing profile */ > + if (!info->profile) { > + if ((profile_compatibility_flag & 0x06) == 0x06) > + info->profile = HEVC_PROFILE_MAIN; /* main profile */ main/main10 profile comments are stating the obvious, please remove them. > + else if ((profile_compatibility_flag & 0x04) == 0x04) > + info->profile = HEVC_PROFILE_MAIN10; /* main10 profile */ > + else if ((profile_compatibility_flag & 0x08) == 0x08) > + /* main still picture profile */ > + info->profile = HEVC_PROFILE_STILLPICTURE; > + else > + info->profile = HEVC_PROFILE_MAIN; /* for old version HM */ > + } > + > + } else if (inst->std == W_AVS2_DEC) { > + if (info->luma_bitdepth == 10 && output_bit_depth_minus8 == 2) > + info->output_bit_depth = 10; > + else > + info->output_bit_depth = 8; > + > + } else if (inst->std == W_AVC_DEC) { > + info->profile = (reg_val >> 24) & 0x7f; > + } > + > + info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); > + info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); > + p_dec_info->vlc_buf_size = info->vlc_buf_size; > + p_dec_info->param_buf_size = info->param_buf_size; > +} > + ..snip.. > + > +static u32 calculate_table_size(u32 bit_depth, u32 frame_width, u32 frame_height, u32 ot_bg_width) > +{ > + u32 bgs_width = ((bit_depth > 8) ? 256 : 512); > + u32 comp_frame_width = ALIGN(ALIGN(frame_width, 16) + 16, 16); > + u32 ot_frame_width = ALIGN(comp_frame_width, ot_bg_width); > + > + // sizeof_offset_table() > + u32 ot_bg_height = 32; > + u32 bgs_height = BIT(14) / bgs_width / ((bit_depth > 8) ? 2 : 1); Please, no magic BIT(x) usage: add a definition for that bit. > + u32 comp_frame_height = ALIGN(ALIGN(frame_height, 4) + 4, bgs_height); > + u32 ot_frame_height = ALIGN(comp_frame_height, ot_bg_height); > + > + return (ot_frame_width / 16) * (ot_frame_height / 4) * 2; > +} > + ..snip.. > + > +int wave5_vpu_decode(struct vpu_instance *inst, struct dec_param *option, u32 *fail_res) > +{ > + u32 mode_option = DEC_PIC_NORMAL, bs_option, reg_val; > + u32 force_latency = 0; > + struct dec_info *p_dec_info = &inst->codec_info->dec_info; > + struct dec_open_param *p_open_param = &p_dec_info->open_param; > + int ret; > + switch (option->skipframe_mode) { case ... ... default: break; }; if (p_dec_info->thumbnail_mode) { mode_option = DEC_PIC_W_THUMBNAIL; if (mode_option != DEC_PIC_NORMAL) ... do something: as I read the code, this is not a supported case. } ^^^^ this should improve the flow. > + if (p_dec_info->thumbnail_mode) { > + mode_option = DEC_PIC_W_THUMBNAIL; > + } else if (option->skipframe_mode) { > + switch (option->skipframe_mode) { > + case WAVE_SKIPMODE_NON_IRAP: > + mode_option = SKIP_NON_IRAP; > + force_latency = 1; > + break; > + case WAVE_SKIPMODE_NON_REF: > + mode_option = SKIP_NON_REF_PIC; > + break; > + default: > + // skip mode off > + break; > + } > + } > + > + // set disable reorder > + if (!p_dec_info->reorder_enable) > + force_latency = 1; > + > + /* set attributes of bitstream buffer controller */ > + bs_option = 0; You don't have to initialize this variable at all, as you're either writing twice or failing. > + switch (p_open_param->bitstream_mode) { > + case BS_MODE_INTERRUPT: > + bs_option = BSOPTION_ENABLE_EXPLICIT_END; > + break; > + case BS_MODE_PIC_END: > + bs_option = BSOPTION_ENABLE_EXPLICIT_END; > + break; > + default: > + return -EINVAL; > + } > + ..snip.. > + > +int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) > +{ > + struct vpu_buf *common_vb; > + dma_addr_t code_base, temp_base; > + dma_addr_t old_code_base, temp_size; > + u32 code_size; > + u32 reg_val; > + struct vpu_device *vpu_dev = dev_get_drvdata(dev); > + > + common_vb = &vpu_dev->common_mem; > + > + code_base = common_vb->daddr; > + /* ALIGN TO 4KB */ > + code_size = (WAVE5_MAX_CODE_BUF_SIZE & ~0xfff); > + if (code_size < size * 2) > + return -EINVAL; > + temp_base = common_vb->daddr + WAVE5_TEMPBUF_OFFSET; > + temp_size = WAVE5_TEMPBUF_SIZE; > + > + old_code_base = vpu_read_reg(vpu_dev, W5_VPU_REMAP_PADDR); > + > + if (old_code_base != code_base + W5_REMAP_INDEX1 * W5_REMAP_MAX_SIZE) { Put the contents of this branch into another function maybe? if (old_code_base != code_base + W5_REMAP_INDEX1 * W5_REMAP_MAX_SIZE) { ret = do_that_vpu_init_flow(things); if (ret) return ret; } return setup_wave5_properties(dev); }; Alternatively, invert the conditional and use a goto, but I personally don't really like using gotos unless it's *totally* necessary. > + int ret; > + struct dma_vpu_buf *sram_vb; > + > + ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size, > + VDI_128BIT_LITTLE_ENDIAN); > + if (ret < 0) { > + dev_err(vpu_dev->dev, > + "VPU init, Writing firmware to common buffer, fail: %d\n", ret); > + return ret; > + } > + > + vpu_write_reg(vpu_dev, W5_PO_CONF, 0); > + > + ret = wave5_vpu_reset(dev, SW_RESET_ON_BOOT); > + if (ret < 0) { > + dev_err(vpu_dev->dev, "VPU init, Resetting the VPU, fail: %d\n", ret); > + return ret; > + } > + > + remap_page(vpu_dev, code_base, W5_REMAP_INDEX0); > + remap_page(vpu_dev, code_base, W5_REMAP_INDEX1); > + > + vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base); > + vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size); > + vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0); > + vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base); > + vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size); > + > + vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); > + > + reg_val = (WAVE5_PROC_AXI_EXT_ADDR & 0xFFFF); > + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, reg_val); > + reg_val = ((WAVE5_PROC_AXI_AXPROT & 0x7) << 4) | > + (WAVE5_PROC_AXI_AXCACHE & 0xF); > + wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, reg_val); > + reg_val = ((WAVE5_SEC_AXI_AXPROT & 0x7) << 20) | > + ((WAVE5_SEC_AXI_AXCACHE & 0xF) << 16) | > + (WAVE5_SEC_AXI_EXT_ADDR & 0xFFFF); > + vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, reg_val); > + > + /* interrupt */ > + // encoder > + reg_val = BIT(INT_WAVE5_ENC_SET_PARAM); > + reg_val |= BIT(INT_WAVE5_ENC_PIC); > + reg_val |= BIT(INT_WAVE5_BSBUF_FULL); > + // decoder > + reg_val |= BIT(INT_WAVE5_INIT_SEQ); > + reg_val |= BIT(INT_WAVE5_DEC_PIC); > + reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); > + vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); > + > + reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); > + if ((reg_val >> 16) & 1) { > + reg_val = ((WAVE5_PROC_AXI_ID << 28) | > + (WAVE5_PRP_AXI_ID << 24) | > + (WAVE5_FBD_Y_AXI_ID << 20) | > + (WAVE5_FBC_Y_AXI_ID << 16) | > + (WAVE5_FBD_C_AXI_ID << 12) | > + (WAVE5_FBC_C_AXI_ID << 8) | > + (WAVE5_PRI_AXI_ID << 4) | > + WAVE5_SEC_AXI_ID); > + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); > + } > + > + sram_vb = &vpu_dev->sram_buf; > + > + vpu_write_reg(vpu_dev, W5_ADDR_SEC_AXI, sram_vb->daddr); > + vpu_write_reg(vpu_dev, W5_SEC_AXI_SIZE, sram_vb->size); > + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); > + vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU); > + vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); > + > + ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); > + if (ret) { > + dev_err(vpu_dev->dev, "VPU reinit(W5_VPU_REMAP_CORE_START) timeout\n"); > + return ret; > + } > + > + reg_val = vpu_read_reg(vpu_dev, W5_RET_SUCCESS); > + if (!reg_val) { > + u32 reason_code = vpu_read_reg(vpu_dev, W5_RET_FAIL_REASON); > + > + wave5_print_reg_err(vpu_dev, reason_code); > + return -EIO; > + } > + } > + > + return setup_wave5_properties(dev); > +} > + ..snip.. > + > +int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode) > +{ > + u32 val = 0; > + int ret = 0; > + struct vpu_device *vpu_dev = dev_get_drvdata(dev); > + struct vpu_attr *p_attr = &vpu_dev->attr; > + // VPU doesn't send response. force to set BUSY flag to 0. > + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 0); > + > + if (reset_mode == SW_RESET_SAFETY) { > + ret = wave5_vpu_sleep_wake(dev, true, NULL, 0); > + if (ret) > + return ret; > + } > + > + val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); > + if ((val >> 16) & 0x1) > + p_attr->support_backbone = true; bitfield macros ftw. > + if ((val >> 22) & 0x1) > + p_attr->support_vcore_backbone = true; > + if ((val >> 28) & 0x1) > + p_attr->support_vcpu_backbone = true; > + > + val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG1); > + if ((val >> 26) & 0x1) > + p_attr->support_dual_core = true; > + ..snip.. > +static void wave5_set_enc_crop_info(u32 codec, struct enc_wave_param *param, int rot_mode, > + int src_width, int src_height) > +{ > + int aligned_width = (codec == W_HEVC_ENC) ? ALIGN(src_width, 32) : ALIGN(src_width, 16); > + int aligned_height = (codec == W_HEVC_ENC) ? ALIGN(src_height, 32) : ALIGN(src_height, 16); > + int pad_right, pad_bot; > + int crop_right, crop_left, crop_top, crop_bot; > + int prp_mode = rot_mode >> 1; // remove prp_enable bit > + > + if (codec == W_HEVC_ENC && > + (!rot_mode || prp_mode == 14)) // prp_mode 14 : hor_mir && ver_mir && rot_180 > + return; > + > + pad_right = aligned_width - src_width; > + pad_bot = aligned_height - src_height; > + > + if (param->conf_win_right > 0) > + crop_right = param->conf_win_right + pad_right; > + else > + crop_right = pad_right; > + > + if (param->conf_win_bot > 0) > + crop_bot = param->conf_win_bot + pad_bot; > + else > + crop_bot = pad_bot; > + > + crop_top = param->conf_win_top; > + crop_left = param->conf_win_left; > + > + param->conf_win_top = crop_top; > + param->conf_win_left = crop_left; > + param->conf_win_bot = crop_bot; > + param->conf_win_right = crop_right; > + > + if (prp_mode == 1 || prp_mode == 15) { #define PRP_MODE_SOMETHING 1 #define PRP_MODE_SOMETHING_ELSE 2 or use an enumeration... otherwise it's not really understandable... > + param->conf_win_top = crop_right; > + param->conf_win_left = crop_top; > + param->conf_win_bot = crop_left; > + param->conf_win_right = crop_bot; > + } else if (prp_mode == 2 || prp_mode == 12) { > + param->conf_win_top = crop_bot; > + param->conf_win_left = crop_right; > + param->conf_win_bot = crop_top; > + param->conf_win_right = crop_left; > + } else if (prp_mode == 3 || prp_mode == 13) { > + param->conf_win_top = crop_left; > + param->conf_win_left = crop_bot; > + param->conf_win_bot = crop_right; > + param->conf_win_right = crop_top; > + } else if (prp_mode == 4 || prp_mode == 10) { > + param->conf_win_top = crop_bot; > + param->conf_win_bot = crop_top; > + } else if (prp_mode == 8 || prp_mode == 6) { > + param->conf_win_left = crop_right; > + param->conf_win_right = crop_left; > + } else if (prp_mode == 5 || prp_mode == 11) { > + param->conf_win_top = crop_left; > + param->conf_win_left = crop_top; > + param->conf_win_bot = crop_right; > + param->conf_win_right = crop_bot; > + } else if (prp_mode == 7 || prp_mode == 9) { > + param->conf_win_top = crop_right; > + param->conf_win_left = crop_bot; > + param->conf_win_bot = crop_left; > + param->conf_win_right = crop_top; > + } > +} > + > +int wave5_vpu_enc_init_seq(struct vpu_instance *inst) > +{ > + u32 reg_val = 0, rot_mir_mode, fixed_cu_size_mode = 0x7; > + struct enc_info *p_enc_info = &inst->codec_info->enc_info; > + struct enc_open_param *p_open_param = &p_enc_info->open_param; > + struct enc_wave_param *p_param = &p_open_param->wave_param; > + int ret; > + > + if (inst->dev->product != PRODUCT_ID_521) > + return -EINVAL; > + > + /*==============================================*/ > + /* OPT_CUSTOM_GOP */ > + /*==============================================*/ Comments like these are usually like /* * OPT_CUSTOM_GOP * * SET_PARAM + CUSTOM_GOP * only when... blah */ > + /* > + * SET_PARAM + CUSTOM_GOP > + * only when gop_preset_idx == custom_gop, custom_gop related registers should be set > + */ ..snip.. > +} > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h > new file mode 100644 > index 000000000000..1b3ffb737925 > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h > @@ -0,0 +1,1136 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ > +/* > + * Wave5 series multi-standard codec IP - helper definitions > + * > + * Copyright (C) 2021 CHIPS&MEDIA INC > + */ > + > +#ifndef VPUAPI_H_INCLUDED > +#define VPUAPI_H_INCLUDED > + > +#include <linux/kfifo.h> > +#include <linux/idr.h> > +#include <media/v4l2-device.h> > +#include <media/v4l2-mem2mem.h> > +#include <media/v4l2-ctrls.h> > +#include "wave5-vpuerror.h" > +#include "wave5-vpuconfig.h" > +#include "wave5-vdi.h" > + > +enum product_id { > + PRODUCT_ID_521, > + PRODUCT_ID_511, > + PRODUCT_ID_517, > + PRODUCT_ID_NONE, > +}; > + > +struct vpu_attr; > + > +enum vpu_instance_type { > + VPU_INST_TYPE_DEC = 0, The default for the first enum entry is always zero, and the next one will always be 1, 2, 3, 4..... .....so you don't need to assign any number. > + VPU_INST_TYPE_ENC = 1 > +}; > + > +enum vpu_instance_state { > + VPU_INST_STATE_NONE = 0, > + VPU_INST_STATE_OPEN = 1, > + VPU_INST_STATE_INIT_SEQ = 2, > + VPU_INST_STATE_PIC_RUN = 3, > + VPU_INST_STATE_STOP = 4 ditto > +}; > + > +#define WAVE5_MAX_FBS 32 > + > +#define MAX_REG_FRAME (WAVE5_MAX_FBS * 2) > + > +#define WAVE5_DEC_HEVC_BUF_SIZE(_w, _h) (DIV_ROUND_UP(_w, 64) * DIV_ROUND_UP(_h, 64) * 256 + 64) > +#define WAVE5_DEC_AVC_BUF_SIZE(_w, _h) ((((ALIGN(_w, 256) / 16) * (ALIGN(_h, 16) / 16)) + 16) * 80) > +#define WAVE5_DEC_VP9_BUF_SIZE(_w, _h) (((ALIGN(_w, 64) * ALIGN(_h, 64)) >> 2)) > +#define WAVE5_DEC_AVS2_BUF_SIZE(_w, _h) (((ALIGN(_w, 64) * ALIGN(_h, 64)) >> 5)) > +// AV1 BUF SIZE : MFMV + segment ID + CDF probs table + film grain param Y+ film graim param C > +#define WAVE5_DEC_AV1_BUF_SZ_1(_w, _h) \ > + (((ALIGN(_w, 64) / 64) * (ALIGN(_h, 64) / 64) * 512) + 41984 + 8192 + 4864) > +#define WAVE5_DEC_AV1_BUF_SZ_2(_w1, _w2, _h) \ > + (((ALIGN(_w1, 64) / 64) * 256 + (ALIGN(_w2, 256) / 64) * 128) * (ALIGN(_h, 64) / 64)) > + > +#define WAVE5_FBC_LUMA_TABLE_SIZE(_w, _h) (ALIGN(_h, 64) * ALIGN(_w, 256) / 32) > +#define WAVE5_FBC_CHROMA_TABLE_SIZE(_w, _h) (ALIGN((_h), 64) * ALIGN((_w) / 2, 256) / 32) > +#define WAVE5_ENC_AVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) * ALIGN(_h, 64) / 32) > +#define WAVE5_ENC_HEVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) / 64 * ALIGN(_h, 64) / 64 * 128) > + > +/* > + * common struct and definition > + */ > +enum cod_std { > + STD_AVC = 0, > + STD_VC1 = 1, > + STD_MPEG2 = 2, > + STD_MPEG4 = 3, > + STD_H263 = 4, > + STD_DIV3 = 5, > + STD_RV = 6, > + STD_AVS = 7, and same here, so that becomes ..... STD_AVS, STD_RESERVED, STD_THO, > + STD_THO = 9 > + STD_VP3 = 10, > + STD_VP8 = 11, > + STD_HEVC = 12, > + STD_VP9 = 13, > + STD_AVS2 = 14, STD_RESERVED2, (which will be 15)... > + STD_AV1 = 16, > + STD_MAX > +}; > + > +enum wave_std { > + W_HEVC_DEC = 0x00, > + W_HEVC_ENC = 0x01, > + W_AVC_DEC = 0x02, > + W_AVC_ENC = 0x03, > + W_VP9_DEC = 0x16, > + W_AVS2_DEC = 0x18, > + W_AV1_DEC = 0x1A, > + STD_UNKNOWN = 0xFF > +}; > + > +enum SET_PARAM_OPTION { Lowercase names for enums please. > + OPT_COMMON = 0, /* SET_PARAM command option for encoding sequence */ > + OPT_CUSTOM_GOP = 1, /* SET_PARAM command option for setting custom GOP */ > + OPT_CUSTOM_HEADER = 2, /* SET_PARAM command option for setting custom VPS/SPS/PPS */ > + OPT_VUI = 3, /* SET_PARAM command option for encoding VUI */ > + OPT_CHANGE_PARAM = 0x10, > +}; > + > +enum DEC_PIC_HDR_OPTION { > + INIT_SEQ_NORMAL = 0x01, > + INIT_SEQ_W_THUMBNAIL = 0x11, > +}; > + > +enum DEC_PIC_OPTION { > + DEC_PIC_NORMAL = 0x00, /* it is normal mode of DEC_PIC command */ > + DEC_PIC_W_THUMBNAIL = 0x10, /* thumbnail mode (skip non-IRAP without reference reg) */ > + SKIP_NON_IRAP = 0x11, /* it skips to decode non-IRAP pictures */ > + SKIP_NON_REF_PIC = 0x13 > +}; > + There's probably more, but starting with that is surely something :-) Regards, Angelo ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v11 2/6] media: chips-media: wave5: Add vpuapi layer 2022-12-07 13:05 ` AngeloGioacchino Del Regno @ 2022-12-15 13:31 ` Sebastian Fricke 0 siblings, 0 replies; 22+ messages in thread From: Sebastian Fricke @ 2022-12-15 13:31 UTC (permalink / raw) To: AngeloGioacchino Del Regno Cc: linux-media, Nas Chung, Robert Beckett, Mauro Carvalho Chehab, kernel, hverkuil-cisco, nicolas.dufresne, linux-kernel Hey Angelo, thanks a lot for your extensive review. See my notes and questions below. On 07.12.2022 14:05, AngeloGioacchino Del Regno wrote: >Il 07/12/22 13:13, Sebastian Fricke ha scritto: >>From: Nas Chung <nas.chung@chipsnmedia.com> >> >>Add the vpuapi layer of the wave5 codec driver. >>This layer is used to configure the hardware according >>to the parameters. >> >>Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> >>Signed-off-by: Robert Beckett <bob.beckett@collabora.com> >>Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> >>Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com> >>--- >> .../platform/chips-media/wave5/wave5-hw.c | 3359 +++++++++++++++++ >> .../chips-media/wave5/wave5-regdefine.h | 743 ++++ >> .../platform/chips-media/wave5/wave5-vdi.c | 245 ++ >> .../platform/chips-media/wave5/wave5-vdi.h | 67 + >> .../platform/chips-media/wave5/wave5-vpuapi.c | 1040 +++++ >> .../platform/chips-media/wave5/wave5-vpuapi.h | 1136 ++++++ >> .../chips-media/wave5/wave5-vpuconfig.h | 90 + >> .../chips-media/wave5/wave5-vpuerror.h | 454 +++ >> .../media/platform/chips-media/wave5/wave5.h | 94 + >> 9 files changed, 7228 insertions(+) >> create mode 100644 drivers/media/platform/chips-media/wave5/wave5-hw.c >> create mode 100644 drivers/media/platform/chips-media/wave5/wave5-regdefine.h >> create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vdi.c >> create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vdi.h >> create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpuapi.c >> create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpuapi.h >> create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h >> create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpuerror.h >> create mode 100644 drivers/media/platform/chips-media/wave5/wave5.h >> >>diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c >>new file mode 100644 >>index 000000000000..25705e61cdb3 >>--- /dev/null >>+++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c >>@@ -0,0 +1,3359 @@ >>+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) >>+/* >>+ * Wave5 series multi-standard codec IP - wave5 backend logic >>+ * >>+ * Copyright (C) 2021 CHIPS&MEDIA INC >>+ */ >>+ >>+#include <linux/iopoll.h> >>+#include "wave5-vpu.h" >>+#include "wave5.h" >>+#include "wave5-regdefine.h" >>+ >>+#define FIO_TIMEOUT 10000000 > >FIO_TIMEOUT_US looks better :-) Agreed. > >>+#define FIO_CTRL_READY BIT(31) >>+#define FIO_CTRL_WRITE BIT(16) >>+#define VPU_BUSY_CHECK_TIMEOUT 10000000 >>+#define QUEUE_REPORT_MASK 0xffff >>+ >>+static void wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason) >>+{ >>+ char *caller = __builtin_return_address(0); >>+ struct device *dev = vpu_dev->dev; >>+ u32 reg_val; >>+ >>+ switch (reg_fail_reason) { >>+ case WAVE5_SYSERR_QUEUEING_FAIL: >>+ reg_val = vpu_read_reg(vpu_dev, W5_RET_QUEUE_FAIL_REASON); >>+ dev_dbg(dev, "%s: queueing failure: 0x%x\n", caller, reg_val); >>+ break; >>+ case WAVE5_SYSERR_RESULT_NOT_READY: >>+ dev_err(dev, "%s: result not ready: 0x%x\n", caller, reg_fail_reason); >>+ break; >>+ case WAVE5_SYSERR_ACCESS_VIOLATION_HW: >>+ dev_err(dev, "%s: access violation: 0x%x\n", caller, reg_fail_reason); >>+ break; >>+ case WAVE5_SYSERR_WATCHDOG_TIMEOUT: >>+ dev_err(dev, "%s: watchdog timeout: 0x%x\n", caller, reg_fail_reason); >>+ break; >>+ case WAVE5_SYSERR_BUS_ERROR: >>+ dev_err(dev, "%s: bus error: 0x%x\n", caller, reg_fail_reason); >>+ break; >>+ case WAVE5_SYSERR_DOUBLE_FAULT: >>+ dev_err(dev, "%s: double fault: 0x%x\n", caller, reg_fail_reason); >>+ break; >>+ case WAVE5_SYSERR_VPU_STILL_RUNNING: >>+ dev_err(dev, "%s: still running: 0x%x\n", caller, reg_fail_reason); >>+ break; >>+ case WAVE5_SYSERR_VLC_BUF_FULL: >>+ dev_err(dev, "%s: vlc buf full: 0x%x\n", caller, reg_fail_reason); >>+ break; >>+ default: >>+ dev_err(dev, "%s: failure:: 0x%x\n", caller, reg_fail_reason); >>+ break; >>+ } >>+} >>+ >>+static int wave5_wait_fio_readl(struct vpu_device *vpu_dev, u32 addr, u32 val) >>+{ >>+ u32 ctrl; >>+ int ret; >>+ >>+ ctrl = addr & 0xffff; >>+ wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl); >>+ ret = read_poll_timeout(wave5_vdi_readl, ctrl, ctrl & FIO_CTRL_READY, >>+ 0, FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR); >>+ if (ret) >>+ return ret; >>+ if (wave5_vdi_readl(vpu_dev, W5_VPU_FIO_DATA) != val) >>+ return -ETIMEDOUT; > >Are you sure that this is a timeout? >if (read_data != expected_data) => invalid data => return -EINVAL ? Hmm so if we take this use-case: ``` wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7); ret = wave5_wait_bus_busy(vpu_dev, W5_BACKBONE_BUS_STATUS_VCORE0); if (ret) { ``` We try to set the ctrl for the core and we expect the hardware to set the correct status value. If we don't get that status value doesn't that indicate a timeout? >>+ return 0; >>+} >>+ > >..snip.. > >>+ >>+static int wave5_wait_bus_busy(struct vpu_device *vpu_dev, unsigned int addr) >>+{ >>+ u32 gdi_status_check_value = 0x3f; >>+ >>+ if (vpu_dev->product_code == WAVE521C_CODE || >>+ vpu_dev->product_code == WAVE521_CODE || >>+ vpu_dev->product_code == WAVE521E1_CODE) >>+ gdi_status_check_value = 0x00ff1f3f; > >#define SOME_VALUE 0x3f >#define ANOTHER_VALUE 0xff1f3f Yep makes sense. > >>+ >>+ return wave5_wait_fio_readl(vpu_dev, addr, gdi_status_check_value); >>+} >>+ > >..snip.. > >>+ >>+static int setup_wave5_properties(struct device *dev) >>+{ >>+ struct vpu_device *vpu_dev = dev_get_drvdata(dev); >>+ struct vpu_attr *p_attr = &vpu_dev->attr; >>+ u32 reg_val; >>+ u8 *str; >>+ int ret; >>+ u32 hw_config_def0, hw_config_def1, hw_config_feature, hw_config_rev; >>+ >>+ vpu_write_reg(vpu_dev, W5_QUERY_OPTION, GET_VPU_INFO); >>+ vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); >>+ vpu_write_reg(vpu_dev, W5_COMMAND, W5_QUERY); >>+ vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); >>+ ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); >>+ if (ret) >>+ return ret; >>+ >>+ if (!vpu_read_reg(vpu_dev, W5_RET_SUCCESS)) >>+ return -EIO; >>+ >>+ reg_val = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_NAME); >>+ str = (u8 *)®_val; >>+ p_attr->product_name[0] = str[3]; >>+ p_attr->product_name[1] = str[2]; >>+ p_attr->product_name[2] = str[1]; >>+ p_attr->product_name[3] = str[0]; >>+ p_attr->product_name[4] = 0; >>+ >>+ p_attr->product_id = wave5_vpu_get_product_id(vpu_dev); >>+ p_attr->product_version = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_VERSION); >>+ p_attr->fw_version = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); >>+ p_attr->customer_id = vpu_read_reg(vpu_dev, W5_RET_CUSTOMER_ID); >>+ hw_config_def0 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF0); >>+ hw_config_def1 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF1); >>+ hw_config_feature = vpu_read_reg(vpu_dev, W5_RET_CONF_FEATURE); >>+ hw_config_rev = vpu_read_reg(vpu_dev, W5_RET_CONF_REVISION); >>+ >>+ p_attr->support_hevc10bit_enc = (hw_config_feature >> 3) & 1; > >This looks like being BIT(3), and the latter is BIT(11)... > >#define W5_CONF_FEATURE_HEVC10_ENC BIT(3) >#define W5_CONF_FEATURE_AVC10_ENC BIT(11) > >p_attr->support_hevc10bit_enc = FIELD_GET(W5_CONF_FEATURE_HEVC10_ENC, >hw_config_feature); > >if (hw_config_rev > W5_REVISION_SOMETHING) > p_attr->support_avc10bit_enc = FIELD_GET(W5_CONF_FEATURE_AVC10_ENC, > hw_config_feature); >else > p_attr->support_avc10bit_enc = p_attr->support_hevc10bit_enc; Yep that looks way better. > > >>+ if (hw_config_rev > 167455) //20190321 >>+ p_attr->support_avc10bit_enc = (hw_config_feature >> 11) & 1; >>+ else >>+ p_attr->support_avc10bit_enc = p_attr->support_hevc10bit_enc; >>+ >>+ p_attr->support_decoders = 0; >>+ p_attr->support_encoders = 0; >>+ if (p_attr->product_id == PRODUCT_ID_521) { >>+ p_attr->support_dual_core = ((hw_config_def1 >> 26) & 0x01); > >p_attr->support_dual_core = FIELD_GET(W5_CONF_DEF_HW_DUAL_CORE, hw_config_def1); > >....and there are others below, but I think I gave enough examples... :-) Yup implemented. > >>+ if (p_attr->support_dual_core || hw_config_rev < 206116) { >>+ p_attr->support_decoders = BIT(STD_AVC); >>+ p_attr->support_decoders |= BIT(STD_HEVC); >>+ p_attr->support_encoders = BIT(STD_AVC); >>+ p_attr->support_encoders |= BIT(STD_HEVC); >>+ } else { >>+ p_attr->support_decoders |= (((hw_config_def1 >> 3) & 0x01) << STD_AVC); >>+ p_attr->support_decoders |= (((hw_config_def1 >> 2) & 0x01) << STD_HEVC); >>+ p_attr->support_encoders = (((hw_config_def1 >> 1) & 0x01) << STD_AVC); >>+ p_attr->support_encoders |= ((hw_config_def1 & 0x01) << STD_HEVC); >>+ } >>+ } else if (p_attr->product_id == PRODUCT_ID_511) { >>+ p_attr->support_decoders = BIT(STD_HEVC); >>+ p_attr->support_decoders |= BIT(STD_AVC); >>+ } else if (p_attr->product_id == PRODUCT_ID_517) { >>+ p_attr->support_decoders = (((hw_config_def1 >> 4) & 0x01) << STD_AV1); >>+ p_attr->support_decoders |= (((hw_config_def1 >> 3) & 0x01) << STD_AVS2); >>+ p_attr->support_decoders |= (((hw_config_def1 >> 2) & 0x01) << STD_AVC); >>+ p_attr->support_decoders |= (((hw_config_def1 >> 1) & 0x01) << STD_VP9); >>+ p_attr->support_decoders |= ((hw_config_def1 & 0x01) << STD_HEVC); >>+ } >>+ >>+ p_attr->support_backbone = (hw_config_def0 >> 16) & 0x01; >>+ p_attr->support_vcpu_backbone = (hw_config_def0 >> 28) & 0x01; >>+ p_attr->support_vcore_backbone = (hw_config_def0 >> 22) & 0x01; >>+ p_attr->support_dual_core = (hw_config_def1 >> 26) & 0x01; >>+ p_attr->support_endian_mask = BIT(VDI_LITTLE_ENDIAN) | >>+ BIT(VDI_BIG_ENDIAN) | >>+ BIT(VDI_32BIT_LITTLE_ENDIAN) | >>+ BIT(VDI_32BIT_BIG_ENDIAN) | >>+ (0xffffUL << 16); >>+ p_attr->support_bitstream_mode = BIT(BS_MODE_INTERRUPT) | >>+ BIT(BS_MODE_PIC_END); >>+ >>+ return 0; >>+} >>+ >>+int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision) >>+{ >>+ u32 reg_val; >>+ int ret; >>+ >>+ vpu_write_reg(vpu_dev, W5_QUERY_OPTION, GET_VPU_INFO); >>+ vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); >>+ vpu_write_reg(vpu_dev, W5_COMMAND, W5_QUERY); >>+ vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); >>+ ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); >>+ if (ret) { >>+ dev_err(vpu_dev->dev, "%s: timeout\n", __func__); >>+ return ret; >>+ } >>+ >>+ if (!vpu_read_reg(vpu_dev, W5_RET_SUCCESS)) { >>+ dev_err(vpu_dev->dev, "%s: failed\n", __func__); >>+ return -EIO; >>+ } >>+ >>+ reg_val = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); >>+ if (revision) > >Move the revision pointer null check at the beginning and return an error >if that happens to be null: it doesn't make a lot of sense to read many >registers before the check as the whole point of this function is to get >the version and return it to that variable. True, I just return at beginning now like: if (!revision) return 0; > > >>+ *revision = reg_val; >>+ >>+ return 0; >>+} >>+ >>+static void remap_page(struct vpu_device *vpu_dev, dma_addr_t code_base, u32 index) >>+{ >>+ u32 remap_size = (W5_REMAP_MAX_SIZE >> 12) & 0x1ff; >>+ u32 reg_val = 0x80000000 | (WAVE5_UPPER_PROC_AXI_ID << 20) | (index << 12) | BIT(11) >>+ | remap_size; >>+ >>+ vpu_write_reg(vpu_dev, W5_VPU_REMAP_CTRL, reg_val); >>+ vpu_write_reg(vpu_dev, W5_VPU_REMAP_VADDR, index * W5_REMAP_MAX_SIZE); >>+ vpu_write_reg(vpu_dev, W5_VPU_REMAP_PADDR, code_base + index * W5_REMAP_MAX_SIZE); >>+} >>+ > >..snip.. > >>+ >>+int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, >>+ struct dec_open_param *param) >>+{ >>+ int ret; >>+ struct dec_info *p_dec_info = &inst->codec_info->dec_info; >>+ u32 bs_endian; >>+ struct dma_vpu_buf *sram_vb; >>+ struct vpu_device *vpu_dev = inst->dev; >>+ >>+ p_dec_info->cycle_per_tick = 256; >>+ switch (inst->std) { >>+ case W_HEVC_DEC: >>+ p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_HEVC; >>+ break; >>+ case W_VP9_DEC: >>+ p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_VP9; >>+ break; >>+ case W_AVS2_DEC: >>+ p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVS2; >>+ break; >>+ case W_AVC_DEC: >>+ p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVC; >>+ break; >>+ case W_AV1_DEC: >>+ p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AV1; >>+ break; >>+ default: >>+ return -EINVAL; >>+ } >>+ >>+ if (vpu_dev->product == PRODUCT_ID_517) > >Another switch would be good here. Check. > >>+ p_dec_info->vb_work.size = WAVE517_WORKBUF_SIZE; >>+ else if (vpu_dev->product == PRODUCT_ID_521) >>+ p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; >>+ else if (vpu_dev->product == PRODUCT_ID_511) >>+ p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; >>+ >>+ ret = wave5_vdi_allocate_dma_memory(inst->dev, &p_dec_info->vb_work); >>+ if (ret) >>+ return ret; >>+ >>+ vpu_write_reg(inst->dev, W5_CMD_DEC_VCORE_INFO, 1); >>+ >>+ sram_vb = &vpu_dev->sram_buf; >>+ p_dec_info->sec_axi_info.buf_base = sram_vb->daddr; >>+ p_dec_info->sec_axi_info.buf_size = sram_vb->size; >>+ >>+ wave5_vdi_clear_memory(inst->dev, &p_dec_info->vb_work); >>+ >>+ vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_dec_info->vb_work.daddr); >>+ vpu_write_reg(inst->dev, W5_WORK_SIZE, p_dec_info->vb_work.size); >>+ >>+ vpu_write_reg(inst->dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info->stream_buf_start_addr); >>+ vpu_write_reg(inst->dev, W5_CMD_DEC_BS_SIZE, p_dec_info->stream_buf_size); >>+ >>+ /* NOTE: when endian mode is 0, SDMA reads MSB first */ >>+ bs_endian = wave5_vdi_convert_endian(inst->dev, param->stream_endian); >>+ bs_endian = (~bs_endian & VDI_128BIT_ENDIAN_MASK); >>+ vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, bs_endian); >>+ vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, (param->pri_axprot << 20) | >>+ (param->pri_axcache << 16) | param->pri_ext_addr); >>+ vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, (COMMAND_QUEUE_DEPTH - 1)); >>+ vpu_write_reg(inst->dev, W5_CMD_ERR_CONCEAL, (param->error_conceal_unit << 2) | >>+ (param->error_conceal_mode)); >>+ >>+ wave5_bit_issue_command(inst, W5_CREATE_INSTANCE); >>+ // check QUEUE_DONE > >Please be consistent in comments format. Use C-style comments. > >>+ ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); >>+ if (ret) { >>+ dev_warn(inst->dev->dev, "command: 'W5_CREATE_INSTANCE' timed out\n"); >>+ goto free_vb_work; >>+ } >>+ >>+ // Check if we were able to add the parameters into the VCPU QUEUE >>+ if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { >>+ ret = -EIO; >>+ goto free_vb_work; >>+ } >>+ >>+ p_dec_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); >>+ >>+ return 0; >>+free_vb_work: >>+ wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); >>+ return ret; >>+} >>+ > >..snip.. > >>+ >>+static void wave5_get_dec_seq_result(struct vpu_instance *inst, struct dec_initial_info *info) >>+{ >>+ u32 reg_val, sub_layer_info; >>+ u32 profile_compatibility_flag; >>+ u32 output_bit_depth_minus8; >>+ struct dec_info *p_dec_info = &inst->codec_info->dec_info; >>+ >>+ p_dec_info->stream_rd_ptr = wave5_vpu_dec_get_rd_ptr(inst); >>+ info->rd_ptr = p_dec_info->stream_rd_ptr; >>+ >>+ p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); >>+ >>+ reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); >>+ info->pic_width = ((reg_val >> 16) & 0xffff); >>+ info->pic_height = (reg_val & 0xffff); >>+ info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REQUIRED_FB); >>+ info->frame_buf_delay = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REORDER_DELAY); >>+ >>+ reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_LEFT_RIGHT); >>+ info->pic_crop_rect.left = (reg_val >> 16) & 0xffff; >>+ info->pic_crop_rect.right = reg_val & 0xffff; >>+ reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_TOP_BOTTOM); >>+ info->pic_crop_rect.top = (reg_val >> 16) & 0xffff; >>+ info->pic_crop_rect.bottom = reg_val & 0xffff; >>+ >>+ info->f_rate_numerator = vpu_read_reg(inst->dev, W5_RET_DEC_FRAME_RATE_NR); >>+ info->f_rate_denominator = vpu_read_reg(inst->dev, W5_RET_DEC_FRAME_RATE_DR); >>+ >>+ reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_COLOR_SAMPLE_INFO); >>+ info->luma_bitdepth = reg_val & 0xf; >>+ info->chroma_bitdepth = (reg_val >> 4) & 0xf; >>+ info->chroma_format_idc = (reg_val >> 8) & 0xf; >>+ info->aspect_rate_info = (reg_val >> 16) & 0xff; > >Bitfield macros would make this way more readable. Thanks, I have adjusted this pattern throughout the whole file. > >>+ info->is_ext_sar = ((info->aspect_rate_info == 255) ? true : false); >>+ /* [0:15] - vertical size, [16:31] - horizontal size */ >>+ if (info->is_ext_sar) >>+ info->aspect_rate_info = vpu_read_reg(inst->dev, W5_RET_DEC_ASPECT_RATIO); >>+ info->bit_rate = vpu_read_reg(inst->dev, W5_RET_DEC_BIT_RATE); >>+ >>+ sub_layer_info = vpu_read_reg(inst->dev, W5_RET_DEC_SUB_LAYER_INFO); >>+ info->max_temporal_layers = (sub_layer_info >> 8) & 0x7; >>+ >>+ reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_SEQ_PARAM); >>+ info->level = reg_val & 0xff; >>+ profile_compatibility_flag = (reg_val >> 12) & 0xff; >>+ info->profile = (reg_val >> 24) & 0x1f; >>+ info->tier = (reg_val >> 29) & 0x01; >>+ output_bit_depth_minus8 = (reg_val >> 30) & 0x03; >>+ >>+ if (inst->std == W_HEVC_DEC) { >>+ /* guessing profile */ >>+ if (!info->profile) { >>+ if ((profile_compatibility_flag & 0x06) == 0x06) >>+ info->profile = HEVC_PROFILE_MAIN; /* main profile */ > >main/main10 profile comments are stating the obvious, please remove them. Done. > >>+ else if ((profile_compatibility_flag & 0x04) == 0x04) >>+ info->profile = HEVC_PROFILE_MAIN10; /* main10 profile */ >>+ else if ((profile_compatibility_flag & 0x08) == 0x08) >>+ /* main still picture profile */ >>+ info->profile = HEVC_PROFILE_STILLPICTURE; >>+ else >>+ info->profile = HEVC_PROFILE_MAIN; /* for old version HM */ >>+ } >>+ >>+ } else if (inst->std == W_AVS2_DEC) { >>+ if (info->luma_bitdepth == 10 && output_bit_depth_minus8 == 2) >>+ info->output_bit_depth = 10; >>+ else >>+ info->output_bit_depth = 8; >>+ >>+ } else if (inst->std == W_AVC_DEC) { >>+ info->profile = (reg_val >> 24) & 0x7f; >>+ } >>+ >>+ info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); >>+ info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); >>+ p_dec_info->vlc_buf_size = info->vlc_buf_size; >>+ p_dec_info->param_buf_size = info->param_buf_size; >>+} >>+ > >..snip.. > >>+ >>+static u32 calculate_table_size(u32 bit_depth, u32 frame_width, u32 frame_height, u32 ot_bg_width) >>+{ >>+ u32 bgs_width = ((bit_depth > 8) ? 256 : 512); >>+ u32 comp_frame_width = ALIGN(ALIGN(frame_width, 16) + 16, 16); >>+ u32 ot_frame_width = ALIGN(comp_frame_width, ot_bg_width); >>+ >>+ // sizeof_offset_table() >>+ u32 ot_bg_height = 32; >>+ u32 bgs_height = BIT(14) / bgs_width / ((bit_depth > 8) ? 2 : 1); > >Please, no magic BIT(x) usage: add a definition for that bit. > >>+ u32 comp_frame_height = ALIGN(ALIGN(frame_height, 4) + 4, bgs_height); >>+ u32 ot_frame_height = ALIGN(comp_frame_height, ot_bg_height); >>+ >>+ return (ot_frame_width / 16) * (ot_frame_height / 4) * 2; >>+} >>+ > >..snip.. > >>+ >>+int wave5_vpu_decode(struct vpu_instance *inst, struct dec_param *option, u32 *fail_res) >>+{ >>+ u32 mode_option = DEC_PIC_NORMAL, bs_option, reg_val; >>+ u32 force_latency = 0; >>+ struct dec_info *p_dec_info = &inst->codec_info->dec_info; >>+ struct dec_open_param *p_open_param = &p_dec_info->open_param; >>+ int ret; >>+ > >switch (option->skipframe_mode) { >case ... >... >default: > break; >}; Hmm this changes the logic, because we would only look at this if we don't have the thumbnail mode. With this change we always check the skipframe mode no matter the thumbnail mode. > >if (p_dec_info->thumbnail_mode) { > mode_option = DEC_PIC_W_THUMBNAIL; > if (mode_option != DEC_PIC_NORMAL) > ... do something: as I read the code, this is not a supported case. How can this happen? It is initialized to DEC_PIC_NORMAL. So, if we don't have the thumbnail or skipframe mode flags then we are PIC_NORMAL anyway. Or am I missing something? >} > >^^^^ this should improve the flow. > >>+ if (p_dec_info->thumbnail_mode) { >>+ mode_option = DEC_PIC_W_THUMBNAIL; >>+ } else if (option->skipframe_mode) { >>+ switch (option->skipframe_mode) { >>+ case WAVE_SKIPMODE_NON_IRAP: >>+ mode_option = SKIP_NON_IRAP; >>+ force_latency = 1; >>+ break; >>+ case WAVE_SKIPMODE_NON_REF: >>+ mode_option = SKIP_NON_REF_PIC; >>+ break; >>+ default: >>+ // skip mode off >>+ break; >>+ } >>+ } >>+ >>+ // set disable reorder >>+ if (!p_dec_info->reorder_enable) >>+ force_latency = 1; >>+ >>+ /* set attributes of bitstream buffer controller */ >>+ bs_option = 0; > >You don't have to initialize this variable at all, as you're either writing twice >or failing. True, I actually fixed that in another place before but didn't check for other occurences :S > >>+ switch (p_open_param->bitstream_mode) { >>+ case BS_MODE_INTERRUPT: >>+ bs_option = BSOPTION_ENABLE_EXPLICIT_END; >>+ break; >>+ case BS_MODE_PIC_END: >>+ bs_option = BSOPTION_ENABLE_EXPLICIT_END; >>+ break; >>+ default: >>+ return -EINVAL; >>+ } >>+ > >..snip.. > >>+ >>+int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) >>+{ >>+ struct vpu_buf *common_vb; >>+ dma_addr_t code_base, temp_base; >>+ dma_addr_t old_code_base, temp_size; >>+ u32 code_size; >>+ u32 reg_val; >>+ struct vpu_device *vpu_dev = dev_get_drvdata(dev); >>+ >>+ common_vb = &vpu_dev->common_mem; >>+ >>+ code_base = common_vb->daddr; >>+ /* ALIGN TO 4KB */ >>+ code_size = (WAVE5_MAX_CODE_BUF_SIZE & ~0xfff); >>+ if (code_size < size * 2) >>+ return -EINVAL; >>+ temp_base = common_vb->daddr + WAVE5_TEMPBUF_OFFSET; >>+ temp_size = WAVE5_TEMPBUF_SIZE; >>+ >>+ old_code_base = vpu_read_reg(vpu_dev, W5_VPU_REMAP_PADDR); >>+ >>+ if (old_code_base != code_base + W5_REMAP_INDEX1 * W5_REMAP_MAX_SIZE) { > >Put the contents of this branch into another function maybe? > > if (old_code_base != code_base + W5_REMAP_INDEX1 * W5_REMAP_MAX_SIZE) { > ret = do_that_vpu_init_flow(things); > if (ret) > return ret; > } > > > return setup_wave5_properties(dev); >}; > >Alternatively, invert the conditional and use a goto, but I personally don't >really like using gotos unless it's *totally* necessary. I have added a new function `wave5_vpu_init_helper`, which implements the common path of both `wave5_vpu_init` and `wave5_vpu_re_init`. > >>+ int ret; >>+ struct dma_vpu_buf *sram_vb; >>+ >>+ ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size, >>+ VDI_128BIT_LITTLE_ENDIAN); >>+ if (ret < 0) { >>+ dev_err(vpu_dev->dev, >>+ "VPU init, Writing firmware to common buffer, fail: %d\n", ret); >>+ return ret; >>+ } >>+ >>+ vpu_write_reg(vpu_dev, W5_PO_CONF, 0); >>+ >>+ ret = wave5_vpu_reset(dev, SW_RESET_ON_BOOT); >>+ if (ret < 0) { >>+ dev_err(vpu_dev->dev, "VPU init, Resetting the VPU, fail: %d\n", ret); >>+ return ret; >>+ } >>+ >>+ remap_page(vpu_dev, code_base, W5_REMAP_INDEX0); >>+ remap_page(vpu_dev, code_base, W5_REMAP_INDEX1); >>+ >>+ vpu_write_reg(vpu_dev, W5_ADDR_CODE_BASE, code_base); >>+ vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size); >>+ vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0); >>+ vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base); >>+ vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size); >>+ >>+ vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); >>+ >>+ reg_val = (WAVE5_PROC_AXI_EXT_ADDR & 0xFFFF); >>+ wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, reg_val); >>+ reg_val = ((WAVE5_PROC_AXI_AXPROT & 0x7) << 4) | >>+ (WAVE5_PROC_AXI_AXCACHE & 0xF); >>+ wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, reg_val); >>+ reg_val = ((WAVE5_SEC_AXI_AXPROT & 0x7) << 20) | >>+ ((WAVE5_SEC_AXI_AXCACHE & 0xF) << 16) | >>+ (WAVE5_SEC_AXI_EXT_ADDR & 0xFFFF); >>+ vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, reg_val); >>+ >>+ /* interrupt */ >>+ // encoder >>+ reg_val = BIT(INT_WAVE5_ENC_SET_PARAM); >>+ reg_val |= BIT(INT_WAVE5_ENC_PIC); >>+ reg_val |= BIT(INT_WAVE5_BSBUF_FULL); >>+ // decoder >>+ reg_val |= BIT(INT_WAVE5_INIT_SEQ); >>+ reg_val |= BIT(INT_WAVE5_DEC_PIC); >>+ reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); >>+ vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); >>+ >>+ reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); >>+ if ((reg_val >> 16) & 1) { >>+ reg_val = ((WAVE5_PROC_AXI_ID << 28) | >>+ (WAVE5_PRP_AXI_ID << 24) | >>+ (WAVE5_FBD_Y_AXI_ID << 20) | >>+ (WAVE5_FBC_Y_AXI_ID << 16) | >>+ (WAVE5_FBD_C_AXI_ID << 12) | >>+ (WAVE5_FBC_C_AXI_ID << 8) | >>+ (WAVE5_PRI_AXI_ID << 4) | >>+ WAVE5_SEC_AXI_ID); >>+ wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); >>+ } >>+ >>+ sram_vb = &vpu_dev->sram_buf; >>+ >>+ vpu_write_reg(vpu_dev, W5_ADDR_SEC_AXI, sram_vb->daddr); >>+ vpu_write_reg(vpu_dev, W5_SEC_AXI_SIZE, sram_vb->size); >>+ vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); >>+ vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU); >>+ vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); >>+ >>+ ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); >>+ if (ret) { >>+ dev_err(vpu_dev->dev, "VPU reinit(W5_VPU_REMAP_CORE_START) timeout\n"); >>+ return ret; >>+ } >>+ >>+ reg_val = vpu_read_reg(vpu_dev, W5_RET_SUCCESS); >>+ if (!reg_val) { >>+ u32 reason_code = vpu_read_reg(vpu_dev, W5_RET_FAIL_REASON); >>+ >>+ wave5_print_reg_err(vpu_dev, reason_code); >>+ return -EIO; >>+ } >>+ } >>+ >>+ return setup_wave5_properties(dev); >>+} >>+ > >..snip.. > >>+ >>+int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode) >>+{ >>+ u32 val = 0; >>+ int ret = 0; >>+ struct vpu_device *vpu_dev = dev_get_drvdata(dev); >>+ struct vpu_attr *p_attr = &vpu_dev->attr; >>+ // VPU doesn't send response. force to set BUSY flag to 0. >>+ vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 0); >>+ >>+ if (reset_mode == SW_RESET_SAFETY) { >>+ ret = wave5_vpu_sleep_wake(dev, true, NULL, 0); >>+ if (ret) >>+ return ret; >>+ } >>+ >>+ val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); >>+ if ((val >> 16) & 0x1) >>+ p_attr->support_backbone = true; > >bitfield macros ftw. Check. > >>+ if ((val >> 22) & 0x1) >>+ p_attr->support_vcore_backbone = true; >>+ if ((val >> 28) & 0x1) >>+ p_attr->support_vcpu_backbone = true; >>+ >>+ val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG1); >>+ if ((val >> 26) & 0x1) >>+ p_attr->support_dual_core = true; >>+ > > >..snip.. > >>+static void wave5_set_enc_crop_info(u32 codec, struct enc_wave_param *param, int rot_mode, >>+ int src_width, int src_height) >>+{ >>+ int aligned_width = (codec == W_HEVC_ENC) ? ALIGN(src_width, 32) : ALIGN(src_width, 16); >>+ int aligned_height = (codec == W_HEVC_ENC) ? ALIGN(src_height, 32) : ALIGN(src_height, 16); >>+ int pad_right, pad_bot; >>+ int crop_right, crop_left, crop_top, crop_bot; >>+ int prp_mode = rot_mode >> 1; // remove prp_enable bit >>+ >>+ if (codec == W_HEVC_ENC && >>+ (!rot_mode || prp_mode == 14)) // prp_mode 14 : hor_mir && ver_mir && rot_180 >>+ return; >>+ >>+ pad_right = aligned_width - src_width; >>+ pad_bot = aligned_height - src_height; >>+ >>+ if (param->conf_win_right > 0) >>+ crop_right = param->conf_win_right + pad_right; >>+ else >>+ crop_right = pad_right; >>+ >>+ if (param->conf_win_bot > 0) >>+ crop_bot = param->conf_win_bot + pad_bot; >>+ else >>+ crop_bot = pad_bot; >>+ >>+ crop_top = param->conf_win_top; >>+ crop_left = param->conf_win_left; >>+ >>+ param->conf_win_top = crop_top; >>+ param->conf_win_left = crop_left; >>+ param->conf_win_bot = crop_bot; >>+ param->conf_win_right = crop_right; >>+ >>+ if (prp_mode == 1 || prp_mode == 15) { > >#define PRP_MODE_SOMETHING 1 >#define PRP_MODE_SOMETHING_ELSE 2 > >or use an enumeration... otherwise it's not really understandable... Alright so how about this, I looked at the different rotations + the comment above apparently, 0x1 => 90 degree counter clock wise rotation, 0x2 => 180 degree clock wise rotation, 0x4 => vertical mirror and 0x8 => horizontal mirror. And the different modes are simply connections of those. So the new code now looks like this: ``` if (prp_mode == CCW_90 || prp_mode == (CCW_90 | CW_180 | VER_MIR | HOR_MIR)) { param->conf_win_top = crop_right; param->conf_win_left = crop_top; param->conf_win_bot = crop_left; param->conf_win_right = crop_bot; } else if (prp_mode == CW_180 || prp_mode == (VER_MIR | HOR_MIR)) { param->conf_win_top = crop_bot; param->conf_win_left = crop_right; param->conf_win_bot = crop_top; param->conf_win_right = crop_left; } else if (prp_mode == (CCW_90 | CW_180) || prp_mode == (CCW_90 | VER_MIR | HOR_MIR)) { param->conf_win_top = crop_left; param->conf_win_left = crop_bot; param->conf_win_bot = crop_right; param->conf_win_right = crop_top; } else if (prp_mode == VER_MIR || prp_mode == (HOR_MIR | CW_180)) { param->conf_win_top = crop_bot; param->conf_win_bot = crop_top; } else if (prp_mode == HOR_MIR || prp_mode == (CW_180 | VER_MIR)) { param->conf_win_left = crop_right; param->conf_win_right = crop_left; } else if (prp_mode == (CCW_90 | VER_MIR) || prp_mode == (CCW_90 | CW_180 | HOR_MIR)) { param->conf_win_top = crop_left; param->conf_win_left = crop_top; param->conf_win_bot = crop_right; param->conf_win_right = crop_bot; } else if (prp_mode == (CCW_90 | CW_180 | VER_MIR) || prp_mode == (CCW_90 | HOR_MIR)) { param->conf_win_top = crop_right; param->conf_win_left = crop_bot; param->conf_win_bot = crop_left; param->conf_win_right = crop_top; } ``` Clear enough? > >>+ param->conf_win_top = crop_right; >>+ param->conf_win_left = crop_top; >>+ param->conf_win_bot = crop_left; >>+ param->conf_win_right = crop_bot; >>+ } else if (prp_mode == 2 || prp_mode == 12) { >>+ param->conf_win_top = crop_bot; >>+ param->conf_win_left = crop_right; >>+ param->conf_win_bot = crop_top; >>+ param->conf_win_right = crop_left; >>+ } else if (prp_mode == 3 || prp_mode == 13) { >>+ param->conf_win_top = crop_left; >>+ param->conf_win_left = crop_bot; >>+ param->conf_win_bot = crop_right; >>+ param->conf_win_right = crop_top; >>+ } else if (prp_mode == 4 || prp_mode == 10) { >>+ param->conf_win_top = crop_bot; >>+ param->conf_win_bot = crop_top; >>+ } else if (prp_mode == 8 || prp_mode == 6) { >>+ param->conf_win_left = crop_right; >>+ param->conf_win_right = crop_left; >>+ } else if (prp_mode == 5 || prp_mode == 11) { >>+ param->conf_win_top = crop_left; >>+ param->conf_win_left = crop_top; >>+ param->conf_win_bot = crop_right; >>+ param->conf_win_right = crop_bot; >>+ } else if (prp_mode == 7 || prp_mode == 9) { >>+ param->conf_win_top = crop_right; >>+ param->conf_win_left = crop_bot; >>+ param->conf_win_bot = crop_left; >>+ param->conf_win_right = crop_top; >>+ } >>+} >>+ >>+int wave5_vpu_enc_init_seq(struct vpu_instance *inst) >>+{ >>+ u32 reg_val = 0, rot_mir_mode, fixed_cu_size_mode = 0x7; >>+ struct enc_info *p_enc_info = &inst->codec_info->enc_info; >>+ struct enc_open_param *p_open_param = &p_enc_info->open_param; >>+ struct enc_wave_param *p_param = &p_open_param->wave_param; >>+ int ret; >>+ >>+ if (inst->dev->product != PRODUCT_ID_521) >>+ return -EINVAL; >>+ >>+ /*==============================================*/ >>+ /* OPT_CUSTOM_GOP */ >>+ /*==============================================*/ > >Comments like these are usually like > > /* > * OPT_CUSTOM_GOP > * > * SET_PARAM + CUSTOM_GOP > * only when... blah > */ Done. > >>+ /* >>+ * SET_PARAM + CUSTOM_GOP >>+ * only when gop_preset_idx == custom_gop, custom_gop related registers should be set >>+ */ > >..snip.. > >>+} >>diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h >>new file mode 100644 >>index 000000000000..1b3ffb737925 >>--- /dev/null >>+++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h >>@@ -0,0 +1,1136 @@ >>+/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ >>+/* >>+ * Wave5 series multi-standard codec IP - helper definitions >>+ * >>+ * Copyright (C) 2021 CHIPS&MEDIA INC >>+ */ >>+ >>+#ifndef VPUAPI_H_INCLUDED >>+#define VPUAPI_H_INCLUDED >>+ >>+#include <linux/kfifo.h> >>+#include <linux/idr.h> >>+#include <media/v4l2-device.h> >>+#include <media/v4l2-mem2mem.h> >>+#include <media/v4l2-ctrls.h> >>+#include "wave5-vpuerror.h" >>+#include "wave5-vpuconfig.h" >>+#include "wave5-vdi.h" >>+ >>+enum product_id { >>+ PRODUCT_ID_521, >>+ PRODUCT_ID_511, >>+ PRODUCT_ID_517, >>+ PRODUCT_ID_NONE, >>+}; >>+ >>+struct vpu_attr; >>+ >>+enum vpu_instance_type { >>+ VPU_INST_TYPE_DEC = 0, > >The default for the first enum entry is always zero, and the next one will always >be 1, 2, 3, 4..... > >.....so you don't need to assign any number. Check. > >>+ VPU_INST_TYPE_ENC = 1 >>+}; >>+ >>+enum vpu_instance_state { >>+ VPU_INST_STATE_NONE = 0, >>+ VPU_INST_STATE_OPEN = 1, >>+ VPU_INST_STATE_INIT_SEQ = 2, >>+ VPU_INST_STATE_PIC_RUN = 3, >>+ VPU_INST_STATE_STOP = 4 > >ditto > >>+}; >>+ >>+#define WAVE5_MAX_FBS 32 >>+ >>+#define MAX_REG_FRAME (WAVE5_MAX_FBS * 2) >>+ >>+#define WAVE5_DEC_HEVC_BUF_SIZE(_w, _h) (DIV_ROUND_UP(_w, 64) * DIV_ROUND_UP(_h, 64) * 256 + 64) >>+#define WAVE5_DEC_AVC_BUF_SIZE(_w, _h) ((((ALIGN(_w, 256) / 16) * (ALIGN(_h, 16) / 16)) + 16) * 80) >>+#define WAVE5_DEC_VP9_BUF_SIZE(_w, _h) (((ALIGN(_w, 64) * ALIGN(_h, 64)) >> 2)) >>+#define WAVE5_DEC_AVS2_BUF_SIZE(_w, _h) (((ALIGN(_w, 64) * ALIGN(_h, 64)) >> 5)) >>+// AV1 BUF SIZE : MFMV + segment ID + CDF probs table + film grain param Y+ film graim param C >>+#define WAVE5_DEC_AV1_BUF_SZ_1(_w, _h) \ >>+ (((ALIGN(_w, 64) / 64) * (ALIGN(_h, 64) / 64) * 512) + 41984 + 8192 + 4864) >>+#define WAVE5_DEC_AV1_BUF_SZ_2(_w1, _w2, _h) \ >>+ (((ALIGN(_w1, 64) / 64) * 256 + (ALIGN(_w2, 256) / 64) * 128) * (ALIGN(_h, 64) / 64)) >>+ >>+#define WAVE5_FBC_LUMA_TABLE_SIZE(_w, _h) (ALIGN(_h, 64) * ALIGN(_w, 256) / 32) >>+#define WAVE5_FBC_CHROMA_TABLE_SIZE(_w, _h) (ALIGN((_h), 64) * ALIGN((_w) / 2, 256) / 32) >>+#define WAVE5_ENC_AVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) * ALIGN(_h, 64) / 32) >>+#define WAVE5_ENC_HEVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) / 64 * ALIGN(_h, 64) / 64 * 128) >>+ >>+/* >>+ * common struct and definition >>+ */ >>+enum cod_std { >>+ STD_AVC = 0, >>+ STD_VC1 = 1, >>+ STD_MPEG2 = 2, >>+ STD_MPEG4 = 3, >>+ STD_H263 = 4, >>+ STD_DIV3 = 5, >>+ STD_RV = 6, >>+ STD_AVS = 7, > >and same here, so that becomes > > ..... > STD_AVS, > STD_RESERVED, > STD_THO, > > >>+ STD_THO = 9 > + STD_VP3 = 10, >>+ STD_VP8 = 11, >>+ STD_HEVC = 12, >>+ STD_VP9 = 13, >>+ STD_AVS2 = 14, > >STD_RESERVED2, (which will be 15)... Good point didn't think about that. > >>+ STD_AV1 = 16, >>+ STD_MAX >>+}; >>+ >>+enum wave_std { >>+ W_HEVC_DEC = 0x00, >>+ W_HEVC_ENC = 0x01, >>+ W_AVC_DEC = 0x02, >>+ W_AVC_ENC = 0x03, >>+ W_VP9_DEC = 0x16, >>+ W_AVS2_DEC = 0x18, >>+ W_AV1_DEC = 0x1A, >>+ STD_UNKNOWN = 0xFF >>+}; >>+ >>+enum SET_PARAM_OPTION { > >Lowercase names for enums please. Check. > >>+ OPT_COMMON = 0, /* SET_PARAM command option for encoding sequence */ >>+ OPT_CUSTOM_GOP = 1, /* SET_PARAM command option for setting custom GOP */ >>+ OPT_CUSTOM_HEADER = 2, /* SET_PARAM command option for setting custom VPS/SPS/PPS */ >>+ OPT_VUI = 3, /* SET_PARAM command option for encoding VUI */ >>+ OPT_CHANGE_PARAM = 0x10, >>+}; >>+ >>+enum DEC_PIC_HDR_OPTION { >>+ INIT_SEQ_NORMAL = 0x01, >>+ INIT_SEQ_W_THUMBNAIL = 0x11, >>+}; >>+ >>+enum DEC_PIC_OPTION { >>+ DEC_PIC_NORMAL = 0x00, /* it is normal mode of DEC_PIC command */ >>+ DEC_PIC_W_THUMBNAIL = 0x10, /* thumbnail mode (skip non-IRAP without reference reg) */ >>+ SKIP_NON_IRAP = 0x11, /* it skips to decode non-IRAP pictures */ >>+ SKIP_NON_REF_PIC = 0x13 >>+}; >>+ > > >There's probably more, but starting with that is surely something :-) > > >Regards, >Angelo Thanks a lot. Sincerly, Sebastian ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v11 3/6] media: chips-media: wave5: Add the v4l2 layer [not found] <20221207121350.66217-1-sebastian.fricke@collabora.com> 2022-12-07 12:13 ` [PATCH v11 1/6] media: platform: chips-media: Move Coda to separate folder Sebastian Fricke 2022-12-07 12:13 ` [PATCH v11 2/6] media: chips-media: wave5: Add vpuapi layer Sebastian Fricke @ 2022-12-07 12:13 ` Sebastian Fricke 2022-12-12 14:19 ` Hans Verkuil 2023-04-26 14:44 ` Nicolas Dufresne 2022-12-07 12:13 ` [PATCH v11 4/6] media: chips-media: wave5: Add TODO file Sebastian Fricke ` (2 subsequent siblings) 5 siblings, 2 replies; 22+ messages in thread From: Sebastian Fricke @ 2022-12-07 12:13 UTC (permalink / raw) To: linux-media, Mauro Carvalho Chehab, Nas Chung, Robert Beckett, Sebastian Fricke Cc: kernel, hverkuil-cisco, nicolas.dufresne, linux-kernel From: Nas Chung <nas.chung@chipsnmedia.com> Add the decoder and encoder implementing the v4l2 API. This patch also adds the Makefile and the VIDEO_WAVE_VPU config Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com> --- drivers/media/platform/chips-media/Kconfig | 1 + drivers/media/platform/chips-media/Makefile | 1 + .../media/platform/chips-media/wave5/Kconfig | 12 + .../media/platform/chips-media/wave5/Makefile | 10 + .../platform/chips-media/wave5/wave5-helper.c | 175 ++ .../platform/chips-media/wave5/wave5-helper.h | 28 + .../chips-media/wave5/wave5-vpu-dec.c | 1429 ++++++++++++++ .../chips-media/wave5/wave5-vpu-enc.c | 1746 +++++++++++++++++ .../platform/chips-media/wave5/wave5-vpu.c | 362 ++++ .../platform/chips-media/wave5/wave5-vpu.h | 72 + 10 files changed, 3836 insertions(+) create mode 100644 drivers/media/platform/chips-media/wave5/Kconfig create mode 100644 drivers/media/platform/chips-media/wave5/Makefile create mode 100644 drivers/media/platform/chips-media/wave5/wave5-helper.c create mode 100644 drivers/media/platform/chips-media/wave5/wave5-helper.h create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu.c create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu.h diff --git a/drivers/media/platform/chips-media/Kconfig b/drivers/media/platform/chips-media/Kconfig index f87a0d693df7..ad350eb6b1fc 100644 --- a/drivers/media/platform/chips-media/Kconfig +++ b/drivers/media/platform/chips-media/Kconfig @@ -3,3 +3,4 @@ comment "Chips&Media media platform drivers" source "drivers/media/platform/chips-media/coda/Kconfig" +source "drivers/media/platform/chips-media/wave5/Kconfig" diff --git a/drivers/media/platform/chips-media/Makefile b/drivers/media/platform/chips-media/Makefile index 5ee693f651c1..6b5d99de8b54 100644 --- a/drivers/media/platform/chips-media/Makefile +++ b/drivers/media/platform/chips-media/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y += coda/ +obj-y += wave5/ diff --git a/drivers/media/platform/chips-media/wave5/Kconfig b/drivers/media/platform/chips-media/wave5/Kconfig new file mode 100644 index 000000000000..a3b949356cd5 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0 +config VIDEO_WAVE_VPU + tristate "Chips&Media Wave Codec Driver" + depends on VIDEO_DEV + select VIDEOBUF2_DMA_CONTIG + select VIDEOBUF2_VMALLOC + select V4L2_MEM2MEM_DEV + help + Chips&Media stateful encoder and decoder driver. + The driver supports HEVC and H264 formats. + To compile this driver as modules, choose M here: the + modules will be called wave5. diff --git a/drivers/media/platform/chips-media/wave5/Makefile b/drivers/media/platform/chips-media/wave5/Makefile new file mode 100644 index 000000000000..3d738a03bd8e --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_VIDEO_WAVE_VPU) += wave5.o +wave5-objs += wave5-hw.o \ + wave5-vpuapi.o \ + wave5-vdi.o \ + wave5-vpu-dec.o \ + wave5-vpu.o \ + wave5-vpu-enc.o \ + wave5-helper.o diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.c b/drivers/media/platform/chips-media/wave5/wave5-helper.c new file mode 100644 index 000000000000..2851f3f0b580 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Wave5 series multi-standard codec IP - decoder interface + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#include "wave5-helper.h" + +void wave5_cleanup_instance(struct vpu_instance *inst) +{ + int i; + + for (i = 0; i < inst->dst_buf_count; i++) + wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[i]); + + wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf); + v4l2_ctrl_handler_free(&inst->v4l2_ctrl_hdl); + if (inst->v4l2_m2m_dev != NULL) + v4l2_m2m_release(inst->v4l2_m2m_dev); + if (inst->v4l2_fh.vdev != NULL) { + v4l2_fh_del(&inst->v4l2_fh); + v4l2_fh_exit(&inst->v4l2_fh); + } + list_del_init(&inst->list); + kfifo_free(&inst->irq_status); + ida_free(&inst->dev->inst_ida, inst->id); + kfree(inst); +} + +int wave5_vpu_release_device(struct file *filp, + int (*close_func)(struct vpu_instance *inst, u32 *fail_res), + char *name) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(filp->private_data); + + v4l2_m2m_ctx_release(inst->v4l2_fh.m2m_ctx); + if (inst->state != VPU_INST_STATE_NONE) { + u32 fail_res; + int retry_count = 10; + int ret; + + do { + fail_res = 0; + ret = close_func(inst, &fail_res); + if (ret && ret != -EIO) + break; + if (fail_res != WAVE5_SYSERR_VPU_STILL_RUNNING) + break; + if (!wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT)) + break; + } while (--retry_count); + + if (fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING) { + dev_err(inst->dev->dev, "%s close failed, device is still running\n", + name); + return -EBUSY; + } + if (ret && ret != -EIO) { + dev_err(inst->dev->dev, "%s close, fail: %d\n", name, ret); + return ret; + } + } + + wave5_cleanup_instance(inst); + + return 0; +} + +int wave5_vpu_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq, + const struct vb2_ops *ops) +{ + struct vpu_instance *inst = priv; + int ret; + + src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; + src_vq->io_modes = VB2_MMAP | VB2_DMABUF; + src_vq->mem_ops = &vb2_dma_contig_memops; + src_vq->ops = ops; + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->buf_struct_size = sizeof(struct vpu_buffer); + src_vq->drv_priv = inst; + src_vq->lock = &inst->dev->dev_lock; + src_vq->dev = inst->dev->v4l2_dev.dev; + ret = vb2_queue_init(src_vq); + if (ret) + return ret; + + dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; + dst_vq->mem_ops = &vb2_dma_contig_memops; + dst_vq->ops = ops; + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->buf_struct_size = sizeof(struct vpu_buffer); + dst_vq->drv_priv = inst; + dst_vq->lock = &inst->dev->dev_lock; + dst_vq->dev = inst->dev->v4l2_dev.dev; + ret = vb2_queue_init(dst_vq); + if (ret) + return ret; + + return 0; +} + +int wave5_vpu_subscribe_event(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + bool is_decoder = inst->type == VPU_INST_TYPE_DEC; + + dev_dbg(inst->dev->dev, "%s: [%s] type: %u id: %u | flags: %u\n", __func__, + is_decoder ? "decoder" : "encoder", sub->type, sub->id, sub->flags); + + switch (sub->type) { + case V4L2_EVENT_EOS: + return v4l2_event_subscribe(fh, sub, 0, NULL); + case V4L2_EVENT_SOURCE_CHANGE: + if (is_decoder) + return v4l2_src_change_event_subscribe(fh, sub); + return -EINVAL; + case V4L2_EVENT_CTRL: + return v4l2_ctrl_subscribe_event(fh, sub); + default: + return -EINVAL; + } +} + +int wave5_vpu_g_fmt_out(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + int i; + + f->fmt.pix_mp.width = inst->src_fmt.width; + f->fmt.pix_mp.height = inst->src_fmt.height; + f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; + f->fmt.pix_mp.field = inst->src_fmt.field; + f->fmt.pix_mp.flags = inst->src_fmt.flags; + f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { + f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->src_fmt.plane_fmt[i].bytesperline; + f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->src_fmt.plane_fmt[i].sizeimage; + } + + f->fmt.pix_mp.colorspace = inst->colorspace; + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; + f->fmt.pix_mp.quantization = inst->quantization; + f->fmt.pix_mp.xfer_func = inst->xfer_func; + + return 0; +} + +const struct vpu_format *wave5_find_vpu_fmt(unsigned int v4l2_pix_fmt, + const struct vpu_format fmt_list[MAX_FMTS]) +{ + unsigned int index; + + for (index = 0; index < MAX_FMTS; index++) { + if (fmt_list[index].v4l2_pix_fmt == v4l2_pix_fmt) + return &fmt_list[index]; + } + + return NULL; +} + +const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx, + const struct vpu_format fmt_list[MAX_FMTS]) +{ + if (idx >= MAX_FMTS) + return NULL; + + if (!fmt_list[idx].v4l2_pix_fmt) + return NULL; + + return &fmt_list[idx]; +} diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.h b/drivers/media/platform/chips-media/wave5/wave5-helper.h new file mode 100644 index 000000000000..d586d624275e --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * Wave5 series multi-standard codec IP - basic types + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#ifndef __WAVE_HELPER_H__ +#define __WAVE_HELPER_H__ + +#include "wave5-vpu.h" + +#define FMT_TYPES 2 +#define MAX_FMTS 6 + +void wave5_cleanup_instance(struct vpu_instance *inst); +int wave5_vpu_release_device(struct file *filp, + int (*close_func)(struct vpu_instance *inst, u32 *fail_res), + char *name); +int wave5_vpu_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq, + const struct vb2_ops *ops); +int wave5_vpu_subscribe_event(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub); +int wave5_vpu_g_fmt_out(struct file *file, void *fh, struct v4l2_format *f); +const struct vpu_format *wave5_find_vpu_fmt(unsigned int v4l2_pix_fmt, + const struct vpu_format fmt_list[MAX_FMTS]); +const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx, + const struct vpu_format fmt_list[MAX_FMTS]); +#endif diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c new file mode 100644 index 000000000000..f32118d59fb8 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c @@ -0,0 +1,1429 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Wave5 series multi-standard codec IP - decoder interface + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#include "wave5-helper.h" + +#define VPU_DEC_DEV_NAME "C&M Wave5 VPU decoder" +#define VPU_DEC_DRV_NAME "wave5-dec" +#define V4L2_CID_VPU_THUMBNAIL_MODE (V4L2_CID_USER_BASE + 0x1001) + +static const struct vpu_format dec_fmt_list[FMT_TYPES][MAX_FMTS] = { + [VPU_FMT_TYPE_CODEC] = { + { + .v4l2_pix_fmt = V4L2_PIX_FMT_HEVC, + .max_width = 8192, + .min_width = 8, + .max_height = 4320, + .min_height = 8, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_H264, + .max_width = 8192, + .min_width = 32, + .max_height = 4320, + .min_height = 32, + }, + }, + [VPU_FMT_TYPE_RAW] = { + { + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420, + .max_width = 8192, + .min_width = 8, + .max_height = 4320, + .min_height = 8, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV12, + .max_width = 8192, + .min_width = 8, + .max_height = 4320, + .min_height = 8, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV21, + .max_width = 8192, + .min_width = 8, + .max_height = 4320, + .min_height = 8, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M, + .max_width = 8192, + .min_width = 8, + .max_height = 4320, + .min_height = 8, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV12M, + .max_width = 8192, + .min_width = 8, + .max_height = 4320, + .min_height = 8, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, + .max_width = 8192, + .min_width = 8, + .max_height = 4320, + .min_height = 8, + }, + } +}; + +static enum wave_std wave5_to_vpu_codstd(unsigned int v4l2_pix_fmt) +{ + switch (v4l2_pix_fmt) { + case V4L2_PIX_FMT_H264: + return W_AVC_DEC; + case V4L2_PIX_FMT_HEVC: + return W_HEVC_DEC; + default: + return STD_UNKNOWN; + } +} + +static void wave5_handle_bitstream_buffer(struct vpu_instance *inst) +{ + struct v4l2_m2m_buffer *buf, *n; + int ret; + + v4l2_m2m_for_each_src_buf_safe(inst->v4l2_fh.m2m_ctx, buf, n) { + struct vb2_v4l2_buffer *vbuf = &buf->vb; + struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); + size_t src_size = vb2_get_plane_payload(&vbuf->vb2_buf, 0); + void *src_buf = vb2_plane_vaddr(&vbuf->vb2_buf, 0); + dma_addr_t rd_ptr = 0; + dma_addr_t wr_ptr = 0; + size_t remain_size = 0; + size_t offset; + + if (vpu_buf->consumed) { + dev_dbg(inst->dev->dev, "already consumed src buf (%u)\n", + vbuf->vb2_buf.index); + continue; + } + + if (!src_buf) { + dev_dbg(inst->dev->dev, + "%s: Acquiring kernel pointer to src buf (%u), fail\n", + __func__, vbuf->vb2_buf.index); + break; + } + + ret = wave5_vpu_dec_get_bitstream_buffer(inst, &rd_ptr, &wr_ptr, &remain_size); + if (ret) { + dev_err(inst->dev->dev, "Getting the bitstream buffer, fail: %d\n", + ret); + return; + } + + if (remain_size < src_size) { + dev_dbg(inst->dev->dev, + "%s: remaining size: %zu < source size: %zu for src buf (%u)\n", + __func__, remain_size, src_size, vbuf->vb2_buf.index); + break; + } + + offset = wr_ptr - inst->bitstream_vbuf.daddr; + if (wr_ptr + src_size > inst->bitstream_vbuf.daddr + inst->bitstream_vbuf.size) { + size_t size; + + size = inst->bitstream_vbuf.daddr + inst->bitstream_vbuf.size - wr_ptr; + ret = wave5_vdi_write_memory(inst->dev, &inst->bitstream_vbuf, offset, + (u8 *)src_buf, size, VDI_128BIT_LITTLE_ENDIAN); + if (ret < 0) { + dev_dbg(inst->dev->dev, + "%s: 1/2 write src buf (%u) into bitstream buf, fail: %d\n", + __func__, vbuf->vb2_buf.index, ret); + break; + } + ret = wave5_vdi_write_memory(inst->dev, &inst->bitstream_vbuf, 0, + (u8 *)src_buf + size, src_size - size, + VDI_128BIT_LITTLE_ENDIAN); + if (ret < 0) { + dev_dbg(inst->dev->dev, + "%s: 2/2 write src buf (%u) into bitstream buf, fail: %d\n", + __func__, vbuf->vb2_buf.index, ret); + break; + } + } else { + ret = wave5_vdi_write_memory(inst->dev, &inst->bitstream_vbuf, offset, + (u8 *)src_buf, src_size, + VDI_128BIT_LITTLE_ENDIAN); + if (ret < 0) { + dev_dbg(inst->dev->dev, + "%s: write src buf (%u) into bitstream buf, fail: %d", + __func__, vbuf->vb2_buf.index, ret); + break; + } + } + + ret = wave5_vpu_dec_update_bitstream_buffer(inst, src_size); + if (ret) { + dev_dbg(inst->dev->dev, + "vpu_dec_update_bitstream_buffer fail: %d for src buf (%u)\n", + ret, vbuf->vb2_buf.index); + break; + } + + vpu_buf->consumed = true; + } +} + +static void wave5_handle_src_buffer(struct vpu_instance *inst) +{ + struct vb2_v4l2_buffer *src_buf; + + src_buf = v4l2_m2m_next_src_buf(inst->v4l2_fh.m2m_ctx); + if (src_buf) { + struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(src_buf); + + if (vpu_buf->consumed) { + dev_dbg(inst->dev->dev, "%s: already consumed buffer\n", __func__); + src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); + inst->timestamp = src_buf->vb2_buf.timestamp; + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); + } + } +} + +static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width, + unsigned int height) +{ + switch (pix_mp->pixelformat) { + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV21: + pix_mp->width = round_up(width, 32); + pix_mp->height = round_up(height, 16); + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); + pix_mp->plane_fmt[0].sizeimage = width * height * 3 / 2; + break; + case V4L2_PIX_FMT_YUV420M: + pix_mp->width = round_up(width, 32); + pix_mp->height = round_up(height, 16); + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); + pix_mp->plane_fmt[0].sizeimage = width * height; + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; + pix_mp->plane_fmt[1].sizeimage = width * height / 4; + pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; + pix_mp->plane_fmt[2].sizeimage = width * height / 4; + break; + case V4L2_PIX_FMT_NV12M: + case V4L2_PIX_FMT_NV21M: + pix_mp->width = round_up(width, 32); + pix_mp->height = round_up(height, 16); + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); + pix_mp->plane_fmt[0].sizeimage = width * height; + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); + pix_mp->plane_fmt[1].sizeimage = width * height / 2; + break; + default: + pix_mp->width = width; + pix_mp->height = height; + pix_mp->plane_fmt[0].bytesperline = 0; + pix_mp->plane_fmt[0].sizeimage = width * height; + break; + } +} + +static void wave5_vpu_dec_start_decode(struct vpu_instance *inst) +{ + struct dec_param pic_param; + int ret; + u32 fail_res = 0; + + memset(&pic_param, 0, sizeof(struct dec_param)); + + if (inst->state == VPU_INST_STATE_INIT_SEQ) { + u32 non_linear_num = inst->dst_buf_count; + u32 linear_num = inst->dst_buf_count; + u32 stride = inst->dst_fmt.width; + + ret = wave5_vpu_dec_register_frame_buffer_ex(inst, non_linear_num, linear_num, + stride, inst->dst_fmt.height, + COMPRESSED_FRAME_MAP); + if (ret) + dev_dbg(inst->dev->dev, "%s: vpu_dec_register_frame_buffer_ex fail: %d", + __func__, ret); + } + + ret = wave5_vpu_dec_start_one_frame(inst, &pic_param, &fail_res); + if (ret && fail_res != WAVE5_SYSERR_QUEUEING_FAIL) { + struct vb2_v4l2_buffer *src_buf; + + src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); + inst->state = VPU_INST_STATE_STOP; + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); + } +} + +static void wave5_vpu_dec_stop_decode(struct vpu_instance *inst) +{ + unsigned int i; + int ret; + + inst->state = VPU_INST_STATE_STOP; + + ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0); + if (ret) { + dev_warn(inst->dev->dev, + "Setting EOS for the bitstream, fail: %d\n", ret); + } + + for (i = 0; i < inst->dst_buf_count; i++) { + ret = wave5_vpu_dec_clr_disp_flag(inst, i); + if (ret) { + dev_dbg(inst->dev->dev, + "%s: Clearing the display flag of buffer index: %u, fail: %d\n", + __func__, i, ret); + } + } + + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); +} + +static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst) +{ + struct dec_output_info dec_output_info; + int ret; + u32 irq_status; + + if (kfifo_out(&inst->irq_status, &irq_status, sizeof(int))) + wave5_vpu_clear_interrupt_ex(inst, irq_status); + + ret = wave5_vpu_dec_get_output_info(inst, &dec_output_info); + if (ret) { + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); + return; + } + if (dec_output_info.index_frame_decoded == DECODED_IDX_FLAG_NO_FB && + dec_output_info.index_frame_display == DISPLAY_IDX_FLAG_NO_FB) { + dev_dbg(inst->dev->dev, "%s: no more frame buffer\n", __func__); + } else { + wave5_handle_src_buffer(inst); + + if (dec_output_info.index_frame_display >= 0) { + struct vb2_v4l2_buffer *dst_buf = + v4l2_m2m_dst_buf_remove_by_idx(inst->v4l2_fh.m2m_ctx, + dec_output_info.index_frame_display); + int stride = dec_output_info.disp_frame.stride; + int height = dec_output_info.disp_pic_height - + dec_output_info.rc_display.bottom; + + if (inst->dst_fmt.num_planes == 1) { + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, + (stride * height * 3 / 2)); + } else if (inst->dst_fmt.num_planes == 2) { + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, + (stride * height)); + vb2_set_plane_payload(&dst_buf->vb2_buf, 1, + ((stride / 2) * height)); + } else if (inst->dst_fmt.num_planes == 3) { + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, + (stride * height)); + vb2_set_plane_payload(&dst_buf->vb2_buf, 1, + ((stride / 2) * (height / 2))); + vb2_set_plane_payload(&dst_buf->vb2_buf, 2, + ((stride / 2) * (height / 2))); + } + + dst_buf->vb2_buf.timestamp = inst->timestamp; + dst_buf->field = V4L2_FIELD_NONE; + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); + + dev_dbg(inst->dev->dev, "%s: frame_cycle %8u\n", + __func__, dec_output_info.frame_cycle); + } else if (dec_output_info.index_frame_display == DISPLAY_IDX_FLAG_SEQ_END && + !inst->eos) { + static const struct v4l2_event vpu_event_eos = { + .type = V4L2_EVENT_EOS + }; + struct vb2_v4l2_buffer *dst_buf = + v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx); + + if (!dst_buf) + return; + + if (inst->dst_fmt.num_planes == 1) { + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, + vb2_plane_size(&dst_buf->vb2_buf, 0)); + } else if (inst->dst_fmt.num_planes == 2) { + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, + vb2_plane_size(&dst_buf->vb2_buf, 0)); + vb2_set_plane_payload(&dst_buf->vb2_buf, 1, + vb2_plane_size(&dst_buf->vb2_buf, 1)); + } else if (inst->dst_fmt.num_planes == 3) { + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, + vb2_plane_size(&dst_buf->vb2_buf, 0)); + vb2_set_plane_payload(&dst_buf->vb2_buf, 1, + vb2_plane_size(&dst_buf->vb2_buf, 1)); + vb2_set_plane_payload(&dst_buf->vb2_buf, 2, + vb2_plane_size(&dst_buf->vb2_buf, 2)); + } + + dst_buf->vb2_buf.timestamp = inst->timestamp; + dst_buf->flags |= V4L2_BUF_FLAG_LAST; + dst_buf->field = V4L2_FIELD_NONE; + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); + + inst->eos = TRUE; + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos); + + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); + } + } +} + +static int wave5_vpu_dec_querycap(struct file *file, void *fh, struct v4l2_capability *cap) +{ + strscpy(cap->driver, VPU_DEC_DRV_NAME, sizeof(cap->driver)); + strscpy(cap->card, VPU_DEC_DRV_NAME, sizeof(cap->card)); + strscpy(cap->bus_info, "platform:" VPU_DEC_DRV_NAME, sizeof(cap->bus_info)); + + return 0; +} + +static int wave5_vpu_dec_enum_framesizes(struct file *f, void *fh, struct v4l2_frmsizeenum *fsize) +{ + const struct vpu_format *vpu_fmt; + + if (fsize->index) + return -EINVAL; + + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, dec_fmt_list[VPU_FMT_TYPE_CODEC]); + if (!vpu_fmt) { + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, dec_fmt_list[VPU_FMT_TYPE_RAW]); + if (!vpu_fmt) + return -EINVAL; + } + + fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; + fsize->stepwise.min_width = vpu_fmt->min_width; + fsize->stepwise.max_width = vpu_fmt->max_width; + fsize->stepwise.step_width = 1; + fsize->stepwise.min_height = vpu_fmt->min_height; + fsize->stepwise.max_height = vpu_fmt->max_height; + fsize->stepwise.step_height = 1; + + return 0; +} + +static int wave5_vpu_dec_enum_fmt_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f) +{ + const struct vpu_format *vpu_fmt; + + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, dec_fmt_list[VPU_FMT_TYPE_RAW]); + if (!vpu_fmt) + return -EINVAL; + + f->pixelformat = vpu_fmt->v4l2_pix_fmt; + f->flags = 0; + + return 0; +} + +static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct vpu_format *vpu_fmt; + + dev_dbg(inst->dev->dev, + "%s: fourcc: %u width: %u height: %u nm planes: %u colorspace: %u field: %u\n", + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); + + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) + return -EINVAL; + + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_RAW]); + if (!vpu_fmt) { + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height); + } else { + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); + const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); + + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; + f->fmt.pix_mp.num_planes = info->mem_planes; + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); + } + + f->fmt.pix_mp.flags = 0; + f->fmt.pix_mp.field = V4L2_FIELD_NONE; + f->fmt.pix_mp.colorspace = inst->colorspace; + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; + f->fmt.pix_mp.quantization = inst->quantization; + f->fmt.pix_mp.xfer_func = inst->xfer_func; + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); + + return 0; +} + +static int wave5_vpu_dec_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + int i, ret; + + dev_dbg(inst->dev->dev, + "%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n", + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); + + ret = wave5_vpu_dec_try_fmt_cap(file, fh, f); + if (ret) + return ret; + + inst->dst_fmt.width = f->fmt.pix_mp.width; + inst->dst_fmt.height = f->fmt.pix_mp.height; + inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat; + inst->dst_fmt.field = f->fmt.pix_mp.field; + inst->dst_fmt.flags = f->fmt.pix_mp.flags; + inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes; + for (i = 0; i < inst->dst_fmt.num_planes; i++) { + inst->dst_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; + inst->dst_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; + } + + if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12 || + inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12M) { + inst->cbcr_interleave = true; + inst->nv21 = false; + } else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21 || + inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21M) { + inst->cbcr_interleave = true; + inst->nv21 = true; + } else { + inst->cbcr_interleave = false; + inst->nv21 = false; + } + + return 0; +} + +static int wave5_vpu_dec_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + int i; + + f->fmt.pix_mp.width = inst->dst_fmt.width; + f->fmt.pix_mp.height = inst->dst_fmt.height; + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; + f->fmt.pix_mp.field = inst->dst_fmt.field; + f->fmt.pix_mp.flags = inst->dst_fmt.flags; + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { + f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->dst_fmt.plane_fmt[i].bytesperline; + f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->dst_fmt.plane_fmt[i].sizeimage; + } + + f->fmt.pix_mp.colorspace = inst->colorspace; + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; + f->fmt.pix_mp.quantization = inst->quantization; + f->fmt.pix_mp.xfer_func = inst->xfer_func; + + return 0; +} + +static int wave5_vpu_dec_enum_fmt_out(struct file *file, void *fh, struct v4l2_fmtdesc *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct vpu_format *vpu_fmt; + + dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); + + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, dec_fmt_list[VPU_FMT_TYPE_CODEC]); + if (!vpu_fmt) + return -EINVAL; + + f->pixelformat = vpu_fmt->v4l2_pix_fmt; + f->flags = 0; + + return 0; +} + +static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct vpu_format *vpu_fmt; + + dev_dbg(inst->dev->dev, + "%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n", + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); + + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + return -EINVAL; + + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_CODEC]); + if (!vpu_fmt) { + f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; + f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height); + } else { + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); + + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; + f->fmt.pix_mp.num_planes = 1; + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); + } + + f->fmt.pix_mp.flags = 0; + f->fmt.pix_mp.field = V4L2_FIELD_NONE; + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); + + return 0; +} + +static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + int i, ret; + + dev_dbg(inst->dev->dev, + "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); + + ret = wave5_vpu_dec_try_fmt_out(file, fh, f); + if (ret) + return ret; + + inst->src_fmt.width = f->fmt.pix_mp.width; + inst->src_fmt.height = f->fmt.pix_mp.height; + inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat; + inst->src_fmt.field = f->fmt.pix_mp.field; + inst->src_fmt.flags = f->fmt.pix_mp.flags; + inst->src_fmt.num_planes = f->fmt.pix_mp.num_planes; + for (i = 0; i < inst->src_fmt.num_planes; i++) { + inst->src_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; + inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; + } + + inst->colorspace = f->fmt.pix_mp.colorspace; + inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; + inst->hsv_enc = f->fmt.pix_mp.hsv_enc; + inst->quantization = f->fmt.pix_mp.quantization; + inst->xfer_func = f->fmt.pix_mp.xfer_func; + + wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height); + + return 0; +} + +static int wave5_vpu_dec_g_selection(struct file *file, void *fh, struct v4l2_selection *s) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + + dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target); + + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + switch (s->target) { + case V4L2_SEL_TGT_COMPOSE_BOUNDS: + case V4L2_SEL_TGT_COMPOSE_PADDED: + s->r.left = 0; + s->r.top = 0; + s->r.width = inst->dst_fmt.width; + s->r.height = inst->dst_fmt.height; + break; + case V4L2_SEL_TGT_COMPOSE: + case V4L2_SEL_TGT_COMPOSE_DEFAULT: + s->r.left = 0; + s->r.top = 0; + if (inst->state > VPU_INST_STATE_OPEN) { + s->r.width = inst->conf_win_width; + s->r.height = inst->conf_win_height; + } else { + s->r.width = inst->src_fmt.width; + s->r.height = inst->src_fmt.height; + } + break; + default: + return -EINVAL; + } + + return 0; +} + +static int wave5_vpu_dec_s_selection(struct file *file, void *fh, struct v4l2_selection *s) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + if (s->target != V4L2_SEL_TGT_COMPOSE) + return -EINVAL; + + dev_dbg(inst->dev->dev, "V4L2_SEL_TGT_COMPOSE w: %u h: %u\n", + s->r.width, s->r.height); + + s->r.left = 0; + s->r.top = 0; + s->r.width = inst->dst_fmt.width; + s->r.height = inst->dst_fmt.height; + + return 0; +} + +static int wave5_vpu_dec_decoder_cmd(struct file *file, void *fh, struct v4l2_decoder_cmd *dc) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + int ret; + + dev_dbg(inst->dev->dev, "decoder command: %u\n", dc->cmd); + + ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc); + if (ret) + return ret; + + if (!wave5_vpu_both_queues_are_streaming(inst)) + return 0; + + switch (dc->cmd) { + case V4L2_DEC_CMD_STOP: + inst->state = VPU_INST_STATE_STOP; + + ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0); + if (ret) { + dev_err(inst->dev->dev, + "Setting EOS for the bitstream, fail: %d\n", ret); + return ret; + } + break; + case V4L2_DEC_CMD_START: + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct v4l2_ioctl_ops wave5_vpu_dec_ioctl_ops = { + .vidioc_querycap = wave5_vpu_dec_querycap, + .vidioc_enum_framesizes = wave5_vpu_dec_enum_framesizes, + + .vidioc_enum_fmt_vid_cap = wave5_vpu_dec_enum_fmt_cap, + .vidioc_s_fmt_vid_cap_mplane = wave5_vpu_dec_s_fmt_cap, + .vidioc_g_fmt_vid_cap_mplane = wave5_vpu_dec_g_fmt_cap, + .vidioc_try_fmt_vid_cap_mplane = wave5_vpu_dec_try_fmt_cap, + + .vidioc_enum_fmt_vid_out = wave5_vpu_dec_enum_fmt_out, + .vidioc_s_fmt_vid_out_mplane = wave5_vpu_dec_s_fmt_out, + .vidioc_g_fmt_vid_out_mplane = wave5_vpu_g_fmt_out, + .vidioc_try_fmt_vid_out_mplane = wave5_vpu_dec_try_fmt_out, + + .vidioc_g_selection = wave5_vpu_dec_g_selection, + .vidioc_s_selection = wave5_vpu_dec_s_selection, + + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, + .vidioc_streamon = v4l2_m2m_ioctl_streamon, + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, + + .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd, + .vidioc_decoder_cmd = wave5_vpu_dec_decoder_cmd, + + .vidioc_subscribe_event = wave5_vpu_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static int wave5_vpu_dec_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl); + + dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n", + __func__, ctrl->name, ctrl->val); + + switch (ctrl->id) { + case V4L2_CID_VPU_THUMBNAIL_MODE: + inst->thumbnail_mode = ctrl->val; + break; + case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE: + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct v4l2_ctrl_ops wave5_vpu_dec_ctrl_ops = { + .s_ctrl = wave5_vpu_dec_s_ctrl, +}; + +static const struct v4l2_ctrl_config wave5_vpu_thumbnail_mode = { + .ops = &wave5_vpu_dec_ctrl_ops, + .id = V4L2_CID_VPU_THUMBNAIL_MODE, + .name = "thumbnail mode", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .def = 0, + .min = 0, + .max = 1, + .step = 1, + .flags = V4L2_CTRL_FLAG_WRITE_ONLY, +}; + +static void wave5_set_default_dec_openparam(struct dec_open_param *open_param) +{ + open_param->bitstream_mode = BS_MODE_INTERRUPT; + open_param->stream_endian = VPU_STREAM_ENDIAN; + open_param->frame_endian = VPU_FRAME_ENDIAN; +} + +static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, + unsigned int *num_planes, unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct vpu_instance *inst = vb2_get_drv_priv(q); + struct v4l2_pix_format_mplane inst_format = + (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; + unsigned int i; + int ret; + + dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, + *num_buffers, *num_planes, q->type); + + if (*num_planes) { + if (inst_format.num_planes != *num_planes) + return -EINVAL; + + for (i = 0; i < *num_planes; i++) { + if (sizes[i] < inst_format.plane_fmt[i].sizeimage) + return -EINVAL; + } + } else { + *num_planes = inst_format.num_planes; + + if (*num_planes == 1) { + sizes[0] = inst_format.width * inst_format.height * 3 / 2; + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + sizes[0] = inst_format.plane_fmt[0].sizeimage; + dev_dbg(inst->dev->dev, "%s: size[0]: %u\n", __func__, sizes[0]); + } else if (*num_planes == 2) { + sizes[0] = inst_format.width * inst_format.height; + sizes[1] = inst_format.width * inst_format.height / 2; + dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u\n", + __func__, sizes[0], sizes[1]); + } else if (*num_planes == 3) { + sizes[0] = inst_format.width * inst_format.height; + sizes[1] = inst_format.width * inst_format.height / 4; + sizes[2] = inst_format.width * inst_format.height / 4; + dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u | size[2]: %u\n", + __func__, sizes[0], sizes[1], sizes[2]); + } + } + + if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + struct dec_open_param open_param; + + memset(&open_param, 0, sizeof(struct dec_open_param)); + wave5_set_default_dec_openparam(&open_param); + + inst->bitstream_vbuf.size = ALIGN(inst->src_fmt.plane_fmt[0].sizeimage, 1024) * 4; + ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->bitstream_vbuf); + if (ret) { + dev_dbg(inst->dev->dev, "%s: alloc bitstream of size %zu fail: %d\n", + __func__, inst->bitstream_vbuf.size, ret); + return ret; + } + + inst->std = wave5_to_vpu_codstd(inst->src_fmt.pixelformat); + if (inst->std == STD_UNKNOWN) { + dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", + (char *)&inst->src_fmt.pixelformat); + ret = -EINVAL; + goto free_bitstream_vbuf; + } + open_param.bitstream_buffer = inst->bitstream_vbuf.daddr; + open_param.bitstream_buffer_size = inst->bitstream_vbuf.size; + + ret = wave5_vpu_dec_open(inst, &open_param); + if (ret) { + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_open, fail: %d\n", + __func__, ret); + goto free_bitstream_vbuf; + } + + inst->state = VPU_INST_STATE_OPEN; + + if (inst->thumbnail_mode) + wave5_vpu_dec_give_command(inst, ENABLE_DEC_THUMBNAIL_MODE, NULL); + + } else if (inst->state == VPU_INST_STATE_INIT_SEQ && + q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + u32 non_linear_num; + u32 fb_stride, fb_height; + u32 luma_size, chroma_size; + + if (*num_buffers > inst->min_dst_buf_count && + *num_buffers < WAVE5_MAX_FBS) + inst->dst_buf_count = *num_buffers; + + *num_buffers = inst->dst_buf_count; + non_linear_num = inst->dst_buf_count; + + for (i = 0; i < non_linear_num; i++) { + struct frame_buffer *frame = &inst->frame_buf[i]; + struct vpu_buf *vframe = &inst->frame_vbuf[i]; + + fb_stride = inst->dst_fmt.width; + fb_height = ALIGN(inst->dst_fmt.height, 32); + luma_size = fb_stride * fb_height; + chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; + + vframe->size = luma_size + chroma_size; + ret = wave5_vdi_allocate_dma_memory(inst->dev, vframe); + if (ret) { + dev_dbg(inst->dev->dev, + "%s: Allocating FBC buf of size %zu, fail: %d\n", + __func__, vframe->size, ret); + return ret; + } + + frame->buf_y = vframe->daddr; + frame->buf_cb = vframe->daddr + luma_size; + frame->buf_cr = (dma_addr_t)-1; + frame->size = vframe->size; + frame->width = inst->src_fmt.width; + frame->stride = fb_stride; + frame->map_type = COMPRESSED_FRAME_MAP; + frame->update_fb_info = true; + } + } else if (inst->state == VPU_INST_STATE_STOP && + q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + *num_buffers = 0; + } + + return 0; + +free_bitstream_vbuf: + wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf); + return ret; +} + +static int wave5_vpu_dec_start_streaming_open(struct vpu_instance *inst) +{ + struct dec_initial_info initial_info; + int ret = 0; + + memset(&initial_info, 0, sizeof(struct dec_initial_info)); + + ret = wave5_vpu_dec_issue_seq_init(inst); + if (ret) { + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_issue_seq_init, fail: %d\n", + __func__, ret); + return ret; + } + + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) + dev_dbg(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__); + + ret = wave5_vpu_dec_complete_seq_init(inst, &initial_info); + if (ret) { + dev_dbg(inst->dev->dev, "%s: vpu_dec_complete_seq_init, fail: %d, reason: %u\n", + __func__, ret, initial_info.seq_init_err_reason); + } else { + static const struct v4l2_event vpu_event_src_ch = { + .type = V4L2_EVENT_SOURCE_CHANGE, + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, + }; + struct v4l2_ctrl *ctrl; + + dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n", + __func__, initial_info.pic_width, initial_info.pic_height, + initial_info.profile, initial_info.min_frame_buffer_count); + + inst->state = VPU_INST_STATE_INIT_SEQ; + inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1; + inst->dst_buf_count = inst->min_dst_buf_count; + + inst->conf_win_width = initial_info.pic_width - initial_info.pic_crop_rect.right; + inst->conf_win_height = initial_info.pic_height - initial_info.pic_crop_rect.bottom; + + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE); + if (ctrl) + v4l2_ctrl_s_ctrl(ctrl, inst->min_dst_buf_count); + + if (initial_info.pic_width != inst->src_fmt.width || + initial_info.pic_height != inst->src_fmt.height) { + wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width, + initial_info.pic_height); + wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width, + initial_info.pic_height); + } + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch); + + wave5_handle_src_buffer(inst); + } + + return ret; +} + +static int wave5_vpu_dec_start_streaming_seek(struct vpu_instance *inst) +{ + struct dec_initial_info initial_info; + struct dec_param pic_param; + struct dec_output_info dec_output_info; + int ret = 0; + u32 fail_res = 0; + + memset(&pic_param, 0, sizeof(struct dec_param)); + + ret = wave5_vpu_dec_start_one_frame(inst, &pic_param, &fail_res); + if (ret && fail_res != WAVE5_SYSERR_QUEUEING_FAIL) { + struct vb2_v4l2_buffer *src_buf; + + src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); + inst->state = VPU_INST_STATE_STOP; + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_start_one_frame\n", __func__); + return ret; + } + + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) + dev_dbg(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__); + + ret = wave5_vpu_dec_get_output_info(inst, &dec_output_info); + if (ret) { + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_get_output_info, fail: %d\n", + __func__, ret); + return ret; + } + + if (dec_output_info.sequence_changed) { + static const struct v4l2_event vpu_event_src_ch = { + .type = V4L2_EVENT_SOURCE_CHANGE, + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, + }; + struct v4l2_ctrl *ctrl; + + wave5_vpu_dec_give_command(inst, DEC_RESET_FRAMEBUF_INFO, NULL); + wave5_vpu_dec_give_command(inst, DEC_GET_SEQ_INFO, &initial_info); + + dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n", + __func__, initial_info.pic_width, initial_info.pic_height, + initial_info.profile, initial_info.min_frame_buffer_count); + + inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1; + inst->dst_buf_count = inst->min_dst_buf_count; + + inst->conf_win_width = initial_info.pic_width - initial_info.pic_crop_rect.right; + inst->conf_win_height = initial_info.pic_height - initial_info.pic_crop_rect.bottom; + + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE); + if (ctrl) + v4l2_ctrl_s_ctrl(ctrl, inst->min_dst_buf_count); + + if (initial_info.pic_width != inst->src_fmt.width || + initial_info.pic_height != inst->src_fmt.height) { + wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width, + initial_info.pic_height); + wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width, + initial_info.pic_height); + } + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch); + + wave5_handle_src_buffer(inst); + } + + return ret; +} + +static void wave5_vpu_dec_buf_queue_src(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); + struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); + + vpu_buf->consumed = false; + vbuf->sequence = inst->queued_src_buf_num++; + + if (inst->state == VPU_INST_STATE_PIC_RUN) { + wave5_handle_bitstream_buffer(inst); + inst->ops->start_process(inst); + } +} + +static void wave5_vpu_dec_buf_queue_dst(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); + int ret; + + vbuf->sequence = inst->queued_dst_buf_num++; + ret = wave5_vpu_dec_clr_disp_flag(inst, vb->index); + if (ret) { + dev_dbg(inst->dev->dev, + "%s: Clearing the display flag of buffer index: %u, fail: %d\n", + __func__, vb->index, ret); + } + + if (inst->state == VPU_INST_STATE_INIT_SEQ) { + dma_addr_t buf_addr_y = 0, buf_addr_cb = 0, buf_addr_cr = 0; + u32 buf_size = 0; + u32 non_linear_num = inst->dst_buf_count; + u32 fb_stride = inst->dst_fmt.width; + u32 luma_size = fb_stride * inst->dst_fmt.height; + u32 chroma_size = (fb_stride / 2) * (inst->dst_fmt.height / 2); + + if (inst->dst_fmt.num_planes == 1) { + buf_size = vb2_plane_size(&vbuf->vb2_buf, 0); + buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); + buf_addr_cb = buf_addr_y + luma_size; + buf_addr_cr = buf_addr_cb + chroma_size; + } else if (inst->dst_fmt.num_planes == 2) { + buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) + + vb2_plane_size(&vbuf->vb2_buf, 1); + buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); + buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1); + buf_addr_cr = buf_addr_cb + chroma_size; + } else if (inst->dst_fmt.num_planes == 3) { + buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) + + vb2_plane_size(&vbuf->vb2_buf, 1) + + vb2_plane_size(&vbuf->vb2_buf, 2); + buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); + buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1); + buf_addr_cr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 2); + } + inst->frame_buf[vb->index + non_linear_num].buf_y = buf_addr_y; + inst->frame_buf[vb->index + non_linear_num].buf_cb = buf_addr_cb; + inst->frame_buf[vb->index + non_linear_num].buf_cr = buf_addr_cr; + inst->frame_buf[vb->index + non_linear_num].size = buf_size; + inst->frame_buf[vb->index + non_linear_num].width = inst->src_fmt.width; + inst->frame_buf[vb->index + non_linear_num].stride = fb_stride; + inst->frame_buf[vb->index + non_linear_num].map_type = LINEAR_FRAME_MAP; + inst->frame_buf[vb->index + non_linear_num].update_fb_info = true; + } + + if (!vb2_is_streaming(vb->vb2_queue)) + return; + + if (inst->state == VPU_INST_STATE_STOP && inst->eos == FALSE) + inst->ops->start_process(inst); +} + +static void wave5_vpu_dec_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); + + dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n", + __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), + vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); + + v4l2_m2m_buf_queue(inst->v4l2_fh.m2m_ctx, vbuf); + + if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + wave5_vpu_dec_buf_queue_src(vb); + else if (vb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) + wave5_vpu_dec_buf_queue_dst(vb); +} + +static int wave5_vpu_dec_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct vpu_instance *inst = vb2_get_drv_priv(q); + int ret = 0; + + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); + + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + wave5_handle_bitstream_buffer(inst); + if (inst->state == VPU_INST_STATE_OPEN) + ret = wave5_vpu_dec_start_streaming_open(inst); + else if (inst->state == VPU_INST_STATE_INIT_SEQ) + ret = wave5_vpu_dec_start_streaming_seek(inst); + + if (ret) { + struct vb2_v4l2_buffer *buf; + + while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { + dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4d | index %4d\n", + __func__, buf->vb2_buf.type, buf->vb2_buf.index); + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_QUEUED); + } + } + } + + return ret; +} + +static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q) +{ + struct vpu_instance *inst = vb2_get_drv_priv(q); + struct vb2_v4l2_buffer *buf; + bool check_cmd = TRUE; + + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); + + while (check_cmd) { + struct queue_status_info q_status; + struct dec_output_info dec_output_info; + + wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status); + + if (q_status.instance_queue_count + q_status.report_queue_count == 0) + break; + + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) + break; + + if (wave5_vpu_dec_get_output_info(inst, &dec_output_info)) + dev_dbg(inst->dev->dev, "Getting decoding results from fw, fail\n"); + } + + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { + dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4u | index %4u\n", + __func__, buf->vb2_buf.type, buf->vb2_buf.index); + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); + } + inst->queued_src_buf_num = 0; + } else { + unsigned int i; + int ret; + dma_addr_t rd_ptr, wr_ptr; + + while ((buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx))) { + u32 plane; + + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", + __func__, buf->vb2_buf.type, buf->vb2_buf.index); + + for (plane = 0; plane < inst->dst_fmt.num_planes; plane++) + vb2_set_plane_payload(&buf->vb2_buf, plane, 0); + + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); + } + + for (i = 0; i < inst->dst_buf_count; i++) { + ret = wave5_vpu_dec_set_disp_flag(inst, i); + if (ret) { + dev_dbg(inst->dev->dev, + "%s: Setting display flag of buf index: %u, fail: %d\n", + __func__, i, ret); + } + } + + ret = wave5_vpu_dec_get_bitstream_buffer(inst, &rd_ptr, &wr_ptr, NULL); + if (ret) { + dev_err(inst->dev->dev, + "Getting bitstream buf, fail: %d\n", ret); + return; + } + ret = wave5_vpu_dec_set_rd_ptr(inst, wr_ptr, TRUE); + if (ret) { + dev_err(inst->dev->dev, + "Setting read pointer for the decoder, fail: %d\n", ret); + return; + } + if (inst->eos) { + inst->eos = FALSE; + inst->state = VPU_INST_STATE_INIT_SEQ; + } + inst->queued_dst_buf_num = 0; + } +} + +static const struct vb2_ops wave5_vpu_dec_vb2_ops = { + .queue_setup = wave5_vpu_dec_queue_setup, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, + .buf_queue = wave5_vpu_dec_buf_queue, + .start_streaming = wave5_vpu_dec_start_streaming, + .stop_streaming = wave5_vpu_dec_stop_streaming, +}; + +static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, + struct v4l2_pix_format_mplane *dst_fmt) +{ + unsigned int dst_pix_fmt = dec_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; + const struct v4l2_format_info *dst_fmt_info = v4l2_format_info(dst_pix_fmt); + + src_fmt->pixelformat = dec_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; + src_fmt->field = V4L2_FIELD_NONE; + src_fmt->flags = 0; + src_fmt->num_planes = 1; + wave5_update_pix_fmt(src_fmt, 720, 480); + + dst_fmt->pixelformat = dst_pix_fmt; + dst_fmt->field = V4L2_FIELD_NONE; + dst_fmt->flags = 0; + dst_fmt->num_planes = dst_fmt_info->mem_planes; + wave5_update_pix_fmt(dst_fmt, 736, 480); +} + +static int wave5_vpu_dec_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) +{ + return wave5_vpu_queue_init(priv, src_vq, dst_vq, &wave5_vpu_dec_vb2_ops); +} + +static const struct vpu_instance_ops wave5_vpu_dec_inst_ops = { + .start_process = wave5_vpu_dec_start_decode, + .stop_process = wave5_vpu_dec_stop_decode, + .finish_process = wave5_vpu_dec_finish_decode, +}; + +static void wave5_vpu_dec_device_run(void *priv) +{ + struct vpu_instance *inst = priv; + + inst->ops->start_process(inst); + + inst->state = VPU_INST_STATE_PIC_RUN; +} + +static void wave5_vpu_dec_job_abort(void *priv) +{ + struct vpu_instance *inst = priv; + + inst->ops->stop_process(inst); +} + +static const struct v4l2_m2m_ops wave5_vpu_dec_m2m_ops = { + .device_run = wave5_vpu_dec_device_run, + .job_abort = wave5_vpu_dec_job_abort, +}; + +static int wave5_vpu_open_dec(struct file *filp) +{ + struct video_device *vdev = video_devdata(filp); + struct vpu_device *dev = video_drvdata(filp); + struct vpu_instance *inst = NULL; + int ret = 0; + + inst = kzalloc(sizeof(*inst), GFP_KERNEL); + if (!inst) + return -ENOMEM; + + inst->dev = dev; + inst->type = VPU_INST_TYPE_DEC; + inst->ops = &wave5_vpu_dec_inst_ops; + + v4l2_fh_init(&inst->v4l2_fh, vdev); + filp->private_data = &inst->v4l2_fh; + v4l2_fh_add(&inst->v4l2_fh); + + INIT_LIST_HEAD(&inst->list); + list_add_tail(&inst->list, &dev->instances); + + inst->v4l2_m2m_dev = v4l2_m2m_init(&wave5_vpu_dec_m2m_ops); + if (IS_ERR(inst->v4l2_m2m_dev)) { + ret = PTR_ERR(inst->v4l2_m2m_dev); + dev_err(inst->dev->dev, "v4l2_m2m_init, fail: %d\n", ret); + goto cleanup_inst; + } + + inst->v4l2_fh.m2m_ctx = + v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_dec_queue_init); + if (IS_ERR(inst->v4l2_fh.m2m_ctx)) { + ret = PTR_ERR(inst->v4l2_fh.m2m_ctx); + goto cleanup_inst; + } + + v4l2_ctrl_handler_init(&inst->v4l2_ctrl_hdl, 10); + v4l2_ctrl_new_custom(&inst->v4l2_ctrl_hdl, &wave5_vpu_thumbnail_mode, NULL); + v4l2_ctrl_new_std(&inst->v4l2_ctrl_hdl, &wave5_vpu_dec_ctrl_ops, + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 1); + + if (inst->v4l2_ctrl_hdl.error) { + ret = -ENODEV; + goto cleanup_inst; + } + + inst->v4l2_fh.ctrl_handler = &inst->v4l2_ctrl_hdl; + v4l2_ctrl_handler_setup(&inst->v4l2_ctrl_hdl); + + wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); + inst->colorspace = V4L2_COLORSPACE_REC709; + inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; + inst->hsv_enc = 0; + inst->quantization = V4L2_QUANTIZATION_DEFAULT; + inst->xfer_func = V4L2_XFER_FUNC_DEFAULT; + + init_completion(&inst->irq_done); + ret = kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL); + if (ret) { + dev_err(inst->dev->dev, "failed to allocate fifo\n"); + goto cleanup_inst; + } + + inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); + if (inst->id < 0) { + dev_warn(inst->dev->dev, "Allocating instance ID, fail: %d\n", inst->id); + ret = inst->id; + goto cleanup_inst; + } + + return 0; + +cleanup_inst: + wave5_cleanup_instance(inst); + return ret; +} + +static int wave5_vpu_dec_release(struct file *filp) +{ + return wave5_vpu_release_device(filp, wave5_vpu_dec_close, "decoder"); +} + +static const struct v4l2_file_operations wave5_vpu_dec_fops = { + .owner = THIS_MODULE, + .open = wave5_vpu_open_dec, + .release = wave5_vpu_dec_release, + .unlocked_ioctl = video_ioctl2, + .poll = v4l2_m2m_fop_poll, + .mmap = v4l2_m2m_fop_mmap, +}; + +int wave5_vpu_dec_register_device(struct vpu_device *dev) +{ + struct video_device *vdev_dec; + int ret; + + vdev_dec = devm_kzalloc(dev->v4l2_dev.dev, sizeof(*vdev_dec), GFP_KERNEL); + if (!vdev_dec) + return -ENOMEM; + + dev->video_dev_dec = vdev_dec; + + strscpy(vdev_dec->name, VPU_DEC_DEV_NAME, sizeof(vdev_dec->name)); + vdev_dec->fops = &wave5_vpu_dec_fops; + vdev_dec->ioctl_ops = &wave5_vpu_dec_ioctl_ops; + vdev_dec->release = video_device_release_empty; + vdev_dec->v4l2_dev = &dev->v4l2_dev; + vdev_dec->vfl_dir = VFL_DIR_M2M; + vdev_dec->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; + vdev_dec->lock = &dev->dev_lock; + + ret = video_register_device(vdev_dec, VFL_TYPE_VIDEO, -1); + if (ret) + return ret; + + video_set_drvdata(vdev_dec, dev); + + return 0; +} + +void wave5_vpu_dec_unregister_device(struct vpu_device *dev) +{ + video_unregister_device(dev->video_dev_dec); +} diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c new file mode 100644 index 000000000000..285111c2d9cd --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -0,0 +1,1746 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Wave5 series multi-standard codec IP - encoder interface + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ + +#include "wave5-helper.h" + +#define VPU_ENC_DEV_NAME "C&M Wave5 VPU encoder" +#define VPU_ENC_DRV_NAME "wave5-enc" + +static const struct vpu_format enc_fmt_list[FMT_TYPES][MAX_FMTS] = { + [VPU_FMT_TYPE_CODEC] = { + { + .v4l2_pix_fmt = V4L2_PIX_FMT_HEVC, + .max_width = W5_MAX_ENC_PIC_WIDTH, + .min_width = W5_MIN_ENC_PIC_WIDTH, + .max_height = W5_MAX_ENC_PIC_HEIGHT, + .min_height = W5_MIN_ENC_PIC_HEIGHT, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_H264, + .max_width = W5_MAX_ENC_PIC_WIDTH, + .min_width = W5_MIN_ENC_PIC_WIDTH, + .max_height = W5_MAX_ENC_PIC_HEIGHT, + .min_height = W5_MIN_ENC_PIC_HEIGHT, + }, + }, + [VPU_FMT_TYPE_RAW] = { + { + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420, + .max_width = W5_MAX_ENC_PIC_WIDTH, + .min_width = W5_MIN_ENC_PIC_WIDTH, + .max_height = W5_MAX_ENC_PIC_HEIGHT, + .min_height = W5_MIN_ENC_PIC_HEIGHT, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV12, + .max_width = W5_MAX_ENC_PIC_WIDTH, + .min_width = W5_MIN_ENC_PIC_WIDTH, + .max_height = W5_MAX_ENC_PIC_HEIGHT, + .min_height = W5_MIN_ENC_PIC_HEIGHT, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV21, + .max_width = W5_MAX_ENC_PIC_WIDTH, + .min_width = W5_MIN_ENC_PIC_WIDTH, + .max_height = W5_MAX_ENC_PIC_HEIGHT, + .min_height = W5_MIN_ENC_PIC_HEIGHT, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M, + .max_width = W5_MAX_ENC_PIC_WIDTH, + .min_width = W5_MIN_ENC_PIC_WIDTH, + .max_height = W5_MAX_ENC_PIC_HEIGHT, + .min_height = W5_MIN_ENC_PIC_HEIGHT, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV12M, + .max_width = W5_MAX_ENC_PIC_WIDTH, + .min_width = W5_MIN_ENC_PIC_WIDTH, + .max_height = W5_MAX_ENC_PIC_HEIGHT, + .min_height = W5_MIN_ENC_PIC_HEIGHT, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, + .max_width = W5_MAX_ENC_PIC_WIDTH, + .min_width = W5_MIN_ENC_PIC_WIDTH, + .max_height = W5_MAX_ENC_PIC_HEIGHT, + .min_height = W5_MIN_ENC_PIC_HEIGHT, + }, + } +}; + +static enum wave_std wave5_to_vpu_wavestd(unsigned int v4l2_pix_fmt) +{ + switch (v4l2_pix_fmt) { + case V4L2_PIX_FMT_H264: + return W_AVC_ENC; + case V4L2_PIX_FMT_HEVC: + return W_HEVC_ENC; + default: + return STD_UNKNOWN; + } +} + +static struct vb2_v4l2_buffer *wave5_get_valid_src_buf(struct vpu_instance *inst) +{ + struct v4l2_m2m_buffer *v4l2_m2m_buf; + + v4l2_m2m_for_each_src_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { + struct vb2_v4l2_buffer *vb2_v4l2_buf; + struct vpu_buffer *vpu_buf = NULL; + + vb2_v4l2_buf = &v4l2_m2m_buf->vb; + vpu_buf = wave5_to_vpu_buf(vb2_v4l2_buf); + + if (!vpu_buf->consumed) { + dev_dbg(inst->dev->dev, "%s: src buf (index: %u) has not been consumed\n", + __func__, vb2_v4l2_buf->vb2_buf.index); + return vb2_v4l2_buf; + } + } + + return NULL; +} + +static struct vb2_v4l2_buffer *wave5_get_valid_dst_buf(struct vpu_instance *inst) +{ + struct v4l2_m2m_buffer *v4l2_m2m_buf; + + v4l2_m2m_for_each_dst_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { + struct vb2_v4l2_buffer *vb2_v4l2_buf; + struct vpu_buffer *vpu_buf = NULL; + + vb2_v4l2_buf = &v4l2_m2m_buf->vb; + vpu_buf = wave5_to_vpu_buf(vb2_v4l2_buf); + + if (!vpu_buf->consumed) { + dev_dbg(inst->dev->dev, "%s: dst buf (index: %u) has not been consumed\n", + __func__, vb2_v4l2_buf->vb2_buf.index); + return vb2_v4l2_buf; + } + } + + return NULL; +} + +static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width, + unsigned int height) +{ + switch (pix_mp->pixelformat) { + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV21: + pix_mp->width = width; + pix_mp->height = height; + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); + pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height * 3 / 2; + break; + case V4L2_PIX_FMT_YUV420M: + pix_mp->width = width; + pix_mp->height = height; + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); + pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height; + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; + pix_mp->plane_fmt[1].sizeimage = round_up(width, 32) * height / 4; + pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; + pix_mp->plane_fmt[2].sizeimage = round_up(width, 32) * height / 4; + break; + case V4L2_PIX_FMT_NV12M: + case V4L2_PIX_FMT_NV21M: + pix_mp->width = width; + pix_mp->height = height; + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); + pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height; + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); + pix_mp->plane_fmt[1].sizeimage = round_up(width, 32) * height / 2; + break; + default: + pix_mp->width = width; + pix_mp->height = height; + pix_mp->plane_fmt[0].bytesperline = 0; + pix_mp->plane_fmt[0].sizeimage = width * height; + break; + } +} + +static void wave5_vpu_enc_start_encode(struct vpu_instance *inst) +{ + u32 max_cmd_q = 0; + + max_cmd_q = (inst->src_buf_count < COMMAND_QUEUE_DEPTH) ? + inst->src_buf_count : COMMAND_QUEUE_DEPTH; + + if (inst->state == VPU_INST_STATE_STOP) + max_cmd_q = 1; + + while (max_cmd_q) { + struct vb2_v4l2_buffer *src_buf; + struct vb2_v4l2_buffer *dst_buf; + struct vpu_buffer *src_vbuf; + struct vpu_buffer *dst_vbuf; + struct frame_buffer frame_buf; + struct enc_param pic_param; + u32 stride = ALIGN(inst->dst_fmt.width, 32); + u32 luma_size = (stride * inst->dst_fmt.height); + u32 chroma_size = ((stride / 2) * (inst->dst_fmt.height / 2)); + u32 fail_res; + int ret; + + memset(&pic_param, 0, sizeof(struct enc_param)); + memset(&frame_buf, 0, sizeof(struct frame_buffer)); + + src_buf = wave5_get_valid_src_buf(inst); + dst_buf = wave5_get_valid_dst_buf(inst); + + if (!dst_buf) { + dev_dbg(inst->dev->dev, "%s: No valid dst buf\n", __func__); + break; + } + + dst_vbuf = wave5_to_vpu_buf(dst_buf); + pic_param.pic_stream_buffer_addr = + vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); + pic_param.pic_stream_buffer_size = + vb2_plane_size(&dst_buf->vb2_buf, 0); + + if (!src_buf) { + dev_dbg(inst->dev->dev, "%s: No valid src buf\n", __func__); + if (inst->state == VPU_INST_STATE_STOP) + pic_param.src_end_flag = true; + else + break; + } else { + src_vbuf = wave5_to_vpu_buf(src_buf); + if (inst->src_fmt.num_planes == 1) { + frame_buf.buf_y = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + frame_buf.buf_cb = frame_buf.buf_y + luma_size; + frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; + } else if (inst->src_fmt.num_planes == 2) { + frame_buf.buf_y = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + frame_buf.buf_cb = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); + frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; + } else if (inst->src_fmt.num_planes == 3) { + frame_buf.buf_y = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + frame_buf.buf_cb = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); + frame_buf.buf_cr = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 2); + } + frame_buf.stride = stride; + pic_param.src_idx = src_buf->vb2_buf.index; + } + + pic_param.source_frame = &frame_buf; + pic_param.code_option.implicit_header_encode = 1; + ret = wave5_vpu_enc_start_one_frame(inst, &pic_param, &fail_res); + if (ret) { + if (fail_res == WAVE5_SYSERR_QUEUEING_FAIL) + break; + + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame fail: %d\n", + __func__, ret); + src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); + if (!src_buf) { + dev_dbg(inst->dev->dev, + "%s: Removing src buf failed, the queue is empty\n", + __func__); + continue; + } + dst_buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx); + if (!dst_buf) { + dev_dbg(inst->dev->dev, + "%s: Removing dst buf failed, the queue is empty\n", + __func__); + continue; + } + inst->state = VPU_INST_STATE_STOP; + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR); + } else { + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame success\n", + __func__); + if (src_buf) + src_vbuf->consumed = true; + if (dst_buf) + dst_vbuf->consumed = true; + } + + max_cmd_q--; + } +} + +static void wave5_vpu_enc_stop_encode(struct vpu_instance *inst) +{ + inst->state = VPU_INST_STATE_STOP; + + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); +} + +static void wave5_vpu_enc_finish_encode(struct vpu_instance *inst) +{ + int ret; + struct enc_output_info enc_output_info; + u32 irq_status; + struct vb2_v4l2_buffer *dst_buf = NULL; + struct v4l2_m2m_buffer *v4l2_m2m_buf = NULL; + + if (kfifo_out(&inst->irq_status, &irq_status, sizeof(int))) + wave5_vpu_clear_interrupt_ex(inst, irq_status); + + ret = wave5_vpu_enc_get_output_info(inst, &enc_output_info); + if (ret) { + dev_dbg(inst->dev->dev, + "%s: vpu_enc_get_output_info fail: %d reason: %u | info: %u\n", + __func__, ret, enc_output_info.error_reason, enc_output_info.warn_info); + return; + } + + v4l2_m2m_for_each_dst_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { + dst_buf = &v4l2_m2m_buf->vb; + if (enc_output_info.bitstream_buffer == + vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0)) + break; + } + + if (enc_output_info.enc_src_idx >= 0) { + struct vb2_v4l2_buffer *src_buf = + v4l2_m2m_src_buf_remove_by_idx(inst->v4l2_fh.m2m_ctx, + enc_output_info.enc_src_idx); + + inst->timestamp = src_buf->vb2_buf.timestamp; + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); + } + + if (enc_output_info.recon_frame_index == RECON_IDX_FLAG_ENC_END) { + static const struct v4l2_event vpu_event_eos = { + .type = V4L2_EVENT_EOS + }; + + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, 0); + dst_buf->vb2_buf.timestamp = inst->timestamp; + dst_buf->field = V4L2_FIELD_NONE; + dst_buf->flags |= V4L2_BUF_FLAG_LAST; + v4l2_m2m_dst_buf_remove_by_buf(inst->v4l2_fh.m2m_ctx, dst_buf); + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); + + inst->state = VPU_INST_STATE_PIC_RUN; + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos); + + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); + } else { + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, enc_output_info.bitstream_size); + + dst_buf->vb2_buf.timestamp = inst->timestamp; + dst_buf->field = V4L2_FIELD_NONE; + if (enc_output_info.pic_type == PIC_TYPE_I) { + if (enc_output_info.enc_vcl_nut == 19 || + enc_output_info.enc_vcl_nut == 20) + dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME; + else + dst_buf->flags |= V4L2_BUF_FLAG_PFRAME; + } else if (enc_output_info.pic_type == PIC_TYPE_P) { + dst_buf->flags |= V4L2_BUF_FLAG_PFRAME; + } else if (enc_output_info.pic_type == PIC_TYPE_B) { + dst_buf->flags |= V4L2_BUF_FLAG_BFRAME; + } + + v4l2_m2m_dst_buf_remove_by_buf(inst->v4l2_fh.m2m_ctx, dst_buf); + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); + + dev_dbg(inst->dev->dev, "%s: frame_cycle %8u\n", + __func__, enc_output_info.frame_cycle); + } +} + +static int wave5_vpu_enc_querycap(struct file *file, void *fh, struct v4l2_capability *cap) +{ + strscpy(cap->driver, VPU_ENC_DRV_NAME, sizeof(cap->driver)); + strscpy(cap->card, VPU_ENC_DRV_NAME, sizeof(cap->card)); + strscpy(cap->bus_info, "platform:" VPU_ENC_DRV_NAME, sizeof(cap->bus_info)); + + return 0; +} + +static int wave5_vpu_enc_enum_framesizes(struct file *f, void *fh, struct v4l2_frmsizeenum *fsize) +{ + const struct vpu_format *vpu_fmt; + + if (fsize->index) + return -EINVAL; + + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, enc_fmt_list[VPU_FMT_TYPE_CODEC]); + if (!vpu_fmt) { + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, enc_fmt_list[VPU_FMT_TYPE_RAW]); + if (!vpu_fmt) + return -EINVAL; + } + + fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; + fsize->stepwise.min_width = vpu_fmt->min_width; + fsize->stepwise.max_width = vpu_fmt->max_width; + fsize->stepwise.step_width = 1; + fsize->stepwise.min_height = vpu_fmt->min_height; + fsize->stepwise.max_height = vpu_fmt->max_height; + fsize->stepwise.step_height = 1; + + return 0; +} + +static int wave5_vpu_enc_enum_fmt_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct vpu_format *vpu_fmt; + + dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); + + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, enc_fmt_list[VPU_FMT_TYPE_CODEC]); + if (!vpu_fmt) + return -EINVAL; + + f->pixelformat = vpu_fmt->v4l2_pix_fmt; + f->flags = 0; + + return 0; +} + +static int wave5_vpu_enc_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct vpu_format *vpu_fmt; + + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); + + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) + return -EINVAL; + + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]); + if (!vpu_fmt) { + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height); + } else { + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); + + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; + f->fmt.pix_mp.num_planes = 1; + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); + } + + f->fmt.pix_mp.flags = 0; + f->fmt.pix_mp.field = V4L2_FIELD_NONE; + f->fmt.pix_mp.colorspace = inst->colorspace; + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; + f->fmt.pix_mp.quantization = inst->quantization; + f->fmt.pix_mp.xfer_func = inst->xfer_func; + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); + + return 0; +} + +static int wave5_vpu_enc_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + int i, ret; + + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); + + ret = wave5_vpu_enc_try_fmt_cap(file, fh, f); + if (ret) + return ret; + + inst->dst_fmt.width = f->fmt.pix_mp.width; + inst->dst_fmt.height = f->fmt.pix_mp.height; + inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat; + inst->dst_fmt.field = f->fmt.pix_mp.field; + inst->dst_fmt.flags = f->fmt.pix_mp.flags; + inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes; + for (i = 0; i < inst->dst_fmt.num_planes; i++) { + inst->dst_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; + inst->dst_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; + } + + return 0; +} + +static int wave5_vpu_enc_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + int i; + + f->fmt.pix_mp.width = inst->dst_fmt.width; + f->fmt.pix_mp.height = inst->dst_fmt.height; + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; + f->fmt.pix_mp.field = inst->dst_fmt.field; + f->fmt.pix_mp.flags = inst->dst_fmt.flags; + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { + f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->dst_fmt.plane_fmt[i].bytesperline; + f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->dst_fmt.plane_fmt[i].sizeimage; + } + + f->fmt.pix_mp.colorspace = inst->colorspace; + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; + f->fmt.pix_mp.quantization = inst->quantization; + f->fmt.pix_mp.xfer_func = inst->xfer_func; + + return 0; +} + +static int wave5_vpu_enc_enum_fmt_out(struct file *file, void *fh, struct v4l2_fmtdesc *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct vpu_format *vpu_fmt; + + dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); + + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, enc_fmt_list[VPU_FMT_TYPE_RAW]); + if (!vpu_fmt) + return -EINVAL; + + f->pixelformat = vpu_fmt->v4l2_pix_fmt; + f->flags = 0; + + return 0; +} + +static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct vpu_format *vpu_fmt; + + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); + + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + return -EINVAL; + + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_RAW]); + if (!vpu_fmt) { + f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; + f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height); + } else { + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); + const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); + + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; + f->fmt.pix_mp.num_planes = info->mem_planes; + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); + } + + f->fmt.pix_mp.flags = 0; + f->fmt.pix_mp.field = V4L2_FIELD_NONE; + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); + + return 0; +} + +static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + int i, ret; + + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); + + ret = wave5_vpu_enc_try_fmt_out(file, fh, f); + if (ret) + return ret; + + inst->src_fmt.width = f->fmt.pix_mp.width; + inst->src_fmt.height = f->fmt.pix_mp.height; + inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat; + inst->src_fmt.field = f->fmt.pix_mp.field; + inst->src_fmt.flags = f->fmt.pix_mp.flags; + inst->src_fmt.num_planes = f->fmt.pix_mp.num_planes; + for (i = 0; i < inst->src_fmt.num_planes; i++) { + inst->src_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; + inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; + } + + if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12 || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12M) { + inst->cbcr_interleave = true; + inst->nv21 = false; + } else if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21 || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21M) { + inst->cbcr_interleave = true; + inst->nv21 = true; + } else { + inst->cbcr_interleave = false; + inst->nv21 = false; + } + + inst->colorspace = f->fmt.pix_mp.colorspace; + inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; + inst->hsv_enc = f->fmt.pix_mp.hsv_enc; + inst->quantization = f->fmt.pix_mp.quantization; + inst->xfer_func = f->fmt.pix_mp.xfer_func; + + wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height); + + return 0; +} + +static int wave5_vpu_enc_g_selection(struct file *file, void *fh, struct v4l2_selection *s) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + + dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target); + + if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { + switch (s->target) { + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + s->r.left = 0; + s->r.top = 0; + s->r.width = inst->dst_fmt.width; + s->r.height = inst->dst_fmt.height; + break; + case V4L2_SEL_TGT_CROP: + s->r.left = 0; + s->r.top = 0; + s->r.width = inst->dst_fmt.width; + s->r.height = inst->dst_fmt.height; + dev_dbg(inst->dev->dev, "%s: V4L2_SEL_TGT_CROP width: %u | height: %u\n", + __func__, s->r.width, s->r.height); + break; + default: + return -EINVAL; + } + } else { + return -EINVAL; + } + + return 0; +} + +static int wave5_vpu_enc_s_selection(struct file *file, void *fh, struct v4l2_selection *s) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + + if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) + return -EINVAL; + + if (s->target != V4L2_SEL_TGT_CROP) + return -EINVAL; + + dev_dbg(inst->dev->dev, "%s: V4L2_SEL_TGT_CROP width: %u | height: %u\n", + __func__, s->r.width, s->r.height); + + s->r.left = 0; + s->r.top = 0; + s->r.width = inst->src_fmt.width; + s->r.height = inst->src_fmt.height; + + return 0; +} + +static int wave5_vpu_enc_encoder_cmd(struct file *file, void *fh, struct v4l2_encoder_cmd *ec) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + int ret; + + ret = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, ec); + if (ret) + return ret; + + if (!wave5_vpu_both_queues_are_streaming(inst)) + return 0; + + switch (ec->cmd) { + case V4L2_ENC_CMD_STOP: + inst->state = VPU_INST_STATE_STOP; + inst->ops->start_process(inst); + break; + case V4L2_ENC_CMD_START: + break; + default: + return -EINVAL; + } + + return 0; +} + +static int wave5_vpu_enc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, a->type); + + if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + return -EINVAL; + + a->parm.output.capability = V4L2_CAP_TIMEPERFRAME; + a->parm.output.timeperframe.numerator = 1; + a->parm.output.timeperframe.denominator = inst->frame_rate; + + dev_dbg(inst->dev->dev, "%s: numerator: %u | denominator: %u\n", + __func__, a->parm.output.timeperframe.numerator, + a->parm.output.timeperframe.denominator); + + return 0; +} + +static int wave5_vpu_enc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a) +{ + struct vpu_instance *inst = wave5_to_vpu_inst(fh); + + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, a->type); + + if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + return -EINVAL; + + a->parm.output.capability = V4L2_CAP_TIMEPERFRAME; + if (a->parm.output.timeperframe.denominator && a->parm.output.timeperframe.numerator) { + inst->frame_rate = a->parm.output.timeperframe.denominator / + a->parm.output.timeperframe.numerator; + } else { + a->parm.output.timeperframe.numerator = 1; + a->parm.output.timeperframe.denominator = inst->frame_rate; + } + + dev_dbg(inst->dev->dev, "%s: numerator: %u | denominator: %u\n", + __func__, a->parm.output.timeperframe.numerator, + a->parm.output.timeperframe.denominator); + + return 0; +} + +static const struct v4l2_ioctl_ops wave5_vpu_enc_ioctl_ops = { + .vidioc_querycap = wave5_vpu_enc_querycap, + .vidioc_enum_framesizes = wave5_vpu_enc_enum_framesizes, + + .vidioc_enum_fmt_vid_cap = wave5_vpu_enc_enum_fmt_cap, + .vidioc_s_fmt_vid_cap_mplane = wave5_vpu_enc_s_fmt_cap, + .vidioc_g_fmt_vid_cap_mplane = wave5_vpu_enc_g_fmt_cap, + .vidioc_try_fmt_vid_cap_mplane = wave5_vpu_enc_try_fmt_cap, + + .vidioc_enum_fmt_vid_out = wave5_vpu_enc_enum_fmt_out, + .vidioc_s_fmt_vid_out_mplane = wave5_vpu_enc_s_fmt_out, + .vidioc_g_fmt_vid_out_mplane = wave5_vpu_g_fmt_out, + .vidioc_try_fmt_vid_out_mplane = wave5_vpu_enc_try_fmt_out, + + .vidioc_g_selection = wave5_vpu_enc_g_selection, + .vidioc_s_selection = wave5_vpu_enc_s_selection, + + .vidioc_g_parm = wave5_vpu_enc_g_parm, + .vidioc_s_parm = wave5_vpu_enc_s_parm, + + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, + .vidioc_streamon = v4l2_m2m_ioctl_streamon, + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, + + .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd, + .vidioc_encoder_cmd = wave5_vpu_enc_encoder_cmd, + + .vidioc_subscribe_event = wave5_vpu_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl); + + dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n", __func__, ctrl->name, ctrl->val); + + switch (ctrl->id) { + case V4L2_CID_HFLIP: + inst->mirror_direction |= (ctrl->val << 1); + break; + case V4L2_CID_VFLIP: + inst->mirror_direction |= ctrl->val; + break; + case V4L2_CID_ROTATE: + inst->rot_angle = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_VBV_SIZE: + inst->vbv_buf_size = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: + switch (ctrl->val) { + case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR: + inst->rc_mode = 0; + break; + case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR: + inst->rc_mode = 1; + break; + default: + return -EINVAL; + } + break; + case V4L2_CID_MPEG_VIDEO_BITRATE: + inst->bit_rate = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_GOP_SIZE: + inst->enc_param.avc_idr_period = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE: + inst->enc_param.independ_slice_mode = ctrl->val; + inst->enc_param.avc_slice_mode = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB: + inst->enc_param.independ_slice_mode_arg = ctrl->val; + inst->enc_param.avc_slice_arg = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: + inst->rc_enable = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE: + inst->enc_param.mb_level_rc_enable = ctrl->val; + inst->enc_param.cu_level_rc_enable = ctrl->val; + inst->enc_param.hvs_qp_enable = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: + switch (ctrl->val) { + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN: + inst->enc_param.profile = HEVC_PROFILE_MAIN; + inst->bit_depth = 8; + break; + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE: + inst->enc_param.profile = HEVC_PROFILE_STILLPICTURE; + inst->enc_param.en_still_picture = 1; + inst->bit_depth = 8; + break; + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10: + inst->enc_param.profile = HEVC_PROFILE_MAIN10; + inst->bit_depth = 10; + break; + default: + return -EINVAL; + } + break; + case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: + switch (ctrl->val) { + case V4L2_MPEG_VIDEO_HEVC_LEVEL_1: + inst->enc_param.level = 10 * 3; + break; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2: + inst->enc_param.level = 20 * 3; + break; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1: + inst->enc_param.level = 21 * 3; + break; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3: + inst->enc_param.level = 30 * 3; + break; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1: + inst->enc_param.level = 31 * 3; + break; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4: + inst->enc_param.level = 40 * 3; + break; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1: + inst->enc_param.level = 41 * 3; + break; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5: + inst->enc_param.level = 50 * 3; + break; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1: + inst->enc_param.level = 51 * 3; + break; + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2: + inst->enc_param.level = 52 * 3; + break; + default: + return -EINVAL; + } + break; + case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: + inst->enc_param.min_qp_i = ctrl->val; + inst->enc_param.min_qp_p = ctrl->val; + inst->enc_param.min_qp_b = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: + inst->enc_param.max_qp_i = ctrl->val; + inst->enc_param.max_qp_p = ctrl->val; + inst->enc_param.max_qp_b = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: + inst->enc_param.intra_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE: + switch (ctrl->val) { + case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED: + inst->enc_param.disable_deblk = 1; + inst->enc_param.sao_enable = 0; + inst->enc_param.lf_cross_slice_boundary_enable = 0; + break; + case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED: + inst->enc_param.disable_deblk = 0; + inst->enc_param.sao_enable = 1; + inst->enc_param.lf_cross_slice_boundary_enable = 1; + break; + case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY: + inst->enc_param.disable_deblk = 0; + inst->enc_param.sao_enable = 1; + inst->enc_param.lf_cross_slice_boundary_enable = 0; + break; + default: + return -EINVAL; + } + break; + case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2: + inst->enc_param.beta_offset_div2 = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2: + inst->enc_param.tc_offset_div2 = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE: + switch (ctrl->val) { + case V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE: + inst->enc_param.decoding_refresh_type = 0; + break; + case V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA: + inst->enc_param.decoding_refresh_type = 1; + break; + case V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR: + inst->enc_param.decoding_refresh_type = 2; + break; + default: + return -EINVAL; + } + break; + case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD: + inst->enc_param.intra_period = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU: + inst->enc_param.lossless_enable = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED: + inst->enc_param.const_intra_pred_flag = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT: + inst->enc_param.wpp_enable = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING: + inst->enc_param.strong_intra_smooth_enable = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1: + inst->enc_param.max_num_merge = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION: + inst->enc_param.tmvp_enable = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_PROFILE: + switch (ctrl->val) { + case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: + case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: + inst->enc_param.profile = H264_PROFILE_BP; + inst->bit_depth = 8; + break; + case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: + inst->enc_param.profile = H264_PROFILE_MP; + inst->bit_depth = 8; + break; + case V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED: + inst->enc_param.profile = H264_PROFILE_EXTENDED; + inst->bit_depth = 8; + break; + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: + inst->enc_param.profile = H264_PROFILE_HP; + inst->bit_depth = 8; + break; + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10: + inst->enc_param.profile = H264_PROFILE_HIGH10; + inst->bit_depth = 10; + break; + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422: + inst->enc_param.profile = H264_PROFILE_HIGH422; + inst->bit_depth = 10; + break; + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE: + inst->enc_param.profile = H264_PROFILE_HIGH444; + inst->bit_depth = 10; + break; + default: + return -EINVAL; + } + break; + case V4L2_CID_MPEG_VIDEO_H264_LEVEL: + switch (ctrl->val) { + case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: + inst->enc_param.level = 10; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_1B: + inst->enc_param.level = 9; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: + inst->enc_param.level = 11; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: + inst->enc_param.level = 12; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: + inst->enc_param.level = 13; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: + inst->enc_param.level = 20; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: + inst->enc_param.level = 21; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: + inst->enc_param.level = 22; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: + inst->enc_param.level = 30; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: + inst->enc_param.level = 31; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: + inst->enc_param.level = 32; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: + inst->enc_param.level = 40; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_4_1: + inst->enc_param.level = 41; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_4_2: + inst->enc_param.level = 42; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_5_0: + inst->enc_param.level = 50; + break; + case V4L2_MPEG_VIDEO_H264_LEVEL_5_1: + inst->enc_param.level = 51; + break; + default: + return -EINVAL; + } + break; + case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: + inst->enc_param.min_qp_i = ctrl->val; + inst->enc_param.min_qp_p = ctrl->val; + inst->enc_param.min_qp_b = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: + inst->enc_param.max_qp_i = ctrl->val; + inst->enc_param.max_qp_p = ctrl->val; + inst->enc_param.max_qp_b = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: + inst->enc_param.intra_qp = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE: + switch (ctrl->val) { + case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED: + inst->enc_param.disable_deblk = 1; + inst->enc_param.lf_cross_slice_boundary_enable = 1; + break; + case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED: + inst->enc_param.disable_deblk = 0; + inst->enc_param.lf_cross_slice_boundary_enable = 1; + break; + case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY: + inst->enc_param.disable_deblk = 0; + inst->enc_param.lf_cross_slice_boundary_enable = 0; + break; + default: + return -EINVAL; + } + break; + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA: + inst->enc_param.beta_offset_div2 = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA: + inst->enc_param.tc_offset_div2 = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM: + inst->enc_param.transform8x8_enable = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: + inst->enc_param.const_intra_pred_flag = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET: + inst->enc_param.chroma_cb_qp_offset = ctrl->val; + inst->enc_param.chroma_cr_qp_offset = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD: + inst->enc_param.intra_period = ctrl->val; + break; + case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: + inst->enc_param.entropy_coding_mode = ctrl->val; + break; + case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT: + break; + default: + return -EINVAL; + } + + return 0; +} + +static const struct v4l2_ctrl_ops wave5_vpu_enc_ctrl_ops = { + .s_ctrl = wave5_vpu_enc_s_ctrl, +}; + +static void wave5_set_enc_openparam(struct enc_open_param *open_param, + struct vpu_instance *inst) +{ + struct enc_wave_param input = inst->enc_param; + u32 num_ctu_row = ALIGN(inst->dst_fmt.height, 64) / 64; + u32 num_mb_row = ALIGN(inst->dst_fmt.height, 16) / 16; + + open_param->wave_param.gop_preset_idx = PRESET_IDX_IPP_SINGLE; + open_param->wave_param.hvs_qp_scale = 2; + open_param->wave_param.hvs_max_delta_qp = 10; + open_param->wave_param.skip_intra_trans = 1; + open_param->wave_param.intra_nx_n_enable = 1; + open_param->wave_param.nr_intra_weight_y = 7; + open_param->wave_param.nr_intra_weight_cb = 7; + open_param->wave_param.nr_intra_weight_cr = 7; + open_param->wave_param.nr_inter_weight_y = 4; + open_param->wave_param.nr_inter_weight_cb = 4; + open_param->wave_param.nr_inter_weight_cr = 4; + open_param->wave_param.rdo_skip = 1; + open_param->wave_param.lambda_scaling_enable = 1; + + open_param->stream_endian = VPU_STREAM_ENDIAN; + open_param->source_endian = VPU_SOURCE_ENDIAN; + open_param->line_buf_int_en = true; + open_param->pic_width = inst->dst_fmt.width; + open_param->pic_height = inst->dst_fmt.height; + open_param->frame_rate_info = inst->frame_rate; + open_param->rc_enable = inst->rc_enable; + if (inst->rc_enable) { + open_param->wave_param.initial_rc_qp = -1; + open_param->wave_param.rc_weight_param = 16; + open_param->wave_param.rc_weight_buf = 128; + } + open_param->wave_param.mb_level_rc_enable = input.mb_level_rc_enable; + open_param->wave_param.cu_level_rc_enable = input.cu_level_rc_enable; + open_param->wave_param.hvs_qp_enable = input.hvs_qp_enable; + open_param->bit_rate = inst->bit_rate; + open_param->vbv_buffer_size = inst->vbv_buf_size; + if (inst->rc_mode == 0) + open_param->vbv_buffer_size = 3000; + open_param->wave_param.profile = input.profile; + open_param->wave_param.en_still_picture = input.en_still_picture; + open_param->wave_param.level = input.level; + open_param->wave_param.internal_bit_depth = inst->bit_depth; + open_param->wave_param.intra_qp = input.intra_qp; + open_param->wave_param.min_qp_i = input.min_qp_i; + open_param->wave_param.max_qp_i = input.max_qp_i; + open_param->wave_param.min_qp_p = input.min_qp_p; + open_param->wave_param.max_qp_p = input.max_qp_p; + open_param->wave_param.min_qp_b = input.min_qp_b; + open_param->wave_param.max_qp_b = input.max_qp_b; + open_param->wave_param.disable_deblk = input.disable_deblk; + open_param->wave_param.lf_cross_slice_boundary_enable = + input.lf_cross_slice_boundary_enable; + open_param->wave_param.tc_offset_div2 = input.tc_offset_div2; + open_param->wave_param.beta_offset_div2 = input.beta_offset_div2; + open_param->wave_param.decoding_refresh_type = input.decoding_refresh_type; + open_param->wave_param.intra_period = input.intra_period; + if (inst->std == W_HEVC_ENC) { + if (input.intra_period == 0) { + open_param->wave_param.decoding_refresh_type = DEC_REFRESH_TYPE_IDR; + open_param->wave_param.intra_period = input.avc_idr_period; + } + } else { + open_param->wave_param.avc_idr_period = input.avc_idr_period; + } + open_param->wave_param.entropy_coding_mode = input.entropy_coding_mode; + open_param->wave_param.lossless_enable = input.lossless_enable; + open_param->wave_param.const_intra_pred_flag = input.const_intra_pred_flag; + open_param->wave_param.wpp_enable = input.wpp_enable; + open_param->wave_param.strong_intra_smooth_enable = input.strong_intra_smooth_enable; + open_param->wave_param.max_num_merge = input.max_num_merge; + open_param->wave_param.tmvp_enable = input.tmvp_enable; + open_param->wave_param.transform8x8_enable = input.transform8x8_enable; + open_param->wave_param.chroma_cb_qp_offset = input.chroma_cb_qp_offset; + open_param->wave_param.chroma_cr_qp_offset = input.chroma_cr_qp_offset; + open_param->wave_param.independ_slice_mode = input.independ_slice_mode; + open_param->wave_param.independ_slice_mode_arg = input.independ_slice_mode_arg; + open_param->wave_param.avc_slice_mode = input.avc_slice_mode; + open_param->wave_param.avc_slice_arg = input.avc_slice_arg; + open_param->wave_param.intra_mb_refresh_mode = input.intra_mb_refresh_mode; + if (input.intra_mb_refresh_mode != REFRESH_MB_MODE_NONE) { + if (num_mb_row >= input.intra_mb_refresh_arg) + open_param->wave_param.intra_mb_refresh_arg = + num_mb_row / input.intra_mb_refresh_arg; + else + open_param->wave_param.intra_mb_refresh_arg = num_mb_row; + } + open_param->wave_param.intra_refresh_mode = input.intra_refresh_mode; + if (input.intra_refresh_mode != 0) { + if (num_ctu_row >= input.intra_refresh_arg) + open_param->wave_param.intra_refresh_arg = + num_ctu_row / input.intra_refresh_arg; + else + open_param->wave_param.intra_refresh_arg = num_ctu_row; + } +} + +static int wave5_vpu_enc_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, + unsigned int *num_planes, unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct vpu_instance *inst = vb2_get_drv_priv(q); + struct v4l2_pix_format_mplane inst_format = + (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; + unsigned int i; + int ret; + + dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, + *num_buffers, *num_planes, q->type); + + if (*num_planes) { + if (inst_format.num_planes != *num_planes) + return -EINVAL; + + for (i = 0; i < *num_planes; i++) { + if (sizes[i] < inst_format.plane_fmt[i].sizeimage) + return -EINVAL; + } + } else { + *num_planes = inst_format.num_planes; + for (i = 0; i < *num_planes; i++) { + sizes[i] = inst_format.plane_fmt[i].sizeimage; + dev_dbg(inst->dev->dev, "%s: size[%u]: %u\n", __func__, i, sizes[i]); + } + } + + dev_dbg(inst->dev->dev, "%s: size: %u\n", __func__, sizes[0]); + + if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + unsigned int non_linear_num = 0; + u32 fb_stride = 0; + u32 fb_height = 0; + struct enc_open_param open_param; + struct enc_initial_info initial_info; + struct v4l2_ctrl *ctrl; + + memset(&open_param, 0, sizeof(struct enc_open_param)); + + inst->std = wave5_to_vpu_wavestd(inst->dst_fmt.pixelformat); + if (inst->std == STD_UNKNOWN) { + dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", + (char *)&inst->dst_fmt.pixelformat); + return -EINVAL; + } + + wave5_set_enc_openparam(&open_param, inst); + + ret = wave5_vpu_enc_open(inst, &open_param); + if (ret) { + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_open, fail: %d\n", + __func__, ret); + return ret; + } + + inst->state = VPU_INST_STATE_OPEN; + + if (inst->mirror_direction) { + wave5_vpu_enc_give_command(inst, ENABLE_MIRRORING, NULL); + wave5_vpu_enc_give_command(inst, SET_MIRROR_DIRECTION, + &inst->mirror_direction); + } + if (inst->rot_angle) { + wave5_vpu_enc_give_command(inst, ENABLE_ROTATION, NULL); + wave5_vpu_enc_give_command(inst, SET_ROTATION_ANGLE, &inst->rot_angle); + } + + ret = wave5_vpu_enc_issue_seq_init(inst); + if (ret) { + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_issue_seq_init, fail: %d\n", + __func__, ret); + return ret; + } + + if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) { + dev_dbg(inst->dev->dev, "%s: wave5_vpu_wait_interrupt failed\n", __func__); + return -EINVAL; + } + + ret = wave5_vpu_enc_complete_seq_init(inst, &initial_info); + if (ret) + return ret; + + dev_dbg(inst->dev->dev, "%s: min_frame_buffer: %u | min_source_buffer: %u\n", + __func__, initial_info.min_frame_buffer_count, + initial_info.min_src_frame_count); + inst->state = VPU_INST_STATE_INIT_SEQ; + inst->min_src_buf_count = initial_info.min_src_frame_count + + COMMAND_QUEUE_DEPTH; + + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT); + if (ctrl) + v4l2_ctrl_s_ctrl(ctrl, inst->min_src_buf_count); + + inst->min_dst_buf_count = initial_info.min_frame_buffer_count; + inst->src_buf_count = inst->min_src_buf_count; + + if (*num_buffers > inst->src_buf_count) + inst->src_buf_count = *num_buffers; + + *num_buffers = inst->src_buf_count; + non_linear_num = inst->min_dst_buf_count; + + fb_stride = ALIGN(inst->dst_fmt.width, 32); + fb_height = ALIGN(inst->dst_fmt.height, 32); + + for (i = 0; i < non_linear_num; i++) { + u32 luma_size = fb_stride * fb_height; + u32 chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; + + inst->frame_vbuf[i].size = luma_size + chroma_size; + ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->frame_vbuf[i]); + if (ret < 0) { + dev_dbg(inst->dev->dev, "%s: failed to allocate FBC buffer %zu\n", + __func__, inst->frame_vbuf[i].size); + goto free_buffers; + } + + inst->frame_buf[i].buf_y = inst->frame_vbuf[i].daddr; + inst->frame_buf[i].buf_cb = (dma_addr_t)-1; + inst->frame_buf[i].buf_cr = (dma_addr_t)-1; + inst->frame_buf[i].update_fb_info = true; + inst->frame_buf[i].size = inst->frame_vbuf[i].size; + } + + ret = wave5_vpu_enc_register_frame_buffer(inst, non_linear_num, fb_stride, + fb_height, COMPRESSED_FRAME_MAP); + if (ret) { + dev_dbg(inst->dev->dev, + "%s: wave5_vpu_enc_register_frame_buffer, fail: %d\n", + __func__, ret); + goto free_buffers; + } + + inst->state = VPU_INST_STATE_PIC_RUN; + } + + if (inst->state == VPU_INST_STATE_INIT_SEQ && + q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + *num_buffers = inst->src_buf_count; + dev_dbg(inst->dev->dev, "%s: src buf num: %u", __func__, *num_buffers); + } + + return 0; + +free_buffers: + for (i = 0; i < inst->min_dst_buf_count; i++) + wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[i]); + return ret; +} + +static void wave5_vpu_enc_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); + struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); + + dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n", + __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), + vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); + + if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + vbuf->sequence = inst->queued_src_buf_num++; + else + vbuf->sequence = inst->queued_dst_buf_num++; + + vpu_buf->consumed = FALSE; + v4l2_m2m_buf_queue(inst->v4l2_fh.m2m_ctx, vbuf); + + if (vb2_start_streaming_called(vb->vb2_queue)) + inst->ops->start_process(inst); +} + +static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q) +{ + struct vpu_instance *inst = vb2_get_drv_priv(q); + struct vb2_v4l2_buffer *buf; + bool check_cmd = true; + + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); + + if (wave5_vpu_both_queues_are_streaming(inst)) + inst->state = VPU_INST_STATE_STOP; + + while (check_cmd) { + struct queue_status_info q_status; + struct enc_output_info enc_output_info; + + wave5_vpu_enc_give_command(inst, ENC_GET_QUEUE_STATUS, &q_status); + + if (q_status.instance_queue_count + q_status.report_queue_count == 0) + break; + + if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) + break; + + if (wave5_vpu_enc_get_output_info(inst, &enc_output_info)) + dev_dbg(inst->dev->dev, "Getting encoding results from fw, fail\n"); + } + + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", + __func__, buf->vb2_buf.type, buf->vb2_buf.index); + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); + } + } else { + while ((buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx))) { + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", + __func__, buf->vb2_buf.type, buf->vb2_buf.index); + vb2_set_plane_payload(&buf->vb2_buf, 0, 0); + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); + } + } +} + +static const struct vb2_ops wave5_vpu_enc_vb2_ops = { + .queue_setup = wave5_vpu_enc_queue_setup, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, + .buf_queue = wave5_vpu_enc_buf_queue, + .stop_streaming = wave5_vpu_enc_stop_streaming, +}; + +static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, + struct v4l2_pix_format_mplane *dst_fmt) +{ + unsigned int src_pix_fmt = enc_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; + const struct v4l2_format_info *src_fmt_info = v4l2_format_info(src_pix_fmt); + + src_fmt->pixelformat = src_pix_fmt; + src_fmt->field = V4L2_FIELD_NONE; + src_fmt->flags = 0; + src_fmt->num_planes = src_fmt_info->mem_planes; + wave5_update_pix_fmt(src_fmt, 416, 240); + + dst_fmt->pixelformat = enc_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; + dst_fmt->field = V4L2_FIELD_NONE; + dst_fmt->flags = 0; + dst_fmt->num_planes = 1; + wave5_update_pix_fmt(dst_fmt, 416, 240); +} + +static int wave5_vpu_enc_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) +{ + return wave5_vpu_queue_init(priv, src_vq, dst_vq, &wave5_vpu_enc_vb2_ops); +} + +static const struct vpu_instance_ops wave5_vpu_enc_inst_ops = { + .start_process = wave5_vpu_enc_start_encode, + .stop_process = wave5_vpu_enc_stop_encode, + .finish_process = wave5_vpu_enc_finish_encode, +}; + +static void wave5_vpu_enc_device_run(void *priv) +{ + struct vpu_instance *inst = priv; + + inst->ops->start_process(inst); +} + +static int wave5_vpu_enc_job_ready(void *priv) +{ + struct vpu_instance *inst = priv; + + if (inst->state == VPU_INST_STATE_STOP) + return 0; + + return 1; +} + +static void wave5_vpu_enc_job_abort(void *priv) +{ + struct vpu_instance *inst = priv; + + inst->ops->stop_process(inst); +} + +static const struct v4l2_m2m_ops wave5_vpu_enc_m2m_ops = { + .device_run = wave5_vpu_enc_device_run, + .job_ready = wave5_vpu_enc_job_ready, + .job_abort = wave5_vpu_enc_job_abort, +}; + +static int wave5_vpu_open_enc(struct file *filp) +{ + struct video_device *vdev = video_devdata(filp); + struct vpu_device *dev = video_drvdata(filp); + struct vpu_instance *inst = NULL; + struct v4l2_ctrl_handler *v4l2_ctrl_hdl; + int ret = 0; + + inst = kzalloc(sizeof(*inst), GFP_KERNEL); + if (!inst) + return -ENOMEM; + v4l2_ctrl_hdl = &inst->v4l2_ctrl_hdl; + + inst->dev = dev; + inst->type = VPU_INST_TYPE_ENC; + inst->ops = &wave5_vpu_enc_inst_ops; + + v4l2_fh_init(&inst->v4l2_fh, vdev); + filp->private_data = &inst->v4l2_fh; + v4l2_fh_add(&inst->v4l2_fh); + + INIT_LIST_HEAD(&inst->list); + list_add_tail(&inst->list, &dev->instances); + + inst->v4l2_m2m_dev = v4l2_m2m_init(&wave5_vpu_enc_m2m_ops); + if (IS_ERR(inst->v4l2_m2m_dev)) { + ret = PTR_ERR(inst->v4l2_m2m_dev); + dev_err(inst->dev->dev, "v4l2_m2m_init, fail: %d\n", ret); + goto cleanup_inst; + } + + inst->v4l2_fh.m2m_ctx = + v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_enc_queue_init); + if (IS_ERR(inst->v4l2_fh.m2m_ctx)) { + ret = PTR_ERR(inst->v4l2_fh.m2m_ctx); + goto cleanup_inst; + } + + v4l2_ctrl_handler_init(v4l2_ctrl_hdl, 50); + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, 0, + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN); + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, + V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 0, + V4L2_MPEG_VIDEO_HEVC_LEVEL_1); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, + 0, 63, 1, 8); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP, + 0, 63, 1, 51); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP, + 0, 63, 1, 30); + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE, + V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, 0, + V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2, + -6, 6, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2, + -6, 6, 1, 0); + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE, + V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR, 0, + V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD, + 0, 2047, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU, + 0, 1, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED, + 0, 1, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT, + 0, 1, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING, + 0, 1, 1, 1); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1, + 1, 2, 1, 2); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION, + 0, 1, 1, 1); + + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_PROFILE, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE, 0, + V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE); + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_LEVEL, + V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 0, + V4L2_MPEG_VIDEO_H264_LEVEL_1_0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_MIN_QP, + 0, 63, 1, 8); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_MAX_QP, + 0, 63, 1, 51); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, + 0, 63, 1, 30); + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, 0, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA, + -6, 6, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA, + -6, 6, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM, + 0, 1, 1, 1); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION, + 0, 1, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET, + -12, 12, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_I_PERIOD, + 0, 2047, 1, 0); + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, 0, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC); + + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_HFLIP, + 0, 1, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_VFLIP, + 0, 1, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_ROTATE, + 0, 270, 90, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_VBV_SIZE, + 10, 3000, 1, 3000); + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_BITRATE_MODE, + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0, + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_BITRATE, + 0, 700000000, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_GOP_SIZE, + 0, 2047, 1, 0); + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE, + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB, 0, + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, + 0, 0xFFFF, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE, + 0, 1, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE, + 0, 1, 1, 0); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1); + + if (v4l2_ctrl_hdl->error) { + ret = -ENODEV; + goto cleanup_inst; + } + + inst->v4l2_fh.ctrl_handler = v4l2_ctrl_hdl; + v4l2_ctrl_handler_setup(v4l2_ctrl_hdl); + + wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); + inst->colorspace = V4L2_COLORSPACE_REC709; + inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; + inst->hsv_enc = 0; + inst->quantization = V4L2_QUANTIZATION_DEFAULT; + inst->xfer_func = V4L2_XFER_FUNC_DEFAULT; + inst->frame_rate = 30; + + init_completion(&inst->irq_done); + ret = kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL); + if (ret) { + dev_err(inst->dev->dev, "Allocating fifo, fail: %d\n", ret); + goto cleanup_inst; + } + + inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); + if (inst->id < 0) { + dev_warn(inst->dev->dev, "Allocating instance ID, fail: %d\n", inst->id); + ret = inst->id; + goto cleanup_inst; + } + + return 0; + +cleanup_inst: + wave5_cleanup_instance(inst); + return ret; +} + +static int wave5_vpu_enc_release(struct file *filp) +{ + return wave5_vpu_release_device(filp, wave5_vpu_enc_close, "encoder"); +} + +static const struct v4l2_file_operations wave5_vpu_enc_fops = { + .owner = THIS_MODULE, + .open = wave5_vpu_open_enc, + .release = wave5_vpu_enc_release, + .unlocked_ioctl = video_ioctl2, + .poll = v4l2_m2m_fop_poll, + .mmap = v4l2_m2m_fop_mmap, +}; + +int wave5_vpu_enc_register_device(struct vpu_device *dev) +{ + struct video_device *vdev_enc; + int ret; + + vdev_enc = devm_kzalloc(dev->v4l2_dev.dev, sizeof(*vdev_enc), GFP_KERNEL); + if (!vdev_enc) + return -ENOMEM; + + dev->video_dev_enc = vdev_enc; + + strscpy(vdev_enc->name, VPU_ENC_DEV_NAME, sizeof(vdev_enc->name)); + vdev_enc->fops = &wave5_vpu_enc_fops; + vdev_enc->ioctl_ops = &wave5_vpu_enc_ioctl_ops; + vdev_enc->release = video_device_release_empty; + vdev_enc->v4l2_dev = &dev->v4l2_dev; + vdev_enc->vfl_dir = VFL_DIR_M2M; + vdev_enc->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; + vdev_enc->lock = &dev->dev_lock; + + ret = video_register_device(vdev_enc, VFL_TYPE_VIDEO, -1); + if (ret) + return ret; + + video_set_drvdata(vdev_enc, dev); + + return 0; +} + +void wave5_vpu_enc_unregister_device(struct vpu_device *dev) +{ + video_unregister_device(dev->video_dev_enc); +} diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers/media/platform/chips-media/wave5/wave5-vpu.c new file mode 100644 index 000000000000..9c602168cffc --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Wave5 series multi-standard codec IP - platform driver + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <linux/of_address.h> +#include <linux/firmware.h> +#include <linux/interrupt.h> +#include "wave5-vpu.h" +#include "wave5-regdefine.h" +#include "wave5-vpuconfig.h" +#include "wave5.h" + +#define VPU_PLATFORM_DEVICE_NAME "vdec" +#define VPU_CLK_NAME "vcodec" + +#define WAVE5_IS_ENC BIT(0) +#define WAVE5_IS_DEC BIT(1) + +struct wave5_match_data { + int flags; + const char *fw_name; +}; + +int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout) +{ + int ret; + + ret = wait_for_completion_timeout(&inst->irq_done, + msecs_to_jiffies(timeout)); + if (!ret) + return -ETIMEDOUT; + + reinit_completion(&inst->irq_done); + + return 0; +} + +static void wave5_vpu_get_interrupt_for_inst(struct vpu_instance *inst, u32 status) +{ + struct vpu_device *dev = inst->dev; + u32 seq_done; + u32 cmd_done; + int val; + + seq_done = wave5_vdi_readl(dev, W5_RET_SEQ_DONE_INSTANCE_INFO); + cmd_done = wave5_vdi_readl(dev, W5_RET_QUEUE_CMD_DONE_INST); + + if (status & BIT(INT_WAVE5_INIT_SEQ)) { + if (seq_done & BIT(inst->id)) { + seq_done &= ~BIT(inst->id); + wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done); + val = BIT(INT_WAVE5_INIT_SEQ); + kfifo_in(&inst->irq_status, &val, sizeof(int)); + } + } + if (status & BIT(INT_WAVE5_ENC_SET_PARAM)) { + if (seq_done & BIT(inst->id)) { + seq_done &= ~BIT(inst->id); + wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done); + val = BIT(INT_WAVE5_ENC_SET_PARAM); + kfifo_in(&inst->irq_status, &val, sizeof(int)); + } + } + if (status & BIT(INT_WAVE5_DEC_PIC) || + status & BIT(INT_WAVE5_ENC_PIC)) { + if (cmd_done & BIT(inst->id)) { + cmd_done &= ~BIT(inst->id); + wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST, cmd_done); + val = BIT(INT_WAVE5_DEC_PIC); + kfifo_in(&inst->irq_status, &val, sizeof(int)); + } + } +} + +static irqreturn_t wave5_vpu_irq(int irq, void *dev_id) +{ + struct vpu_device *dev = dev_id; + + if (wave5_vdi_readl(dev, W5_VPU_VPU_INT_STS)) { + struct vpu_instance *inst; + u32 irq_status = wave5_vdi_readl(dev, W5_VPU_VINT_REASON); + + list_for_each_entry(inst, &dev->instances, list) { + wave5_vpu_get_interrupt_for_inst(inst, irq_status); + } + + wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_status); + wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1); + + return IRQ_WAKE_THREAD; + } + + return IRQ_HANDLED; +} + +static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id) +{ + struct vpu_device *dev = dev_id; + struct vpu_instance *inst; + int irq_status, ret; + u32 val; + + list_for_each_entry(inst, &dev->instances, list) { + while (kfifo_len(&inst->irq_status)) { + struct vpu_instance *curr; + + curr = v4l2_m2m_get_curr_priv(inst->v4l2_m2m_dev); + if (curr) { + inst->ops->finish_process(inst); + } else { + ret = kfifo_out(&inst->irq_status, &irq_status, sizeof(int)); + if (!ret) + break; + + val = wave5_vdi_readl(dev, W5_VPU_VINT_REASON_USR); + val &= ~irq_status; + wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_USR, val); + complete(&inst->irq_done); + } + } + } + + return IRQ_HANDLED; +} + +static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name) +{ + const struct firmware *fw; + int ret; + u32 revision; + unsigned int product_id; + + ret = request_firmware(&fw, fw_name, dev); + if (ret) { + dev_err(dev, "request_firmware, fail: %d\n", ret); + return ret; + } + + ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw->data, fw->size); + if (ret) { + dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret); + goto release_fw; + } + release_firmware(fw); + + ret = wave5_vpu_get_version_info(dev, &revision, &product_id); + if (ret) { + dev_err(dev, "vpu_get_version_info fail: %d\n", ret); + goto err_without_release; + } + + dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n", + __func__, product_id, revision); + + return 0; + +release_fw: + release_firmware(fw); +err_without_release: + return ret; +} + +static int wave5_vpu_probe(struct platform_device *pdev) +{ + int ret; + struct vpu_device *dev; + struct device_node *np; + const struct wave5_match_data *match_data; + struct resource sram; + + match_data = device_get_match_data(&pdev->dev); + if (!match_data) { + dev_err(&pdev->dev, "missing device match data\n"); + return -EINVAL; + } + + /* physical addresses limited to 32 bits */ + dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); + + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + + dev->vdb_register = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dev->vdb_register)) + return PTR_ERR(dev->vdb_register); + ida_init(&dev->inst_ida); + + mutex_init(&dev->dev_lock); + mutex_init(&dev->hw_lock); + dev_set_drvdata(&pdev->dev, dev); + dev->dev = &pdev->dev; + + ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks); + + /* continue without clock, assume externally managed */ + if (ret < 0) { + dev_warn(&pdev->dev, "Getting clocks, fail: %d\n", ret); + ret = 0; + } + dev->num_clks = ret; + + ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks); + if (ret) { + dev_err(&pdev->dev, "Enabling clocks, fail: %d\n", ret); + return ret; + } + + np = of_parse_phandle(pdev->dev.of_node, "sram", 0); + if (!np) { + dev_warn(&pdev->dev, "sram node not found\n"); + } else { + ret = of_address_to_resource(np, 0, &sram); + if (ret) { + dev_err(&pdev->dev, "sram resource not available\n"); + goto err_put_node; + } + dev->sram_buf.daddr = sram.start; + dev->sram_buf.size = resource_size(&sram); + dev_dbg(&pdev->dev, "%s: sram daddr: %pad, size: 0x%lx\n", + __func__, &dev->sram_buf.daddr, dev->sram_buf.size); + } + + dev->product_code = wave5_vdi_readl(dev, VPU_PRODUCT_CODE_REGISTER); + ret = wave5_vdi_init(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "wave5_vdi_init, fail: %d\n", ret); + goto err_clk_dis; + } + dev->product = wave5_vpu_get_product_id(dev); + + INIT_LIST_HEAD(&dev->instances); + ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); + if (ret) { + dev_err(&pdev->dev, "v4l2_device_register, fail: %d\n", ret); + goto err_vdi_release; + } + + if (match_data->flags & WAVE5_IS_DEC) { + ret = wave5_vpu_dec_register_device(dev); + if (ret) { + dev_err(&pdev->dev, "wave5_vpu_dec_register_device, fail: %d\n", ret); + goto err_v4l2_unregister; + } + } + if (match_data->flags & WAVE5_IS_ENC) { + ret = wave5_vpu_enc_register_device(dev); + if (ret) { + dev_err(&pdev->dev, "wave5_vpu_enc_register_device, fail: %d\n", ret); + goto err_dec_unreg; + } + } + + dev->irq = platform_get_irq(pdev, 0); + if (dev->irq < 0) { + dev_err(&pdev->dev, "failed to get irq resource\n"); + ret = -ENXIO; + goto err_enc_unreg; + } + + ret = devm_request_threaded_irq(&pdev->dev, dev->irq, wave5_vpu_irq, + wave5_vpu_irq_thread, 0, "vpu_irq", dev); + if (ret) { + dev_err(&pdev->dev, "Register interrupt handler, fail: %d\n", ret); + goto err_enc_unreg; + } + + ret = wave5_vpu_load_firmware(&pdev->dev, match_data->fw_name); + if (ret) { + dev_err(&pdev->dev, "wave5_vpu_load_firmware, fail: %d\n", ret); + goto err_enc_unreg; + } + + dev_dbg(&pdev->dev, "Added wave5 driver with caps: %s %s and product code: 0x%x\n", + (match_data->flags & WAVE5_IS_ENC) ? "'ENCODE'" : "", + (match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : "", + dev->product_code); + return 0; + +err_enc_unreg: + if (match_data->flags & WAVE5_IS_ENC) + wave5_vpu_enc_unregister_device(dev); +err_dec_unreg: + if (match_data->flags & WAVE5_IS_DEC) + wave5_vpu_dec_unregister_device(dev); +err_v4l2_unregister: + v4l2_device_unregister(&dev->v4l2_dev); +err_vdi_release: + wave5_vdi_release(&pdev->dev); +err_clk_dis: + clk_bulk_disable_unprepare(dev->num_clks, dev->clks); +err_put_node: + of_node_put(np); + + return ret; +} + +static int wave5_vpu_remove(struct platform_device *pdev) +{ + struct vpu_device *dev = dev_get_drvdata(&pdev->dev); + + clk_bulk_disable_unprepare(dev->num_clks, dev->clks); + wave5_vpu_enc_unregister_device(dev); + wave5_vpu_dec_unregister_device(dev); + v4l2_device_unregister(&dev->v4l2_dev); + wave5_vdi_release(&pdev->dev); + ida_destroy(&dev->inst_ida); + + return 0; +} + +static const struct wave5_match_data wave511_data = { + .flags = WAVE5_IS_DEC, + .fw_name = "wave511_dec_fw.bin", +}; + +static const struct wave5_match_data wave521_data = { + .flags = WAVE5_IS_ENC, + .fw_name = "wave521_enc_fw.bin", +}; + +static const struct wave5_match_data wave521c_data = { + .flags = WAVE5_IS_ENC | WAVE5_IS_DEC, + .fw_name = "wave521c_codec_fw.bin", +}; + +static const struct wave5_match_data default_match_data = { + .flags = WAVE5_IS_ENC | WAVE5_IS_DEC, + .fw_name = "chagall.bin", +}; + +static const struct of_device_id wave5_dt_ids[] = { + { .compatible = "cnm,cm511-vpu", .data = &wave511_data }, + { .compatible = "cnm,cm517-vpu", .data = &default_match_data }, + { .compatible = "cnm,cm521-vpu", .data = &wave521_data }, + { .compatible = "cnm,cm521c-vpu", .data = &wave521c_data }, + { .compatible = "cnm,cm521c-dual-vpu", .data = &wave521c_data }, + { .compatible = "cnm,cm521e1-vpu", .data = &default_match_data }, + { .compatible = "cnm,cm537-vpu", .data = &default_match_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, wave5_dt_ids); + +static struct platform_driver wave5_vpu_driver = { + .driver = { + .name = VPU_PLATFORM_DEVICE_NAME, + .of_match_table = of_match_ptr(wave5_dt_ids), + }, + .probe = wave5_vpu_probe, + .remove = wave5_vpu_remove, +}; + +module_platform_driver(wave5_vpu_driver); +MODULE_DESCRIPTION("chips&media VPU V4L2 driver"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.h b/drivers/media/platform/chips-media/wave5/wave5-vpu.h new file mode 100644 index 000000000000..7156d8c3fee4 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ +/* + * Wave5 series multi-standard codec IP - basic types + * + * Copyright (C) 2021 CHIPS&MEDIA INC + */ +#ifndef __VPU_DRV_H__ +#define __VPU_DRV_H__ + +#include <media/v4l2-ctrls.h> +#include <media/v4l2-ioctl.h> +#include <media/v4l2-event.h> +#include <media/v4l2-fh.h> +#include <media/videobuf2-v4l2.h> +#include <media/videobuf2-dma-contig.h> +#include <media/videobuf2-vmalloc.h> +#include "wave5-vpuconfig.h" +#include "wave5-vpuapi.h" + +#define VPU_BUF_SYNC_TO_DEVICE 0 +#define VPU_BUF_SYNC_FROM_DEVICE 1 + +struct vpu_buffer { + struct v4l2_m2m_buffer v4l2_m2m_buf; + bool consumed; +}; + +enum vpu_fmt_type { + VPU_FMT_TYPE_CODEC = 0, + VPU_FMT_TYPE_RAW = 1 +}; + +struct vpu_format { + unsigned int v4l2_pix_fmt; + unsigned int max_width; + unsigned int min_width; + unsigned int max_height; + unsigned int min_height; +}; + +static inline struct vpu_instance *wave5_to_vpu_inst(struct v4l2_fh *vfh) +{ + return container_of(vfh, struct vpu_instance, v4l2_fh); +} + +static inline struct vpu_instance *wave5_ctrl_to_vpu_inst(struct v4l2_ctrl *vctrl) +{ + return container_of(vctrl->handler, struct vpu_instance, v4l2_ctrl_hdl); +} + +static inline struct vpu_buffer *wave5_to_vpu_buf(struct vb2_v4l2_buffer *vbuf) +{ + return container_of(vbuf, struct vpu_buffer, v4l2_m2m_buf.vb); +} + +int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout); + +int wave5_vpu_dec_register_device(struct vpu_device *dev); +void wave5_vpu_dec_unregister_device(struct vpu_device *dev); +int wave5_vpu_enc_register_device(struct vpu_device *dev); +void wave5_vpu_enc_unregister_device(struct vpu_device *dev); +static inline bool wave5_vpu_both_queues_are_streaming(struct vpu_instance *inst) +{ + struct vb2_queue *vq_cap = + v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + struct vb2_queue *vq_out = + v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + + return vb2_is_streaming(vq_cap) && vb2_is_streaming(vq_out); +} + +#endif -- 2.25.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v11 3/6] media: chips-media: wave5: Add the v4l2 layer 2022-12-07 12:13 ` [PATCH v11 3/6] media: chips-media: wave5: Add the v4l2 layer Sebastian Fricke @ 2022-12-12 14:19 ` Hans Verkuil 2023-04-26 13:22 ` Nicolas Dufresne 2023-04-26 14:44 ` Nicolas Dufresne 1 sibling, 1 reply; 22+ messages in thread From: Hans Verkuil @ 2022-12-12 14:19 UTC (permalink / raw) To: Sebastian Fricke, linux-media, Mauro Carvalho Chehab, Nas Chung, Robert Beckett Cc: kernel, nicolas.dufresne, linux-kernel Hi Sebastian, Some review comments below. FYI: if you can post a v12 by Thursday, then I'll run that through my daily build setup to check for smatch, sparse, etc. issues. The next three weeks I'm on vacation, so it will be on hold until I'm back. Regards, Hans On 07/12/2022 13:13, Sebastian Fricke wrote: > From: Nas Chung <nas.chung@chipsnmedia.com> > > Add the decoder and encoder implementing the v4l2 > API. This patch also adds the Makefile and the VIDEO_WAVE_VPU config > > Signed-off-by: Robert Beckett <bob.beckett@collabora.com> > Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> > Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> > Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com> > --- > drivers/media/platform/chips-media/Kconfig | 1 + > drivers/media/platform/chips-media/Makefile | 1 + > .../media/platform/chips-media/wave5/Kconfig | 12 + > .../media/platform/chips-media/wave5/Makefile | 10 + > .../platform/chips-media/wave5/wave5-helper.c | 175 ++ > .../platform/chips-media/wave5/wave5-helper.h | 28 + > .../chips-media/wave5/wave5-vpu-dec.c | 1429 ++++++++++++++ > .../chips-media/wave5/wave5-vpu-enc.c | 1746 +++++++++++++++++ > .../platform/chips-media/wave5/wave5-vpu.c | 362 ++++ > .../platform/chips-media/wave5/wave5-vpu.h | 72 + > 10 files changed, 3836 insertions(+) > create mode 100644 drivers/media/platform/chips-media/wave5/Kconfig > create mode 100644 drivers/media/platform/chips-media/wave5/Makefile > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-helper.c > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-helper.h > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu.c > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu.h > <snip> > +static int wave5_vpu_dec_querycap(struct file *file, void *fh, struct v4l2_capability *cap) > +{ > + strscpy(cap->driver, VPU_DEC_DRV_NAME, sizeof(cap->driver)); > + strscpy(cap->card, VPU_DEC_DRV_NAME, sizeof(cap->card)); > + strscpy(cap->bus_info, "platform:" VPU_DEC_DRV_NAME, sizeof(cap->bus_info)); No need to set bus_info, the core will fill this in for you these days (at least for platform and PCI(e) devices). > + > + return 0; > +} > + > +static int wave5_vpu_dec_enum_framesizes(struct file *f, void *fh, struct v4l2_frmsizeenum *fsize) > +{ > + const struct vpu_format *vpu_fmt; > + > + if (fsize->index) > + return -EINVAL; > + > + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, dec_fmt_list[VPU_FMT_TYPE_CODEC]); > + if (!vpu_fmt) { > + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, dec_fmt_list[VPU_FMT_TYPE_RAW]); > + if (!vpu_fmt) > + return -EINVAL; > + } > + > + fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; > + fsize->stepwise.min_width = vpu_fmt->min_width; > + fsize->stepwise.max_width = vpu_fmt->max_width; > + fsize->stepwise.step_width = 1; > + fsize->stepwise.min_height = vpu_fmt->min_height; > + fsize->stepwise.max_height = vpu_fmt->max_height; > + fsize->stepwise.step_height = 1; > + > + return 0; > +} > + > +static int wave5_vpu_dec_enum_fmt_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f) > +{ > + const struct vpu_format *vpu_fmt; > + > + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, dec_fmt_list[VPU_FMT_TYPE_RAW]); > + if (!vpu_fmt) > + return -EINVAL; > + > + f->pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->flags = 0; > + > + return 0; > +} > + > +static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, > + "%s: fourcc: %u width: %u height: %u nm planes: %u colorspace: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); > + > + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) > + return -EINVAL; > + > + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_RAW]); > + if (!vpu_fmt) { > + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; > + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; > + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height); > + } else { > + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); > + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); > + const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); > + > + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->fmt.pix_mp.num_planes = info->mem_planes; > + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); > + } > + > + f->fmt.pix_mp.flags = 0; > + f->fmt.pix_mp.field = V4L2_FIELD_NONE; > + f->fmt.pix_mp.colorspace = inst->colorspace; > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > + f->fmt.pix_mp.quantization = inst->quantization; > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); > + > + return 0; > +} > + > +static int wave5_vpu_dec_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i, ret; > + > + dev_dbg(inst->dev->dev, > + "%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); > + > + ret = wave5_vpu_dec_try_fmt_cap(file, fh, f); > + if (ret) > + return ret; > + > + inst->dst_fmt.width = f->fmt.pix_mp.width; > + inst->dst_fmt.height = f->fmt.pix_mp.height; > + inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat; > + inst->dst_fmt.field = f->fmt.pix_mp.field; > + inst->dst_fmt.flags = f->fmt.pix_mp.flags; > + inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes; > + for (i = 0; i < inst->dst_fmt.num_planes; i++) { > + inst->dst_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; > + inst->dst_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; > + } > + > + if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12 || > + inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12M) { > + inst->cbcr_interleave = true; > + inst->nv21 = false; > + } else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21 || > + inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21M) { > + inst->cbcr_interleave = true; > + inst->nv21 = true; > + } else { > + inst->cbcr_interleave = false; > + inst->nv21 = false; > + } > + > + return 0; > +} > + > +static int wave5_vpu_dec_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i; > + > + f->fmt.pix_mp.width = inst->dst_fmt.width; > + f->fmt.pix_mp.height = inst->dst_fmt.height; > + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; > + f->fmt.pix_mp.field = inst->dst_fmt.field; > + f->fmt.pix_mp.flags = inst->dst_fmt.flags; > + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; > + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { > + f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->dst_fmt.plane_fmt[i].bytesperline; > + f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->dst_fmt.plane_fmt[i].sizeimage; > + } > + > + f->fmt.pix_mp.colorspace = inst->colorspace; > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > + f->fmt.pix_mp.quantization = inst->quantization; > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > + > + return 0; > +} > + > +static int wave5_vpu_dec_enum_fmt_out(struct file *file, void *fh, struct v4l2_fmtdesc *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); > + > + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, dec_fmt_list[VPU_FMT_TYPE_CODEC]); > + if (!vpu_fmt) > + return -EINVAL; > + > + f->pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->flags = 0; > + > + return 0; > +} > + > +static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, > + "%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); > + > + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + return -EINVAL; > + > + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_CODEC]); > + if (!vpu_fmt) { > + f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; > + f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; > + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height); > + } else { > + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); > + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); > + > + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->fmt.pix_mp.num_planes = 1; > + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); > + } > + > + f->fmt.pix_mp.flags = 0; > + f->fmt.pix_mp.field = V4L2_FIELD_NONE; > + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); > + > + return 0; > +} > + > +static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i, ret; > + > + dev_dbg(inst->dev->dev, > + "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > + > + ret = wave5_vpu_dec_try_fmt_out(file, fh, f); > + if (ret) > + return ret; > + > + inst->src_fmt.width = f->fmt.pix_mp.width; > + inst->src_fmt.height = f->fmt.pix_mp.height; > + inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat; > + inst->src_fmt.field = f->fmt.pix_mp.field; > + inst->src_fmt.flags = f->fmt.pix_mp.flags; > + inst->src_fmt.num_planes = f->fmt.pix_mp.num_planes; > + for (i = 0; i < inst->src_fmt.num_planes; i++) { > + inst->src_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; > + inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; > + } > + > + inst->colorspace = f->fmt.pix_mp.colorspace; > + inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; > + inst->hsv_enc = f->fmt.pix_mp.hsv_enc; > + inst->quantization = f->fmt.pix_mp.quantization; > + inst->xfer_func = f->fmt.pix_mp.xfer_func; > + > + wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height); > + > + return 0; > +} > + > +static int wave5_vpu_dec_g_selection(struct file *file, void *fh, struct v4l2_selection *s) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + > + dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target); > + > + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) > + return -EINVAL; > + switch (s->target) { > + case V4L2_SEL_TGT_COMPOSE_BOUNDS: > + case V4L2_SEL_TGT_COMPOSE_PADDED: > + s->r.left = 0; > + s->r.top = 0; > + s->r.width = inst->dst_fmt.width; > + s->r.height = inst->dst_fmt.height; > + break; > + case V4L2_SEL_TGT_COMPOSE: > + case V4L2_SEL_TGT_COMPOSE_DEFAULT: > + s->r.left = 0; > + s->r.top = 0; > + if (inst->state > VPU_INST_STATE_OPEN) { > + s->r.width = inst->conf_win_width; > + s->r.height = inst->conf_win_height; > + } else { > + s->r.width = inst->src_fmt.width; > + s->r.height = inst->src_fmt.height; > + } > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int wave5_vpu_dec_s_selection(struct file *file, void *fh, struct v4l2_selection *s) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + > + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) > + return -EINVAL; > + > + if (s->target != V4L2_SEL_TGT_COMPOSE) > + return -EINVAL; > + > + dev_dbg(inst->dev->dev, "V4L2_SEL_TGT_COMPOSE w: %u h: %u\n", > + s->r.width, s->r.height); > + > + s->r.left = 0; > + s->r.top = 0; > + s->r.width = inst->dst_fmt.width; > + s->r.height = inst->dst_fmt.height; > + > + return 0; > +} > + > +static int wave5_vpu_dec_decoder_cmd(struct file *file, void *fh, struct v4l2_decoder_cmd *dc) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int ret; > + > + dev_dbg(inst->dev->dev, "decoder command: %u\n", dc->cmd); > + > + ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc); > + if (ret) > + return ret; > + > + if (!wave5_vpu_both_queues_are_streaming(inst)) > + return 0; > + > + switch (dc->cmd) { > + case V4L2_DEC_CMD_STOP: > + inst->state = VPU_INST_STATE_STOP; > + > + ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0); > + if (ret) { > + dev_err(inst->dev->dev, > + "Setting EOS for the bitstream, fail: %d\n", ret); > + return ret; > + } > + break; > + case V4L2_DEC_CMD_START: > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static const struct v4l2_ioctl_ops wave5_vpu_dec_ioctl_ops = { > + .vidioc_querycap = wave5_vpu_dec_querycap, > + .vidioc_enum_framesizes = wave5_vpu_dec_enum_framesizes, > + > + .vidioc_enum_fmt_vid_cap = wave5_vpu_dec_enum_fmt_cap, > + .vidioc_s_fmt_vid_cap_mplane = wave5_vpu_dec_s_fmt_cap, > + .vidioc_g_fmt_vid_cap_mplane = wave5_vpu_dec_g_fmt_cap, > + .vidioc_try_fmt_vid_cap_mplane = wave5_vpu_dec_try_fmt_cap, > + > + .vidioc_enum_fmt_vid_out = wave5_vpu_dec_enum_fmt_out, > + .vidioc_s_fmt_vid_out_mplane = wave5_vpu_dec_s_fmt_out, > + .vidioc_g_fmt_vid_out_mplane = wave5_vpu_g_fmt_out, > + .vidioc_try_fmt_vid_out_mplane = wave5_vpu_dec_try_fmt_out, > + > + .vidioc_g_selection = wave5_vpu_dec_g_selection, > + .vidioc_s_selection = wave5_vpu_dec_s_selection, > + > + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, > + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, > + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, > + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, > + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, > + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, > + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, > + .vidioc_streamon = v4l2_m2m_ioctl_streamon, > + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, > + > + .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd, > + .vidioc_decoder_cmd = wave5_vpu_dec_decoder_cmd, > + > + .vidioc_subscribe_event = wave5_vpu_subscribe_event, > + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, > +}; > + > +static int wave5_vpu_dec_s_ctrl(struct v4l2_ctrl *ctrl) > +{ > + struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl); > + > + dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n", > + __func__, ctrl->name, ctrl->val); > + > + switch (ctrl->id) { > + case V4L2_CID_VPU_THUMBNAIL_MODE: > + inst->thumbnail_mode = ctrl->val; > + break; > + case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE: > + break; This case can be dropped: this control is a read-only control, so it can never be set and this op will never be called. > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static const struct v4l2_ctrl_ops wave5_vpu_dec_ctrl_ops = { > + .s_ctrl = wave5_vpu_dec_s_ctrl, > +}; > + > +static const struct v4l2_ctrl_config wave5_vpu_thumbnail_mode = { > + .ops = &wave5_vpu_dec_ctrl_ops, > + .id = V4L2_CID_VPU_THUMBNAIL_MODE, > + .name = "thumbnail mode", Capitalize: "Thumbnail Mode". It's not documented, so that needs to be added. Document it either in Documentation/userspace-api/media/drivers or in a public header where this control is defined (see e.g. include/uapi/linux/aspeed-video.h). Also, it's defined as: #define V4L2_CID_VPU_THUMBNAIL_MODE (V4L2_CID_USER_BASE + 0x1001) But you need to reserve a range of controls for this driver in include/uapi/linux/v4l2-controls.h (see e.g. V4L2_CID_USER_ASPEED_BASE). > + .type = V4L2_CTRL_TYPE_BOOLEAN, > + .def = 0, > + .min = 0, > + .max = 1, > + .step = 1, > + .flags = V4L2_CTRL_FLAG_WRITE_ONLY, Why is this WRITE_ONLY? That's weird. > +}; > + > +static void wave5_set_default_dec_openparam(struct dec_open_param *open_param) > +{ > + open_param->bitstream_mode = BS_MODE_INTERRUPT; > + open_param->stream_endian = VPU_STREAM_ENDIAN; > + open_param->frame_endian = VPU_FRAME_ENDIAN; > +} > + > +static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, > + unsigned int *num_planes, unsigned int sizes[], > + struct device *alloc_devs[]) > +{ > + struct vpu_instance *inst = vb2_get_drv_priv(q); > + struct v4l2_pix_format_mplane inst_format = > + (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; > + unsigned int i; > + int ret; > + > + dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, > + *num_buffers, *num_planes, q->type); > + > + if (*num_planes) { > + if (inst_format.num_planes != *num_planes) > + return -EINVAL; > + > + for (i = 0; i < *num_planes; i++) { > + if (sizes[i] < inst_format.plane_fmt[i].sizeimage) > + return -EINVAL; > + } > + } else { > + *num_planes = inst_format.num_planes; > + > + if (*num_planes == 1) { > + sizes[0] = inst_format.width * inst_format.height * 3 / 2; > + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + sizes[0] = inst_format.plane_fmt[0].sizeimage; > + dev_dbg(inst->dev->dev, "%s: size[0]: %u\n", __func__, sizes[0]); > + } else if (*num_planes == 2) { > + sizes[0] = inst_format.width * inst_format.height; > + sizes[1] = inst_format.width * inst_format.height / 2; > + dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u\n", > + __func__, sizes[0], sizes[1]); > + } else if (*num_planes == 3) { > + sizes[0] = inst_format.width * inst_format.height; > + sizes[1] = inst_format.width * inst_format.height / 4; > + sizes[2] = inst_format.width * inst_format.height / 4; > + dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u | size[2]: %u\n", > + __func__, sizes[0], sizes[1], sizes[2]); > + } > + } > + So what happens below if you call REQBUFS followed by CREATE_BUFS some time later? I'm not sure if this is all correct. Certainly the last else doesn't look right to me. > + if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > + struct dec_open_param open_param; > + > + memset(&open_param, 0, sizeof(struct dec_open_param)); > + wave5_set_default_dec_openparam(&open_param); > + > + inst->bitstream_vbuf.size = ALIGN(inst->src_fmt.plane_fmt[0].sizeimage, 1024) * 4; > + ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->bitstream_vbuf); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: alloc bitstream of size %zu fail: %d\n", > + __func__, inst->bitstream_vbuf.size, ret); > + return ret; > + } > + > + inst->std = wave5_to_vpu_codstd(inst->src_fmt.pixelformat); > + if (inst->std == STD_UNKNOWN) { > + dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", > + (char *)&inst->src_fmt.pixelformat); > + ret = -EINVAL; > + goto free_bitstream_vbuf; > + } > + open_param.bitstream_buffer = inst->bitstream_vbuf.daddr; > + open_param.bitstream_buffer_size = inst->bitstream_vbuf.size; > + > + ret = wave5_vpu_dec_open(inst, &open_param); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_open, fail: %d\n", > + __func__, ret); > + goto free_bitstream_vbuf; > + } > + > + inst->state = VPU_INST_STATE_OPEN; > + > + if (inst->thumbnail_mode) > + wave5_vpu_dec_give_command(inst, ENABLE_DEC_THUMBNAIL_MODE, NULL); > + > + } else if (inst->state == VPU_INST_STATE_INIT_SEQ && > + q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { I'm fairly certain you can get here twice by calling CREATE_BUFS while already streaming. > + u32 non_linear_num; > + u32 fb_stride, fb_height; > + u32 luma_size, chroma_size; > + > + if (*num_buffers > inst->min_dst_buf_count && > + *num_buffers < WAVE5_MAX_FBS) Since this driver supports create_bufs, the correct check here is q->num_buffers + *num_buffers. > + inst->dst_buf_count = *num_buffers; I think this is set too early, if there is an error below, then dst_buf_count has been updated, when it shouldn't. > + > + *num_buffers = inst->dst_buf_count; > + non_linear_num = inst->dst_buf_count; > + > + for (i = 0; i < non_linear_num; i++) { > + struct frame_buffer *frame = &inst->frame_buf[i]; > + struct vpu_buf *vframe = &inst->frame_vbuf[i]; > + > + fb_stride = inst->dst_fmt.width; > + fb_height = ALIGN(inst->dst_fmt.height, 32); > + luma_size = fb_stride * fb_height; > + chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; > + > + vframe->size = luma_size + chroma_size; > + ret = wave5_vdi_allocate_dma_memory(inst->dev, vframe); > + if (ret) { > + dev_dbg(inst->dev->dev, > + "%s: Allocating FBC buf of size %zu, fail: %d\n", > + __func__, vframe->size, ret); Shouldn't earlier allocs that succeeded be freed here? > + return ret; > + } > + > + frame->buf_y = vframe->daddr; > + frame->buf_cb = vframe->daddr + luma_size; > + frame->buf_cr = (dma_addr_t)-1; > + frame->size = vframe->size; > + frame->width = inst->src_fmt.width; > + frame->stride = fb_stride; > + frame->map_type = COMPRESSED_FRAME_MAP; > + frame->update_fb_info = true; > + } > + } else if (inst->state == VPU_INST_STATE_STOP && > + q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { > + *num_buffers = 0; Why? It's odd anyway, you can do a STREAMON, stream for a while, then STREAMOFF, add more buffers and do STREAMON again. I'm not sure this will work in this driver. > + } > + > + return 0; > + > +free_bitstream_vbuf: > + wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf); > + return ret; > +} > + > +static int wave5_vpu_dec_start_streaming_open(struct vpu_instance *inst) > +{ > + struct dec_initial_info initial_info; > + int ret = 0; > + > + memset(&initial_info, 0, sizeof(struct dec_initial_info)); > + > + ret = wave5_vpu_dec_issue_seq_init(inst); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_issue_seq_init, fail: %d\n", > + __func__, ret); > + return ret; > + } > + > + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) > + dev_dbg(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__); > + > + ret = wave5_vpu_dec_complete_seq_init(inst, &initial_info); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: vpu_dec_complete_seq_init, fail: %d, reason: %u\n", > + __func__, ret, initial_info.seq_init_err_reason); > + } else { > + static const struct v4l2_event vpu_event_src_ch = { > + .type = V4L2_EVENT_SOURCE_CHANGE, > + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, > + }; > + struct v4l2_ctrl *ctrl; > + > + dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n", > + __func__, initial_info.pic_width, initial_info.pic_height, > + initial_info.profile, initial_info.min_frame_buffer_count); > + > + inst->state = VPU_INST_STATE_INIT_SEQ; > + inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1; > + inst->dst_buf_count = inst->min_dst_buf_count; > + > + inst->conf_win_width = initial_info.pic_width - initial_info.pic_crop_rect.right; > + inst->conf_win_height = initial_info.pic_height - initial_info.pic_crop_rect.bottom; > + > + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, > + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE); > + if (ctrl) > + v4l2_ctrl_s_ctrl(ctrl, inst->min_dst_buf_count); > + > + if (initial_info.pic_width != inst->src_fmt.width || > + initial_info.pic_height != inst->src_fmt.height) { > + wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width, > + initial_info.pic_height); > + wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width, > + initial_info.pic_height); > + } > + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch); > + > + wave5_handle_src_buffer(inst); > + } > + > + return ret; > +} > + > +static int wave5_vpu_dec_start_streaming_seek(struct vpu_instance *inst) > +{ > + struct dec_initial_info initial_info; > + struct dec_param pic_param; > + struct dec_output_info dec_output_info; > + int ret = 0; > + u32 fail_res = 0; > + > + memset(&pic_param, 0, sizeof(struct dec_param)); > + > + ret = wave5_vpu_dec_start_one_frame(inst, &pic_param, &fail_res); > + if (ret && fail_res != WAVE5_SYSERR_QUEUEING_FAIL) { > + struct vb2_v4l2_buffer *src_buf; > + > + src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); > + inst->state = VPU_INST_STATE_STOP; > + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_start_one_frame\n", __func__); > + return ret; > + } > + > + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) > + dev_dbg(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__); > + > + ret = wave5_vpu_dec_get_output_info(inst, &dec_output_info); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_get_output_info, fail: %d\n", > + __func__, ret); > + return ret; > + } > + > + if (dec_output_info.sequence_changed) { > + static const struct v4l2_event vpu_event_src_ch = { > + .type = V4L2_EVENT_SOURCE_CHANGE, > + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, > + }; > + struct v4l2_ctrl *ctrl; > + > + wave5_vpu_dec_give_command(inst, DEC_RESET_FRAMEBUF_INFO, NULL); > + wave5_vpu_dec_give_command(inst, DEC_GET_SEQ_INFO, &initial_info); > + > + dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n", > + __func__, initial_info.pic_width, initial_info.pic_height, > + initial_info.profile, initial_info.min_frame_buffer_count); > + > + inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1; > + inst->dst_buf_count = inst->min_dst_buf_count; > + > + inst->conf_win_width = initial_info.pic_width - initial_info.pic_crop_rect.right; > + inst->conf_win_height = initial_info.pic_height - initial_info.pic_crop_rect.bottom; > + > + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, > + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE); > + if (ctrl) > + v4l2_ctrl_s_ctrl(ctrl, inst->min_dst_buf_count); > + > + if (initial_info.pic_width != inst->src_fmt.width || > + initial_info.pic_height != inst->src_fmt.height) { > + wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width, > + initial_info.pic_height); > + wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width, > + initial_info.pic_height); > + } > + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch); > + > + wave5_handle_src_buffer(inst); > + } > + > + return ret; > +} > + > +static void wave5_vpu_dec_buf_queue_src(struct vb2_buffer *vb) > +{ > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); > + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); > + struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); > + > + vpu_buf->consumed = false; > + vbuf->sequence = inst->queued_src_buf_num++; > + > + if (inst->state == VPU_INST_STATE_PIC_RUN) { > + wave5_handle_bitstream_buffer(inst); > + inst->ops->start_process(inst); > + } > +} > + > +static void wave5_vpu_dec_buf_queue_dst(struct vb2_buffer *vb) > +{ > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); > + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); > + int ret; > + > + vbuf->sequence = inst->queued_dst_buf_num++; > + ret = wave5_vpu_dec_clr_disp_flag(inst, vb->index); > + if (ret) { > + dev_dbg(inst->dev->dev, > + "%s: Clearing the display flag of buffer index: %u, fail: %d\n", > + __func__, vb->index, ret); > + } > + > + if (inst->state == VPU_INST_STATE_INIT_SEQ) { > + dma_addr_t buf_addr_y = 0, buf_addr_cb = 0, buf_addr_cr = 0; > + u32 buf_size = 0; > + u32 non_linear_num = inst->dst_buf_count; > + u32 fb_stride = inst->dst_fmt.width; > + u32 luma_size = fb_stride * inst->dst_fmt.height; > + u32 chroma_size = (fb_stride / 2) * (inst->dst_fmt.height / 2); > + > + if (inst->dst_fmt.num_planes == 1) { > + buf_size = vb2_plane_size(&vbuf->vb2_buf, 0); > + buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); > + buf_addr_cb = buf_addr_y + luma_size; > + buf_addr_cr = buf_addr_cb + chroma_size; > + } else if (inst->dst_fmt.num_planes == 2) { > + buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) + > + vb2_plane_size(&vbuf->vb2_buf, 1); > + buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); > + buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1); > + buf_addr_cr = buf_addr_cb + chroma_size; > + } else if (inst->dst_fmt.num_planes == 3) { > + buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) + > + vb2_plane_size(&vbuf->vb2_buf, 1) + > + vb2_plane_size(&vbuf->vb2_buf, 2); > + buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); > + buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1); > + buf_addr_cr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 2); > + } > + inst->frame_buf[vb->index + non_linear_num].buf_y = buf_addr_y; > + inst->frame_buf[vb->index + non_linear_num].buf_cb = buf_addr_cb; > + inst->frame_buf[vb->index + non_linear_num].buf_cr = buf_addr_cr; > + inst->frame_buf[vb->index + non_linear_num].size = buf_size; > + inst->frame_buf[vb->index + non_linear_num].width = inst->src_fmt.width; > + inst->frame_buf[vb->index + non_linear_num].stride = fb_stride; > + inst->frame_buf[vb->index + non_linear_num].map_type = LINEAR_FRAME_MAP; > + inst->frame_buf[vb->index + non_linear_num].update_fb_info = true; > + } > + > + if (!vb2_is_streaming(vb->vb2_queue)) > + return; > + > + if (inst->state == VPU_INST_STATE_STOP && inst->eos == FALSE) > + inst->ops->start_process(inst); > +} > + > +static void wave5_vpu_dec_buf_queue(struct vb2_buffer *vb) > +{ > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); > + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); > + > + dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n", > + __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), > + vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); > + > + v4l2_m2m_buf_queue(inst->v4l2_fh.m2m_ctx, vbuf); > + > + if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + wave5_vpu_dec_buf_queue_src(vb); > + else if (vb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) > + wave5_vpu_dec_buf_queue_dst(vb); > +} > + > +static int wave5_vpu_dec_start_streaming(struct vb2_queue *q, unsigned int count) > +{ > + struct vpu_instance *inst = vb2_get_drv_priv(q); > + int ret = 0; > + > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); > + > + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > + wave5_handle_bitstream_buffer(inst); > + if (inst->state == VPU_INST_STATE_OPEN) > + ret = wave5_vpu_dec_start_streaming_open(inst); > + else if (inst->state == VPU_INST_STATE_INIT_SEQ) > + ret = wave5_vpu_dec_start_streaming_seek(inst); > + > + if (ret) { > + struct vb2_v4l2_buffer *buf; > + > + while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { > + dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4d | index %4d\n", > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_QUEUED); > + } > + } > + } > + > + return ret; > +} > + > +static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q) > +{ > + struct vpu_instance *inst = vb2_get_drv_priv(q); > + struct vb2_v4l2_buffer *buf; > + bool check_cmd = TRUE; > + > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); > + > + while (check_cmd) { > + struct queue_status_info q_status; > + struct dec_output_info dec_output_info; > + > + wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status); > + > + if (q_status.instance_queue_count + q_status.report_queue_count == 0) > + break; > + > + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) > + break; > + > + if (wave5_vpu_dec_get_output_info(inst, &dec_output_info)) > + dev_dbg(inst->dev->dev, "Getting decoding results from fw, fail\n"); > + } > + > + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > + while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { > + dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4u | index %4u\n", > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); > + } > + inst->queued_src_buf_num = 0; > + } else { > + unsigned int i; > + int ret; > + dma_addr_t rd_ptr, wr_ptr; > + > + while ((buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx))) { > + u32 plane; > + > + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > + > + for (plane = 0; plane < inst->dst_fmt.num_planes; plane++) > + vb2_set_plane_payload(&buf->vb2_buf, plane, 0); > + > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); > + } > + > + for (i = 0; i < inst->dst_buf_count; i++) { > + ret = wave5_vpu_dec_set_disp_flag(inst, i); > + if (ret) { > + dev_dbg(inst->dev->dev, > + "%s: Setting display flag of buf index: %u, fail: %d\n", > + __func__, i, ret); > + } > + } > + > + ret = wave5_vpu_dec_get_bitstream_buffer(inst, &rd_ptr, &wr_ptr, NULL); > + if (ret) { > + dev_err(inst->dev->dev, > + "Getting bitstream buf, fail: %d\n", ret); > + return; > + } > + ret = wave5_vpu_dec_set_rd_ptr(inst, wr_ptr, TRUE); > + if (ret) { > + dev_err(inst->dev->dev, > + "Setting read pointer for the decoder, fail: %d\n", ret); > + return; > + } > + if (inst->eos) { > + inst->eos = FALSE; > + inst->state = VPU_INST_STATE_INIT_SEQ; > + } > + inst->queued_dst_buf_num = 0; > + } > +} > + > +static const struct vb2_ops wave5_vpu_dec_vb2_ops = { > + .queue_setup = wave5_vpu_dec_queue_setup, > + .wait_prepare = vb2_ops_wait_prepare, > + .wait_finish = vb2_ops_wait_finish, > + .buf_queue = wave5_vpu_dec_buf_queue, > + .start_streaming = wave5_vpu_dec_start_streaming, > + .stop_streaming = wave5_vpu_dec_stop_streaming, > +}; > + > +static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, > + struct v4l2_pix_format_mplane *dst_fmt) > +{ > + unsigned int dst_pix_fmt = dec_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; > + const struct v4l2_format_info *dst_fmt_info = v4l2_format_info(dst_pix_fmt); > + > + src_fmt->pixelformat = dec_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; > + src_fmt->field = V4L2_FIELD_NONE; > + src_fmt->flags = 0; > + src_fmt->num_planes = 1; > + wave5_update_pix_fmt(src_fmt, 720, 480); > + > + dst_fmt->pixelformat = dst_pix_fmt; > + dst_fmt->field = V4L2_FIELD_NONE; > + dst_fmt->flags = 0; > + dst_fmt->num_planes = dst_fmt_info->mem_planes; > + wave5_update_pix_fmt(dst_fmt, 736, 480); > +} > + > +static int wave5_vpu_dec_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) > +{ > + return wave5_vpu_queue_init(priv, src_vq, dst_vq, &wave5_vpu_dec_vb2_ops); > +} > + > +static const struct vpu_instance_ops wave5_vpu_dec_inst_ops = { > + .start_process = wave5_vpu_dec_start_decode, > + .stop_process = wave5_vpu_dec_stop_decode, > + .finish_process = wave5_vpu_dec_finish_decode, > +}; > + > +static void wave5_vpu_dec_device_run(void *priv) > +{ > + struct vpu_instance *inst = priv; > + > + inst->ops->start_process(inst); > + > + inst->state = VPU_INST_STATE_PIC_RUN; > +} > + > +static void wave5_vpu_dec_job_abort(void *priv) > +{ > + struct vpu_instance *inst = priv; > + > + inst->ops->stop_process(inst); > +} > + > +static const struct v4l2_m2m_ops wave5_vpu_dec_m2m_ops = { > + .device_run = wave5_vpu_dec_device_run, > + .job_abort = wave5_vpu_dec_job_abort, > +}; > + > +static int wave5_vpu_open_dec(struct file *filp) > +{ > + struct video_device *vdev = video_devdata(filp); > + struct vpu_device *dev = video_drvdata(filp); > + struct vpu_instance *inst = NULL; > + int ret = 0; > + > + inst = kzalloc(sizeof(*inst), GFP_KERNEL); > + if (!inst) > + return -ENOMEM; > + > + inst->dev = dev; > + inst->type = VPU_INST_TYPE_DEC; > + inst->ops = &wave5_vpu_dec_inst_ops; > + > + v4l2_fh_init(&inst->v4l2_fh, vdev); > + filp->private_data = &inst->v4l2_fh; > + v4l2_fh_add(&inst->v4l2_fh); > + > + INIT_LIST_HEAD(&inst->list); > + list_add_tail(&inst->list, &dev->instances); > + > + inst->v4l2_m2m_dev = v4l2_m2m_init(&wave5_vpu_dec_m2m_ops); > + if (IS_ERR(inst->v4l2_m2m_dev)) { > + ret = PTR_ERR(inst->v4l2_m2m_dev); > + dev_err(inst->dev->dev, "v4l2_m2m_init, fail: %d\n", ret); > + goto cleanup_inst; > + } > + > + inst->v4l2_fh.m2m_ctx = > + v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_dec_queue_init); > + if (IS_ERR(inst->v4l2_fh.m2m_ctx)) { > + ret = PTR_ERR(inst->v4l2_fh.m2m_ctx); > + goto cleanup_inst; > + } > + > + v4l2_ctrl_handler_init(&inst->v4l2_ctrl_hdl, 10); > + v4l2_ctrl_new_custom(&inst->v4l2_ctrl_hdl, &wave5_vpu_thumbnail_mode, NULL); > + v4l2_ctrl_new_std(&inst->v4l2_ctrl_hdl, &wave5_vpu_dec_ctrl_ops, > + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 1); > + > + if (inst->v4l2_ctrl_hdl.error) { > + ret = -ENODEV; > + goto cleanup_inst; > + } > + > + inst->v4l2_fh.ctrl_handler = &inst->v4l2_ctrl_hdl; > + v4l2_ctrl_handler_setup(&inst->v4l2_ctrl_hdl); > + > + wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); > + inst->colorspace = V4L2_COLORSPACE_REC709; > + inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; > + inst->hsv_enc = 0; > + inst->quantization = V4L2_QUANTIZATION_DEFAULT; > + inst->xfer_func = V4L2_XFER_FUNC_DEFAULT; > + > + init_completion(&inst->irq_done); > + ret = kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL); > + if (ret) { > + dev_err(inst->dev->dev, "failed to allocate fifo\n"); > + goto cleanup_inst; > + } > + > + inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); > + if (inst->id < 0) { > + dev_warn(inst->dev->dev, "Allocating instance ID, fail: %d\n", inst->id); > + ret = inst->id; > + goto cleanup_inst; > + } > + > + return 0; > + > +cleanup_inst: > + wave5_cleanup_instance(inst); > + return ret; > +} > + > +static int wave5_vpu_dec_release(struct file *filp) > +{ > + return wave5_vpu_release_device(filp, wave5_vpu_dec_close, "decoder"); > +} > + > +static const struct v4l2_file_operations wave5_vpu_dec_fops = { > + .owner = THIS_MODULE, > + .open = wave5_vpu_open_dec, > + .release = wave5_vpu_dec_release, > + .unlocked_ioctl = video_ioctl2, > + .poll = v4l2_m2m_fop_poll, > + .mmap = v4l2_m2m_fop_mmap, > +}; > + > +int wave5_vpu_dec_register_device(struct vpu_device *dev) > +{ > + struct video_device *vdev_dec; > + int ret; > + > + vdev_dec = devm_kzalloc(dev->v4l2_dev.dev, sizeof(*vdev_dec), GFP_KERNEL); > + if (!vdev_dec) > + return -ENOMEM; > + > + dev->video_dev_dec = vdev_dec; > + > + strscpy(vdev_dec->name, VPU_DEC_DEV_NAME, sizeof(vdev_dec->name)); > + vdev_dec->fops = &wave5_vpu_dec_fops; > + vdev_dec->ioctl_ops = &wave5_vpu_dec_ioctl_ops; > + vdev_dec->release = video_device_release_empty; > + vdev_dec->v4l2_dev = &dev->v4l2_dev; > + vdev_dec->vfl_dir = VFL_DIR_M2M; > + vdev_dec->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; > + vdev_dec->lock = &dev->dev_lock; > + > + ret = video_register_device(vdev_dec, VFL_TYPE_VIDEO, -1); > + if (ret) > + return ret; > + > + video_set_drvdata(vdev_dec, dev); > + > + return 0; > +} > + > +void wave5_vpu_dec_unregister_device(struct vpu_device *dev) > +{ > + video_unregister_device(dev->video_dev_dec); > +} > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c > new file mode 100644 > index 000000000000..285111c2d9cd > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c > @@ -0,0 +1,1746 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > +/* > + * Wave5 series multi-standard codec IP - encoder interface > + * > + * Copyright (C) 2021 CHIPS&MEDIA INC > + */ > + > +#include "wave5-helper.h" > + > +#define VPU_ENC_DEV_NAME "C&M Wave5 VPU encoder" > +#define VPU_ENC_DRV_NAME "wave5-enc" > + > +static const struct vpu_format enc_fmt_list[FMT_TYPES][MAX_FMTS] = { > + [VPU_FMT_TYPE_CODEC] = { > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_HEVC, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_H264, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + }, > + [VPU_FMT_TYPE_RAW] = { > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV12, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV21, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV12M, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + } > +}; > + > +static enum wave_std wave5_to_vpu_wavestd(unsigned int v4l2_pix_fmt) > +{ > + switch (v4l2_pix_fmt) { > + case V4L2_PIX_FMT_H264: > + return W_AVC_ENC; > + case V4L2_PIX_FMT_HEVC: > + return W_HEVC_ENC; > + default: > + return STD_UNKNOWN; > + } > +} > + > +static struct vb2_v4l2_buffer *wave5_get_valid_src_buf(struct vpu_instance *inst) > +{ > + struct v4l2_m2m_buffer *v4l2_m2m_buf; > + > + v4l2_m2m_for_each_src_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { > + struct vb2_v4l2_buffer *vb2_v4l2_buf; > + struct vpu_buffer *vpu_buf = NULL; > + > + vb2_v4l2_buf = &v4l2_m2m_buf->vb; > + vpu_buf = wave5_to_vpu_buf(vb2_v4l2_buf); > + > + if (!vpu_buf->consumed) { > + dev_dbg(inst->dev->dev, "%s: src buf (index: %u) has not been consumed\n", > + __func__, vb2_v4l2_buf->vb2_buf.index); > + return vb2_v4l2_buf; > + } > + } > + > + return NULL; > +} > + > +static struct vb2_v4l2_buffer *wave5_get_valid_dst_buf(struct vpu_instance *inst) > +{ > + struct v4l2_m2m_buffer *v4l2_m2m_buf; > + > + v4l2_m2m_for_each_dst_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { > + struct vb2_v4l2_buffer *vb2_v4l2_buf; > + struct vpu_buffer *vpu_buf = NULL; > + > + vb2_v4l2_buf = &v4l2_m2m_buf->vb; > + vpu_buf = wave5_to_vpu_buf(vb2_v4l2_buf); > + > + if (!vpu_buf->consumed) { > + dev_dbg(inst->dev->dev, "%s: dst buf (index: %u) has not been consumed\n", > + __func__, vb2_v4l2_buf->vb2_buf.index); > + return vb2_v4l2_buf; > + } > + } > + > + return NULL; > +} > + > +static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width, > + unsigned int height) > +{ > + switch (pix_mp->pixelformat) { > + case V4L2_PIX_FMT_YUV420: > + case V4L2_PIX_FMT_NV12: > + case V4L2_PIX_FMT_NV21: > + pix_mp->width = width; > + pix_mp->height = height; > + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); > + pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height * 3 / 2; > + break; > + case V4L2_PIX_FMT_YUV420M: > + pix_mp->width = width; > + pix_mp->height = height; > + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); > + pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height; > + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; > + pix_mp->plane_fmt[1].sizeimage = round_up(width, 32) * height / 4; > + pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; > + pix_mp->plane_fmt[2].sizeimage = round_up(width, 32) * height / 4; > + break; > + case V4L2_PIX_FMT_NV12M: > + case V4L2_PIX_FMT_NV21M: > + pix_mp->width = width; > + pix_mp->height = height; > + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); > + pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height; > + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); > + pix_mp->plane_fmt[1].sizeimage = round_up(width, 32) * height / 2; > + break; > + default: > + pix_mp->width = width; > + pix_mp->height = height; > + pix_mp->plane_fmt[0].bytesperline = 0; > + pix_mp->plane_fmt[0].sizeimage = width * height; > + break; > + } > +} > + > +static void wave5_vpu_enc_start_encode(struct vpu_instance *inst) > +{ > + u32 max_cmd_q = 0; > + > + max_cmd_q = (inst->src_buf_count < COMMAND_QUEUE_DEPTH) ? > + inst->src_buf_count : COMMAND_QUEUE_DEPTH; > + > + if (inst->state == VPU_INST_STATE_STOP) > + max_cmd_q = 1; > + > + while (max_cmd_q) { > + struct vb2_v4l2_buffer *src_buf; > + struct vb2_v4l2_buffer *dst_buf; > + struct vpu_buffer *src_vbuf; > + struct vpu_buffer *dst_vbuf; > + struct frame_buffer frame_buf; > + struct enc_param pic_param; > + u32 stride = ALIGN(inst->dst_fmt.width, 32); > + u32 luma_size = (stride * inst->dst_fmt.height); > + u32 chroma_size = ((stride / 2) * (inst->dst_fmt.height / 2)); > + u32 fail_res; > + int ret; > + > + memset(&pic_param, 0, sizeof(struct enc_param)); > + memset(&frame_buf, 0, sizeof(struct frame_buffer)); > + > + src_buf = wave5_get_valid_src_buf(inst); > + dst_buf = wave5_get_valid_dst_buf(inst); > + > + if (!dst_buf) { > + dev_dbg(inst->dev->dev, "%s: No valid dst buf\n", __func__); > + break; > + } > + > + dst_vbuf = wave5_to_vpu_buf(dst_buf); > + pic_param.pic_stream_buffer_addr = > + vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); > + pic_param.pic_stream_buffer_size = > + vb2_plane_size(&dst_buf->vb2_buf, 0); > + > + if (!src_buf) { > + dev_dbg(inst->dev->dev, "%s: No valid src buf\n", __func__); > + if (inst->state == VPU_INST_STATE_STOP) > + pic_param.src_end_flag = true; > + else > + break; > + } else { > + src_vbuf = wave5_to_vpu_buf(src_buf); > + if (inst->src_fmt.num_planes == 1) { > + frame_buf.buf_y = > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); > + frame_buf.buf_cb = frame_buf.buf_y + luma_size; > + frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; > + } else if (inst->src_fmt.num_planes == 2) { > + frame_buf.buf_y = > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); > + frame_buf.buf_cb = > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); > + frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; > + } else if (inst->src_fmt.num_planes == 3) { > + frame_buf.buf_y = > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); > + frame_buf.buf_cb = > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); > + frame_buf.buf_cr = > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 2); > + } > + frame_buf.stride = stride; > + pic_param.src_idx = src_buf->vb2_buf.index; > + } > + > + pic_param.source_frame = &frame_buf; > + pic_param.code_option.implicit_header_encode = 1; > + ret = wave5_vpu_enc_start_one_frame(inst, &pic_param, &fail_res); > + if (ret) { > + if (fail_res == WAVE5_SYSERR_QUEUEING_FAIL) > + break; > + > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame fail: %d\n", > + __func__, ret); > + src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); > + if (!src_buf) { > + dev_dbg(inst->dev->dev, > + "%s: Removing src buf failed, the queue is empty\n", > + __func__); > + continue; > + } > + dst_buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx); > + if (!dst_buf) { > + dev_dbg(inst->dev->dev, > + "%s: Removing dst buf failed, the queue is empty\n", > + __func__); > + continue; > + } > + inst->state = VPU_INST_STATE_STOP; > + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); > + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR); > + } else { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame success\n", > + __func__); > + if (src_buf) > + src_vbuf->consumed = true; > + if (dst_buf) > + dst_vbuf->consumed = true; > + } > + > + max_cmd_q--; > + } > +} > + > +static void wave5_vpu_enc_stop_encode(struct vpu_instance *inst) > +{ > + inst->state = VPU_INST_STATE_STOP; > + > + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); > +} > + > +static void wave5_vpu_enc_finish_encode(struct vpu_instance *inst) > +{ > + int ret; > + struct enc_output_info enc_output_info; > + u32 irq_status; > + struct vb2_v4l2_buffer *dst_buf = NULL; > + struct v4l2_m2m_buffer *v4l2_m2m_buf = NULL; > + > + if (kfifo_out(&inst->irq_status, &irq_status, sizeof(int))) > + wave5_vpu_clear_interrupt_ex(inst, irq_status); > + > + ret = wave5_vpu_enc_get_output_info(inst, &enc_output_info); > + if (ret) { > + dev_dbg(inst->dev->dev, > + "%s: vpu_enc_get_output_info fail: %d reason: %u | info: %u\n", > + __func__, ret, enc_output_info.error_reason, enc_output_info.warn_info); > + return; > + } > + > + v4l2_m2m_for_each_dst_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { > + dst_buf = &v4l2_m2m_buf->vb; > + if (enc_output_info.bitstream_buffer == > + vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0)) > + break; > + } > + > + if (enc_output_info.enc_src_idx >= 0) { > + struct vb2_v4l2_buffer *src_buf = > + v4l2_m2m_src_buf_remove_by_idx(inst->v4l2_fh.m2m_ctx, > + enc_output_info.enc_src_idx); > + > + inst->timestamp = src_buf->vb2_buf.timestamp; > + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); > + } > + > + if (enc_output_info.recon_frame_index == RECON_IDX_FLAG_ENC_END) { > + static const struct v4l2_event vpu_event_eos = { > + .type = V4L2_EVENT_EOS > + }; > + > + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, 0); > + dst_buf->vb2_buf.timestamp = inst->timestamp; > + dst_buf->field = V4L2_FIELD_NONE; > + dst_buf->flags |= V4L2_BUF_FLAG_LAST; > + v4l2_m2m_dst_buf_remove_by_buf(inst->v4l2_fh.m2m_ctx, dst_buf); > + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); > + > + inst->state = VPU_INST_STATE_PIC_RUN; > + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos); > + > + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); > + } else { > + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, enc_output_info.bitstream_size); > + > + dst_buf->vb2_buf.timestamp = inst->timestamp; > + dst_buf->field = V4L2_FIELD_NONE; > + if (enc_output_info.pic_type == PIC_TYPE_I) { > + if (enc_output_info.enc_vcl_nut == 19 || > + enc_output_info.enc_vcl_nut == 20) > + dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME; > + else > + dst_buf->flags |= V4L2_BUF_FLAG_PFRAME; > + } else if (enc_output_info.pic_type == PIC_TYPE_P) { > + dst_buf->flags |= V4L2_BUF_FLAG_PFRAME; > + } else if (enc_output_info.pic_type == PIC_TYPE_B) { > + dst_buf->flags |= V4L2_BUF_FLAG_BFRAME; > + } > + > + v4l2_m2m_dst_buf_remove_by_buf(inst->v4l2_fh.m2m_ctx, dst_buf); > + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); > + > + dev_dbg(inst->dev->dev, "%s: frame_cycle %8u\n", > + __func__, enc_output_info.frame_cycle); > + } > +} > + > +static int wave5_vpu_enc_querycap(struct file *file, void *fh, struct v4l2_capability *cap) > +{ > + strscpy(cap->driver, VPU_ENC_DRV_NAME, sizeof(cap->driver)); > + strscpy(cap->card, VPU_ENC_DRV_NAME, sizeof(cap->card)); > + strscpy(cap->bus_info, "platform:" VPU_ENC_DRV_NAME, sizeof(cap->bus_info)); Can be dropped. > + > + return 0; > +} > + > +static int wave5_vpu_enc_enum_framesizes(struct file *f, void *fh, struct v4l2_frmsizeenum *fsize) > +{ > + const struct vpu_format *vpu_fmt; > + > + if (fsize->index) > + return -EINVAL; > + > + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, enc_fmt_list[VPU_FMT_TYPE_CODEC]); > + if (!vpu_fmt) { > + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, enc_fmt_list[VPU_FMT_TYPE_RAW]); > + if (!vpu_fmt) > + return -EINVAL; > + } > + > + fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; > + fsize->stepwise.min_width = vpu_fmt->min_width; > + fsize->stepwise.max_width = vpu_fmt->max_width; > + fsize->stepwise.step_width = 1; > + fsize->stepwise.min_height = vpu_fmt->min_height; > + fsize->stepwise.max_height = vpu_fmt->max_height; > + fsize->stepwise.step_height = 1; > + > + return 0; > +} > + > +static int wave5_vpu_enc_enum_fmt_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); > + > + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, enc_fmt_list[VPU_FMT_TYPE_CODEC]); > + if (!vpu_fmt) > + return -EINVAL; > + > + f->pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->flags = 0; > + > + return 0; > +} > + > +static int wave5_vpu_enc_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > + > + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) > + return -EINVAL; > + > + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]); > + if (!vpu_fmt) { > + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; > + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; > + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height); > + } else { > + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); > + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); > + > + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->fmt.pix_mp.num_planes = 1; > + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); > + } > + > + f->fmt.pix_mp.flags = 0; > + f->fmt.pix_mp.field = V4L2_FIELD_NONE; > + f->fmt.pix_mp.colorspace = inst->colorspace; > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > + f->fmt.pix_mp.quantization = inst->quantization; > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); > + > + return 0; > +} > + > +static int wave5_vpu_enc_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i, ret; > + > + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > + > + ret = wave5_vpu_enc_try_fmt_cap(file, fh, f); > + if (ret) > + return ret; > + > + inst->dst_fmt.width = f->fmt.pix_mp.width; > + inst->dst_fmt.height = f->fmt.pix_mp.height; > + inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat; > + inst->dst_fmt.field = f->fmt.pix_mp.field; > + inst->dst_fmt.flags = f->fmt.pix_mp.flags; > + inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes; > + for (i = 0; i < inst->dst_fmt.num_planes; i++) { > + inst->dst_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; > + inst->dst_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; > + } > + > + return 0; > +} > + > +static int wave5_vpu_enc_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i; > + > + f->fmt.pix_mp.width = inst->dst_fmt.width; > + f->fmt.pix_mp.height = inst->dst_fmt.height; > + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; > + f->fmt.pix_mp.field = inst->dst_fmt.field; > + f->fmt.pix_mp.flags = inst->dst_fmt.flags; > + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; > + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { > + f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->dst_fmt.plane_fmt[i].bytesperline; > + f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->dst_fmt.plane_fmt[i].sizeimage; > + } > + > + f->fmt.pix_mp.colorspace = inst->colorspace; > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > + f->fmt.pix_mp.quantization = inst->quantization; > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > + > + return 0; > +} > + > +static int wave5_vpu_enc_enum_fmt_out(struct file *file, void *fh, struct v4l2_fmtdesc *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); > + > + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, enc_fmt_list[VPU_FMT_TYPE_RAW]); > + if (!vpu_fmt) > + return -EINVAL; > + > + f->pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->flags = 0; > + > + return 0; > +} > + > +static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > + > + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + return -EINVAL; > + > + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_RAW]); > + if (!vpu_fmt) { > + f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; > + f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; > + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height); > + } else { > + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); > + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); > + const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); > + > + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->fmt.pix_mp.num_planes = info->mem_planes; > + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); > + } > + > + f->fmt.pix_mp.flags = 0; > + f->fmt.pix_mp.field = V4L2_FIELD_NONE; > + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); > + > + return 0; > +} > + > +static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i, ret; > + > + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > + > + ret = wave5_vpu_enc_try_fmt_out(file, fh, f); > + if (ret) > + return ret; > + > + inst->src_fmt.width = f->fmt.pix_mp.width; > + inst->src_fmt.height = f->fmt.pix_mp.height; > + inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat; > + inst->src_fmt.field = f->fmt.pix_mp.field; > + inst->src_fmt.flags = f->fmt.pix_mp.flags; > + inst->src_fmt.num_planes = f->fmt.pix_mp.num_planes; > + for (i = 0; i < inst->src_fmt.num_planes; i++) { > + inst->src_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; > + inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; > + } > + > + if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12 || > + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12M) { > + inst->cbcr_interleave = true; > + inst->nv21 = false; > + } else if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21 || > + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21M) { > + inst->cbcr_interleave = true; > + inst->nv21 = true; > + } else { > + inst->cbcr_interleave = false; > + inst->nv21 = false; > + } > + > + inst->colorspace = f->fmt.pix_mp.colorspace; > + inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; > + inst->hsv_enc = f->fmt.pix_mp.hsv_enc; > + inst->quantization = f->fmt.pix_mp.quantization; > + inst->xfer_func = f->fmt.pix_mp.xfer_func; > + > + wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height); > + > + return 0; > +} > + > +static int wave5_vpu_enc_g_selection(struct file *file, void *fh, struct v4l2_selection *s) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + > + dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target); > + > + if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { > + switch (s->target) { > + case V4L2_SEL_TGT_CROP_DEFAULT: > + case V4L2_SEL_TGT_CROP_BOUNDS: > + s->r.left = 0; > + s->r.top = 0; > + s->r.width = inst->dst_fmt.width; > + s->r.height = inst->dst_fmt.height; > + break; > + case V4L2_SEL_TGT_CROP: > + s->r.left = 0; > + s->r.top = 0; > + s->r.width = inst->dst_fmt.width; > + s->r.height = inst->dst_fmt.height; > + dev_dbg(inst->dev->dev, "%s: V4L2_SEL_TGT_CROP width: %u | height: %u\n", > + __func__, s->r.width, s->r.height); > + break; > + default: > + return -EINVAL; > + } > + } else { > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int wave5_vpu_enc_s_selection(struct file *file, void *fh, struct v4l2_selection *s) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + > + if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) > + return -EINVAL; > + > + if (s->target != V4L2_SEL_TGT_CROP) > + return -EINVAL; > + > + dev_dbg(inst->dev->dev, "%s: V4L2_SEL_TGT_CROP width: %u | height: %u\n", > + __func__, s->r.width, s->r.height); > + > + s->r.left = 0; > + s->r.top = 0; > + s->r.width = inst->src_fmt.width; > + s->r.height = inst->src_fmt.height; > + > + return 0; > +} > + > +static int wave5_vpu_enc_encoder_cmd(struct file *file, void *fh, struct v4l2_encoder_cmd *ec) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int ret; > + > + ret = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, ec); > + if (ret) > + return ret; > + > + if (!wave5_vpu_both_queues_are_streaming(inst)) > + return 0; > + > + switch (ec->cmd) { > + case V4L2_ENC_CMD_STOP: > + inst->state = VPU_INST_STATE_STOP; > + inst->ops->start_process(inst); > + break; > + case V4L2_ENC_CMD_START: > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int wave5_vpu_enc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, a->type); > + > + if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + return -EINVAL; > + > + a->parm.output.capability = V4L2_CAP_TIMEPERFRAME; > + a->parm.output.timeperframe.numerator = 1; > + a->parm.output.timeperframe.denominator = inst->frame_rate; > + > + dev_dbg(inst->dev->dev, "%s: numerator: %u | denominator: %u\n", > + __func__, a->parm.output.timeperframe.numerator, > + a->parm.output.timeperframe.denominator); > + > + return 0; > +} > + > +static int wave5_vpu_enc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, a->type); > + > + if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + return -EINVAL; > + > + a->parm.output.capability = V4L2_CAP_TIMEPERFRAME; > + if (a->parm.output.timeperframe.denominator && a->parm.output.timeperframe.numerator) { > + inst->frame_rate = a->parm.output.timeperframe.denominator / > + a->parm.output.timeperframe.numerator; > + } else { > + a->parm.output.timeperframe.numerator = 1; > + a->parm.output.timeperframe.denominator = inst->frame_rate; > + } > + > + dev_dbg(inst->dev->dev, "%s: numerator: %u | denominator: %u\n", > + __func__, a->parm.output.timeperframe.numerator, > + a->parm.output.timeperframe.denominator); > + > + return 0; > +} > + > +static const struct v4l2_ioctl_ops wave5_vpu_enc_ioctl_ops = { > + .vidioc_querycap = wave5_vpu_enc_querycap, > + .vidioc_enum_framesizes = wave5_vpu_enc_enum_framesizes, > + > + .vidioc_enum_fmt_vid_cap = wave5_vpu_enc_enum_fmt_cap, > + .vidioc_s_fmt_vid_cap_mplane = wave5_vpu_enc_s_fmt_cap, > + .vidioc_g_fmt_vid_cap_mplane = wave5_vpu_enc_g_fmt_cap, > + .vidioc_try_fmt_vid_cap_mplane = wave5_vpu_enc_try_fmt_cap, > + > + .vidioc_enum_fmt_vid_out = wave5_vpu_enc_enum_fmt_out, > + .vidioc_s_fmt_vid_out_mplane = wave5_vpu_enc_s_fmt_out, > + .vidioc_g_fmt_vid_out_mplane = wave5_vpu_g_fmt_out, > + .vidioc_try_fmt_vid_out_mplane = wave5_vpu_enc_try_fmt_out, > + > + .vidioc_g_selection = wave5_vpu_enc_g_selection, > + .vidioc_s_selection = wave5_vpu_enc_s_selection, > + > + .vidioc_g_parm = wave5_vpu_enc_g_parm, > + .vidioc_s_parm = wave5_vpu_enc_s_parm, > + > + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, > + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, > + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, > + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, > + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, > + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, > + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, > + .vidioc_streamon = v4l2_m2m_ioctl_streamon, > + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, > + > + .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd, > + .vidioc_encoder_cmd = wave5_vpu_enc_encoder_cmd, > + > + .vidioc_subscribe_event = wave5_vpu_subscribe_event, > + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, > +}; > + > +static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl) > +{ > + struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl); > + > + dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n", __func__, ctrl->name, ctrl->val); > + > + switch (ctrl->id) { > + case V4L2_CID_HFLIP: > + inst->mirror_direction |= (ctrl->val << 1); > + break; > + case V4L2_CID_VFLIP: > + inst->mirror_direction |= ctrl->val; > + break; > + case V4L2_CID_ROTATE: > + inst->rot_angle = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_VBV_SIZE: > + inst->vbv_buf_size = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR: > + inst->rc_mode = 0; > + break; > + case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR: > + inst->rc_mode = 1; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_BITRATE: > + inst->bit_rate = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_GOP_SIZE: > + inst->enc_param.avc_idr_period = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE: > + inst->enc_param.independ_slice_mode = ctrl->val; > + inst->enc_param.avc_slice_mode = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB: > + inst->enc_param.independ_slice_mode_arg = ctrl->val; > + inst->enc_param.avc_slice_arg = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: > + inst->rc_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE: > + inst->enc_param.mb_level_rc_enable = ctrl->val; > + inst->enc_param.cu_level_rc_enable = ctrl->val; > + inst->enc_param.hvs_qp_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN: > + inst->enc_param.profile = HEVC_PROFILE_MAIN; > + inst->bit_depth = 8; > + break; > + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE: > + inst->enc_param.profile = HEVC_PROFILE_STILLPICTURE; > + inst->enc_param.en_still_picture = 1; > + inst->bit_depth = 8; > + break; > + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10: > + inst->enc_param.profile = HEVC_PROFILE_MAIN10; > + inst->bit_depth = 10; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_1: > + inst->enc_param.level = 10 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2: > + inst->enc_param.level = 20 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1: > + inst->enc_param.level = 21 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3: > + inst->enc_param.level = 30 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1: > + inst->enc_param.level = 31 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4: > + inst->enc_param.level = 40 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1: > + inst->enc_param.level = 41 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5: > + inst->enc_param.level = 50 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1: > + inst->enc_param.level = 51 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2: > + inst->enc_param.level = 52 * 3; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: > + inst->enc_param.min_qp_i = ctrl->val; > + inst->enc_param.min_qp_p = ctrl->val; > + inst->enc_param.min_qp_b = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: > + inst->enc_param.max_qp_i = ctrl->val; > + inst->enc_param.max_qp_p = ctrl->val; > + inst->enc_param.max_qp_b = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: > + inst->enc_param.intra_qp = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED: > + inst->enc_param.disable_deblk = 1; > + inst->enc_param.sao_enable = 0; > + inst->enc_param.lf_cross_slice_boundary_enable = 0; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED: > + inst->enc_param.disable_deblk = 0; > + inst->enc_param.sao_enable = 1; > + inst->enc_param.lf_cross_slice_boundary_enable = 1; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY: > + inst->enc_param.disable_deblk = 0; > + inst->enc_param.sao_enable = 1; > + inst->enc_param.lf_cross_slice_boundary_enable = 0; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2: > + inst->enc_param.beta_offset_div2 = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2: > + inst->enc_param.tc_offset_div2 = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE: > + inst->enc_param.decoding_refresh_type = 0; > + break; > + case V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA: > + inst->enc_param.decoding_refresh_type = 1; > + break; > + case V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR: > + inst->enc_param.decoding_refresh_type = 2; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD: > + inst->enc_param.intra_period = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU: > + inst->enc_param.lossless_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED: > + inst->enc_param.const_intra_pred_flag = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT: > + inst->enc_param.wpp_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING: > + inst->enc_param.strong_intra_smooth_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1: > + inst->enc_param.max_num_merge = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION: > + inst->enc_param.tmvp_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_PROFILE: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: > + case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: > + inst->enc_param.profile = H264_PROFILE_BP; > + inst->bit_depth = 8; > + break; > + case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: > + inst->enc_param.profile = H264_PROFILE_MP; > + inst->bit_depth = 8; > + break; > + case V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED: > + inst->enc_param.profile = H264_PROFILE_EXTENDED; > + inst->bit_depth = 8; > + break; > + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: > + inst->enc_param.profile = H264_PROFILE_HP; > + inst->bit_depth = 8; > + break; > + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10: > + inst->enc_param.profile = H264_PROFILE_HIGH10; > + inst->bit_depth = 10; > + break; > + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422: > + inst->enc_param.profile = H264_PROFILE_HIGH422; > + inst->bit_depth = 10; > + break; > + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE: > + inst->enc_param.profile = H264_PROFILE_HIGH444; > + inst->bit_depth = 10; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_H264_LEVEL: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: > + inst->enc_param.level = 10; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_1B: > + inst->enc_param.level = 9; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: > + inst->enc_param.level = 11; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: > + inst->enc_param.level = 12; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: > + inst->enc_param.level = 13; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: > + inst->enc_param.level = 20; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: > + inst->enc_param.level = 21; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: > + inst->enc_param.level = 22; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: > + inst->enc_param.level = 30; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: > + inst->enc_param.level = 31; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: > + inst->enc_param.level = 32; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: > + inst->enc_param.level = 40; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_4_1: > + inst->enc_param.level = 41; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_4_2: > + inst->enc_param.level = 42; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_5_0: > + inst->enc_param.level = 50; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_5_1: > + inst->enc_param.level = 51; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: > + inst->enc_param.min_qp_i = ctrl->val; > + inst->enc_param.min_qp_p = ctrl->val; > + inst->enc_param.min_qp_b = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: > + inst->enc_param.max_qp_i = ctrl->val; > + inst->enc_param.max_qp_p = ctrl->val; > + inst->enc_param.max_qp_b = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: > + inst->enc_param.intra_qp = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED: > + inst->enc_param.disable_deblk = 1; > + inst->enc_param.lf_cross_slice_boundary_enable = 1; > + break; > + case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED: > + inst->enc_param.disable_deblk = 0; > + inst->enc_param.lf_cross_slice_boundary_enable = 1; > + break; > + case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY: > + inst->enc_param.disable_deblk = 0; > + inst->enc_param.lf_cross_slice_boundary_enable = 0; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA: > + inst->enc_param.beta_offset_div2 = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA: > + inst->enc_param.tc_offset_div2 = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM: > + inst->enc_param.transform8x8_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: > + inst->enc_param.const_intra_pred_flag = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET: > + inst->enc_param.chroma_cb_qp_offset = ctrl->val; > + inst->enc_param.chroma_cr_qp_offset = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD: > + inst->enc_param.intra_period = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: > + inst->enc_param.entropy_coding_mode = ctrl->val; > + break; > + case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT: > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static const struct v4l2_ctrl_ops wave5_vpu_enc_ctrl_ops = { > + .s_ctrl = wave5_vpu_enc_s_ctrl, > +}; > + > +static void wave5_set_enc_openparam(struct enc_open_param *open_param, > + struct vpu_instance *inst) > +{ > + struct enc_wave_param input = inst->enc_param; > + u32 num_ctu_row = ALIGN(inst->dst_fmt.height, 64) / 64; > + u32 num_mb_row = ALIGN(inst->dst_fmt.height, 16) / 16; > + > + open_param->wave_param.gop_preset_idx = PRESET_IDX_IPP_SINGLE; > + open_param->wave_param.hvs_qp_scale = 2; > + open_param->wave_param.hvs_max_delta_qp = 10; > + open_param->wave_param.skip_intra_trans = 1; > + open_param->wave_param.intra_nx_n_enable = 1; > + open_param->wave_param.nr_intra_weight_y = 7; > + open_param->wave_param.nr_intra_weight_cb = 7; > + open_param->wave_param.nr_intra_weight_cr = 7; > + open_param->wave_param.nr_inter_weight_y = 4; > + open_param->wave_param.nr_inter_weight_cb = 4; > + open_param->wave_param.nr_inter_weight_cr = 4; > + open_param->wave_param.rdo_skip = 1; > + open_param->wave_param.lambda_scaling_enable = 1; > + > + open_param->stream_endian = VPU_STREAM_ENDIAN; > + open_param->source_endian = VPU_SOURCE_ENDIAN; > + open_param->line_buf_int_en = true; > + open_param->pic_width = inst->dst_fmt.width; > + open_param->pic_height = inst->dst_fmt.height; > + open_param->frame_rate_info = inst->frame_rate; > + open_param->rc_enable = inst->rc_enable; > + if (inst->rc_enable) { > + open_param->wave_param.initial_rc_qp = -1; > + open_param->wave_param.rc_weight_param = 16; > + open_param->wave_param.rc_weight_buf = 128; > + } > + open_param->wave_param.mb_level_rc_enable = input.mb_level_rc_enable; > + open_param->wave_param.cu_level_rc_enable = input.cu_level_rc_enable; > + open_param->wave_param.hvs_qp_enable = input.hvs_qp_enable; > + open_param->bit_rate = inst->bit_rate; > + open_param->vbv_buffer_size = inst->vbv_buf_size; > + if (inst->rc_mode == 0) > + open_param->vbv_buffer_size = 3000; > + open_param->wave_param.profile = input.profile; > + open_param->wave_param.en_still_picture = input.en_still_picture; > + open_param->wave_param.level = input.level; > + open_param->wave_param.internal_bit_depth = inst->bit_depth; > + open_param->wave_param.intra_qp = input.intra_qp; > + open_param->wave_param.min_qp_i = input.min_qp_i; > + open_param->wave_param.max_qp_i = input.max_qp_i; > + open_param->wave_param.min_qp_p = input.min_qp_p; > + open_param->wave_param.max_qp_p = input.max_qp_p; > + open_param->wave_param.min_qp_b = input.min_qp_b; > + open_param->wave_param.max_qp_b = input.max_qp_b; > + open_param->wave_param.disable_deblk = input.disable_deblk; > + open_param->wave_param.lf_cross_slice_boundary_enable = > + input.lf_cross_slice_boundary_enable; > + open_param->wave_param.tc_offset_div2 = input.tc_offset_div2; > + open_param->wave_param.beta_offset_div2 = input.beta_offset_div2; > + open_param->wave_param.decoding_refresh_type = input.decoding_refresh_type; > + open_param->wave_param.intra_period = input.intra_period; > + if (inst->std == W_HEVC_ENC) { > + if (input.intra_period == 0) { > + open_param->wave_param.decoding_refresh_type = DEC_REFRESH_TYPE_IDR; > + open_param->wave_param.intra_period = input.avc_idr_period; > + } > + } else { > + open_param->wave_param.avc_idr_period = input.avc_idr_period; > + } > + open_param->wave_param.entropy_coding_mode = input.entropy_coding_mode; > + open_param->wave_param.lossless_enable = input.lossless_enable; > + open_param->wave_param.const_intra_pred_flag = input.const_intra_pred_flag; > + open_param->wave_param.wpp_enable = input.wpp_enable; > + open_param->wave_param.strong_intra_smooth_enable = input.strong_intra_smooth_enable; > + open_param->wave_param.max_num_merge = input.max_num_merge; > + open_param->wave_param.tmvp_enable = input.tmvp_enable; > + open_param->wave_param.transform8x8_enable = input.transform8x8_enable; > + open_param->wave_param.chroma_cb_qp_offset = input.chroma_cb_qp_offset; > + open_param->wave_param.chroma_cr_qp_offset = input.chroma_cr_qp_offset; > + open_param->wave_param.independ_slice_mode = input.independ_slice_mode; > + open_param->wave_param.independ_slice_mode_arg = input.independ_slice_mode_arg; > + open_param->wave_param.avc_slice_mode = input.avc_slice_mode; > + open_param->wave_param.avc_slice_arg = input.avc_slice_arg; > + open_param->wave_param.intra_mb_refresh_mode = input.intra_mb_refresh_mode; > + if (input.intra_mb_refresh_mode != REFRESH_MB_MODE_NONE) { > + if (num_mb_row >= input.intra_mb_refresh_arg) > + open_param->wave_param.intra_mb_refresh_arg = > + num_mb_row / input.intra_mb_refresh_arg; > + else > + open_param->wave_param.intra_mb_refresh_arg = num_mb_row; > + } > + open_param->wave_param.intra_refresh_mode = input.intra_refresh_mode; > + if (input.intra_refresh_mode != 0) { > + if (num_ctu_row >= input.intra_refresh_arg) > + open_param->wave_param.intra_refresh_arg = > + num_ctu_row / input.intra_refresh_arg; > + else > + open_param->wave_param.intra_refresh_arg = num_ctu_row; > + } > +} > + > +static int wave5_vpu_enc_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, > + unsigned int *num_planes, unsigned int sizes[], > + struct device *alloc_devs[]) > +{ > + struct vpu_instance *inst = vb2_get_drv_priv(q); > + struct v4l2_pix_format_mplane inst_format = > + (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; > + unsigned int i; > + int ret; > + > + dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, > + *num_buffers, *num_planes, q->type); > + > + if (*num_planes) { > + if (inst_format.num_planes != *num_planes) > + return -EINVAL; > + > + for (i = 0; i < *num_planes; i++) { > + if (sizes[i] < inst_format.plane_fmt[i].sizeimage) > + return -EINVAL; > + } > + } else { > + *num_planes = inst_format.num_planes; > + for (i = 0; i < *num_planes; i++) { > + sizes[i] = inst_format.plane_fmt[i].sizeimage; > + dev_dbg(inst->dev->dev, "%s: size[%u]: %u\n", __func__, i, sizes[i]); > + } > + } > + > + dev_dbg(inst->dev->dev, "%s: size: %u\n", __func__, sizes[0]); > + Same concerns here as for the queue_setup in the decoder. > + if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > + unsigned int non_linear_num = 0; > + u32 fb_stride = 0; > + u32 fb_height = 0; > + struct enc_open_param open_param; > + struct enc_initial_info initial_info; > + struct v4l2_ctrl *ctrl; > + > + memset(&open_param, 0, sizeof(struct enc_open_param)); > + > + inst->std = wave5_to_vpu_wavestd(inst->dst_fmt.pixelformat); > + if (inst->std == STD_UNKNOWN) { > + dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", > + (char *)&inst->dst_fmt.pixelformat); > + return -EINVAL; > + } > + > + wave5_set_enc_openparam(&open_param, inst); > + > + ret = wave5_vpu_enc_open(inst, &open_param); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_open, fail: %d\n", > + __func__, ret); > + return ret; > + } > + > + inst->state = VPU_INST_STATE_OPEN; > + > + if (inst->mirror_direction) { > + wave5_vpu_enc_give_command(inst, ENABLE_MIRRORING, NULL); > + wave5_vpu_enc_give_command(inst, SET_MIRROR_DIRECTION, > + &inst->mirror_direction); > + } > + if (inst->rot_angle) { > + wave5_vpu_enc_give_command(inst, ENABLE_ROTATION, NULL); > + wave5_vpu_enc_give_command(inst, SET_ROTATION_ANGLE, &inst->rot_angle); > + } > + > + ret = wave5_vpu_enc_issue_seq_init(inst); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_issue_seq_init, fail: %d\n", > + __func__, ret); > + return ret; > + } > + > + if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_wait_interrupt failed\n", __func__); > + return -EINVAL; > + } > + > + ret = wave5_vpu_enc_complete_seq_init(inst, &initial_info); > + if (ret) > + return ret; > + > + dev_dbg(inst->dev->dev, "%s: min_frame_buffer: %u | min_source_buffer: %u\n", > + __func__, initial_info.min_frame_buffer_count, > + initial_info.min_src_frame_count); > + inst->state = VPU_INST_STATE_INIT_SEQ; > + inst->min_src_buf_count = initial_info.min_src_frame_count + > + COMMAND_QUEUE_DEPTH; > + > + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, > + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT); > + if (ctrl) > + v4l2_ctrl_s_ctrl(ctrl, inst->min_src_buf_count); > + > + inst->min_dst_buf_count = initial_info.min_frame_buffer_count; > + inst->src_buf_count = inst->min_src_buf_count; > + > + if (*num_buffers > inst->src_buf_count) > + inst->src_buf_count = *num_buffers; > + > + *num_buffers = inst->src_buf_count; > + non_linear_num = inst->min_dst_buf_count; > + > + fb_stride = ALIGN(inst->dst_fmt.width, 32); > + fb_height = ALIGN(inst->dst_fmt.height, 32); > + > + for (i = 0; i < non_linear_num; i++) { > + u32 luma_size = fb_stride * fb_height; > + u32 chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; > + > + inst->frame_vbuf[i].size = luma_size + chroma_size; > + ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->frame_vbuf[i]); > + if (ret < 0) { > + dev_dbg(inst->dev->dev, "%s: failed to allocate FBC buffer %zu\n", > + __func__, inst->frame_vbuf[i].size); > + goto free_buffers; > + } > + > + inst->frame_buf[i].buf_y = inst->frame_vbuf[i].daddr; > + inst->frame_buf[i].buf_cb = (dma_addr_t)-1; > + inst->frame_buf[i].buf_cr = (dma_addr_t)-1; > + inst->frame_buf[i].update_fb_info = true; > + inst->frame_buf[i].size = inst->frame_vbuf[i].size; > + } > + > + ret = wave5_vpu_enc_register_frame_buffer(inst, non_linear_num, fb_stride, > + fb_height, COMPRESSED_FRAME_MAP); > + if (ret) { > + dev_dbg(inst->dev->dev, > + "%s: wave5_vpu_enc_register_frame_buffer, fail: %d\n", > + __func__, ret); > + goto free_buffers; > + } > + > + inst->state = VPU_INST_STATE_PIC_RUN; > + } > + > + if (inst->state == VPU_INST_STATE_INIT_SEQ && > + q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > + *num_buffers = inst->src_buf_count; > + dev_dbg(inst->dev->dev, "%s: src buf num: %u", __func__, *num_buffers); > + } > + > + return 0; > + > +free_buffers: > + for (i = 0; i < inst->min_dst_buf_count; i++) > + wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[i]); > + return ret; > +} > + > +static void wave5_vpu_enc_buf_queue(struct vb2_buffer *vb) > +{ > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); > + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); > + struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); > + > + dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n", > + __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), > + vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); > + > + if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + vbuf->sequence = inst->queued_src_buf_num++; > + else > + vbuf->sequence = inst->queued_dst_buf_num++; > + > + vpu_buf->consumed = FALSE; > + v4l2_m2m_buf_queue(inst->v4l2_fh.m2m_ctx, vbuf); > + > + if (vb2_start_streaming_called(vb->vb2_queue)) > + inst->ops->start_process(inst); > +} > + > +static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q) > +{ > + struct vpu_instance *inst = vb2_get_drv_priv(q); > + struct vb2_v4l2_buffer *buf; > + bool check_cmd = true; > + > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); > + > + if (wave5_vpu_both_queues_are_streaming(inst)) > + inst->state = VPU_INST_STATE_STOP; > + > + while (check_cmd) { > + struct queue_status_info q_status; > + struct enc_output_info enc_output_info; > + > + wave5_vpu_enc_give_command(inst, ENC_GET_QUEUE_STATUS, &q_status); > + > + if (q_status.instance_queue_count + q_status.report_queue_count == 0) > + break; > + > + if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) > + break; > + > + if (wave5_vpu_enc_get_output_info(inst, &enc_output_info)) > + dev_dbg(inst->dev->dev, "Getting encoding results from fw, fail\n"); > + } > + > + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > + while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { > + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); > + } > + } else { > + while ((buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx))) { > + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > + vb2_set_plane_payload(&buf->vb2_buf, 0, 0); > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); > + } > + } > +} > + > +static const struct vb2_ops wave5_vpu_enc_vb2_ops = { > + .queue_setup = wave5_vpu_enc_queue_setup, > + .wait_prepare = vb2_ops_wait_prepare, > + .wait_finish = vb2_ops_wait_finish, > + .buf_queue = wave5_vpu_enc_buf_queue, > + .stop_streaming = wave5_vpu_enc_stop_streaming, > +}; > + > +static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, > + struct v4l2_pix_format_mplane *dst_fmt) > +{ > + unsigned int src_pix_fmt = enc_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; > + const struct v4l2_format_info *src_fmt_info = v4l2_format_info(src_pix_fmt); > + > + src_fmt->pixelformat = src_pix_fmt; > + src_fmt->field = V4L2_FIELD_NONE; > + src_fmt->flags = 0; > + src_fmt->num_planes = src_fmt_info->mem_planes; > + wave5_update_pix_fmt(src_fmt, 416, 240); > + > + dst_fmt->pixelformat = enc_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; > + dst_fmt->field = V4L2_FIELD_NONE; > + dst_fmt->flags = 0; > + dst_fmt->num_planes = 1; > + wave5_update_pix_fmt(dst_fmt, 416, 240); > +} > + > +static int wave5_vpu_enc_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) > +{ > + return wave5_vpu_queue_init(priv, src_vq, dst_vq, &wave5_vpu_enc_vb2_ops); > +} > + > +static const struct vpu_instance_ops wave5_vpu_enc_inst_ops = { > + .start_process = wave5_vpu_enc_start_encode, > + .stop_process = wave5_vpu_enc_stop_encode, > + .finish_process = wave5_vpu_enc_finish_encode, > +}; > + > +static void wave5_vpu_enc_device_run(void *priv) > +{ > + struct vpu_instance *inst = priv; > + > + inst->ops->start_process(inst); > +} > + > +static int wave5_vpu_enc_job_ready(void *priv) > +{ > + struct vpu_instance *inst = priv; > + > + if (inst->state == VPU_INST_STATE_STOP) > + return 0; > + > + return 1; > +} > + > +static void wave5_vpu_enc_job_abort(void *priv) > +{ > + struct vpu_instance *inst = priv; > + > + inst->ops->stop_process(inst); > +} > + > +static const struct v4l2_m2m_ops wave5_vpu_enc_m2m_ops = { > + .device_run = wave5_vpu_enc_device_run, > + .job_ready = wave5_vpu_enc_job_ready, > + .job_abort = wave5_vpu_enc_job_abort, > +}; > + > +static int wave5_vpu_open_enc(struct file *filp) > +{ > + struct video_device *vdev = video_devdata(filp); > + struct vpu_device *dev = video_drvdata(filp); > + struct vpu_instance *inst = NULL; > + struct v4l2_ctrl_handler *v4l2_ctrl_hdl; > + int ret = 0; > + > + inst = kzalloc(sizeof(*inst), GFP_KERNEL); > + if (!inst) > + return -ENOMEM; > + v4l2_ctrl_hdl = &inst->v4l2_ctrl_hdl; > + > + inst->dev = dev; > + inst->type = VPU_INST_TYPE_ENC; > + inst->ops = &wave5_vpu_enc_inst_ops; > + > + v4l2_fh_init(&inst->v4l2_fh, vdev); > + filp->private_data = &inst->v4l2_fh; > + v4l2_fh_add(&inst->v4l2_fh); > + > + INIT_LIST_HEAD(&inst->list); > + list_add_tail(&inst->list, &dev->instances); > + > + inst->v4l2_m2m_dev = v4l2_m2m_init(&wave5_vpu_enc_m2m_ops); > + if (IS_ERR(inst->v4l2_m2m_dev)) { > + ret = PTR_ERR(inst->v4l2_m2m_dev); > + dev_err(inst->dev->dev, "v4l2_m2m_init, fail: %d\n", ret); > + goto cleanup_inst; > + } > + > + inst->v4l2_fh.m2m_ctx = > + v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_enc_queue_init); > + if (IS_ERR(inst->v4l2_fh.m2m_ctx)) { > + ret = PTR_ERR(inst->v4l2_fh.m2m_ctx); > + goto cleanup_inst; > + } > + > + v4l2_ctrl_handler_init(v4l2_ctrl_hdl, 50); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, > + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, 0, > + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, > + V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 0, > + V4L2_MPEG_VIDEO_HEVC_LEVEL_1); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, > + 0, 63, 1, 8); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP, > + 0, 63, 1, 51); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP, > + 0, 63, 1, 30); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE, > + V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, 0, > + V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2, > + -6, 6, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2, > + -6, 6, 1, 0); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE, > + V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR, 0, > + V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD, > + 0, 2047, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING, > + 0, 1, 1, 1); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1, > + 1, 2, 1, 2); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION, > + 0, 1, 1, 1); > + > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_PROFILE, > + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE, 0, > + V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_LEVEL, > + V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 0, > + V4L2_MPEG_VIDEO_H264_LEVEL_1_0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_MIN_QP, > + 0, 63, 1, 8); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_MAX_QP, > + 0, 63, 1, 51); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, > + 0, 63, 1, 30); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE, > + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, 0, > + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA, > + -6, 6, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA, > + -6, 6, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM, > + 0, 1, 1, 1); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET, > + -12, 12, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_I_PERIOD, > + 0, 2047, 1, 0); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE, > + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, 0, > + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC); > + > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_HFLIP, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_VFLIP, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_ROTATE, > + 0, 270, 90, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_VBV_SIZE, > + 10, 3000, 1, 3000); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_BITRATE_MODE, > + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0, > + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_BITRATE, > + 0, 700000000, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_GOP_SIZE, > + 0, 2047, 1, 0); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE, > + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB, 0, > + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, > + 0, 0xFFFF, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1); > + > + if (v4l2_ctrl_hdl->error) { > + ret = -ENODEV; > + goto cleanup_inst; > + } > + > + inst->v4l2_fh.ctrl_handler = v4l2_ctrl_hdl; > + v4l2_ctrl_handler_setup(v4l2_ctrl_hdl); > + > + wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); > + inst->colorspace = V4L2_COLORSPACE_REC709; > + inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; > + inst->hsv_enc = 0; > + inst->quantization = V4L2_QUANTIZATION_DEFAULT; > + inst->xfer_func = V4L2_XFER_FUNC_DEFAULT; > + inst->frame_rate = 30; > + > + init_completion(&inst->irq_done); > + ret = kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL); > + if (ret) { > + dev_err(inst->dev->dev, "Allocating fifo, fail: %d\n", ret); > + goto cleanup_inst; > + } > + > + inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); > + if (inst->id < 0) { > + dev_warn(inst->dev->dev, "Allocating instance ID, fail: %d\n", inst->id); > + ret = inst->id; > + goto cleanup_inst; > + } > + > + return 0; > + > +cleanup_inst: > + wave5_cleanup_instance(inst); > + return ret; > +} > + > +static int wave5_vpu_enc_release(struct file *filp) > +{ > + return wave5_vpu_release_device(filp, wave5_vpu_enc_close, "encoder"); > +} > + > +static const struct v4l2_file_operations wave5_vpu_enc_fops = { > + .owner = THIS_MODULE, > + .open = wave5_vpu_open_enc, > + .release = wave5_vpu_enc_release, > + .unlocked_ioctl = video_ioctl2, > + .poll = v4l2_m2m_fop_poll, > + .mmap = v4l2_m2m_fop_mmap, > +}; > + > +int wave5_vpu_enc_register_device(struct vpu_device *dev) > +{ > + struct video_device *vdev_enc; > + int ret; > + > + vdev_enc = devm_kzalloc(dev->v4l2_dev.dev, sizeof(*vdev_enc), GFP_KERNEL); > + if (!vdev_enc) > + return -ENOMEM; > + > + dev->video_dev_enc = vdev_enc; > + > + strscpy(vdev_enc->name, VPU_ENC_DEV_NAME, sizeof(vdev_enc->name)); > + vdev_enc->fops = &wave5_vpu_enc_fops; > + vdev_enc->ioctl_ops = &wave5_vpu_enc_ioctl_ops; > + vdev_enc->release = video_device_release_empty; > + vdev_enc->v4l2_dev = &dev->v4l2_dev; > + vdev_enc->vfl_dir = VFL_DIR_M2M; > + vdev_enc->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; > + vdev_enc->lock = &dev->dev_lock; > + > + ret = video_register_device(vdev_enc, VFL_TYPE_VIDEO, -1); > + if (ret) > + return ret; > + > + video_set_drvdata(vdev_enc, dev); > + > + return 0; > +} > + > +void wave5_vpu_enc_unregister_device(struct vpu_device *dev) > +{ > + video_unregister_device(dev->video_dev_enc); > +} > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers/media/platform/chips-media/wave5/wave5-vpu.c > new file mode 100644 > index 000000000000..9c602168cffc > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c > @@ -0,0 +1,362 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > +/* > + * Wave5 series multi-standard codec IP - platform driver > + * > + * Copyright (C) 2021 CHIPS&MEDIA INC > + */ > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/clk.h> > +#include <linux/of_address.h> > +#include <linux/firmware.h> > +#include <linux/interrupt.h> > +#include "wave5-vpu.h" > +#include "wave5-regdefine.h" > +#include "wave5-vpuconfig.h" > +#include "wave5.h" > + > +#define VPU_PLATFORM_DEVICE_NAME "vdec" > +#define VPU_CLK_NAME "vcodec" > + > +#define WAVE5_IS_ENC BIT(0) > +#define WAVE5_IS_DEC BIT(1) > + > +struct wave5_match_data { > + int flags; > + const char *fw_name; > +}; > + > +int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout) > +{ > + int ret; > + > + ret = wait_for_completion_timeout(&inst->irq_done, > + msecs_to_jiffies(timeout)); > + if (!ret) > + return -ETIMEDOUT; > + > + reinit_completion(&inst->irq_done); > + > + return 0; > +} > + > +static void wave5_vpu_get_interrupt_for_inst(struct vpu_instance *inst, u32 status) > +{ > + struct vpu_device *dev = inst->dev; > + u32 seq_done; > + u32 cmd_done; > + int val; > + > + seq_done = wave5_vdi_readl(dev, W5_RET_SEQ_DONE_INSTANCE_INFO); > + cmd_done = wave5_vdi_readl(dev, W5_RET_QUEUE_CMD_DONE_INST); > + > + if (status & BIT(INT_WAVE5_INIT_SEQ)) { > + if (seq_done & BIT(inst->id)) { > + seq_done &= ~BIT(inst->id); > + wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done); > + val = BIT(INT_WAVE5_INIT_SEQ); > + kfifo_in(&inst->irq_status, &val, sizeof(int)); > + } > + } > + if (status & BIT(INT_WAVE5_ENC_SET_PARAM)) { > + if (seq_done & BIT(inst->id)) { > + seq_done &= ~BIT(inst->id); > + wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done); > + val = BIT(INT_WAVE5_ENC_SET_PARAM); > + kfifo_in(&inst->irq_status, &val, sizeof(int)); > + } > + } > + if (status & BIT(INT_WAVE5_DEC_PIC) || > + status & BIT(INT_WAVE5_ENC_PIC)) { > + if (cmd_done & BIT(inst->id)) { > + cmd_done &= ~BIT(inst->id); > + wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST, cmd_done); > + val = BIT(INT_WAVE5_DEC_PIC); > + kfifo_in(&inst->irq_status, &val, sizeof(int)); > + } > + } > +} > + > +static irqreturn_t wave5_vpu_irq(int irq, void *dev_id) > +{ > + struct vpu_device *dev = dev_id; > + > + if (wave5_vdi_readl(dev, W5_VPU_VPU_INT_STS)) { > + struct vpu_instance *inst; > + u32 irq_status = wave5_vdi_readl(dev, W5_VPU_VINT_REASON); > + > + list_for_each_entry(inst, &dev->instances, list) { > + wave5_vpu_get_interrupt_for_inst(inst, irq_status); > + } > + > + wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_status); > + wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1); > + > + return IRQ_WAKE_THREAD; > + } > + > + return IRQ_HANDLED; > +} > + > +static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id) > +{ > + struct vpu_device *dev = dev_id; > + struct vpu_instance *inst; > + int irq_status, ret; > + u32 val; > + > + list_for_each_entry(inst, &dev->instances, list) { > + while (kfifo_len(&inst->irq_status)) { > + struct vpu_instance *curr; > + > + curr = v4l2_m2m_get_curr_priv(inst->v4l2_m2m_dev); > + if (curr) { > + inst->ops->finish_process(inst); > + } else { > + ret = kfifo_out(&inst->irq_status, &irq_status, sizeof(int)); > + if (!ret) > + break; > + > + val = wave5_vdi_readl(dev, W5_VPU_VINT_REASON_USR); > + val &= ~irq_status; > + wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_USR, val); > + complete(&inst->irq_done); > + } > + } > + } > + > + return IRQ_HANDLED; > +} > + > +static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name) > +{ > + const struct firmware *fw; > + int ret; > + u32 revision; > + unsigned int product_id; > + > + ret = request_firmware(&fw, fw_name, dev); > + if (ret) { > + dev_err(dev, "request_firmware, fail: %d\n", ret); > + return ret; > + } > + > + ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw->data, fw->size); > + if (ret) { > + dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret); > + goto release_fw; > + } > + release_firmware(fw); > + > + ret = wave5_vpu_get_version_info(dev, &revision, &product_id); > + if (ret) { > + dev_err(dev, "vpu_get_version_info fail: %d\n", ret); > + goto err_without_release; > + } > + > + dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n", > + __func__, product_id, revision); > + > + return 0; > + > +release_fw: > + release_firmware(fw); > +err_without_release: > + return ret; > +} > + > +static int wave5_vpu_probe(struct platform_device *pdev) > +{ > + int ret; > + struct vpu_device *dev; > + struct device_node *np; > + const struct wave5_match_data *match_data; > + struct resource sram; > + > + match_data = device_get_match_data(&pdev->dev); > + if (!match_data) { > + dev_err(&pdev->dev, "missing device match data\n"); > + return -EINVAL; > + } > + > + /* physical addresses limited to 32 bits */ > + dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); > + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); > + > + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); > + if (!dev) > + return -ENOMEM; > + > + dev->vdb_register = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(dev->vdb_register)) > + return PTR_ERR(dev->vdb_register); > + ida_init(&dev->inst_ida); > + > + mutex_init(&dev->dev_lock); > + mutex_init(&dev->hw_lock); > + dev_set_drvdata(&pdev->dev, dev); > + dev->dev = &pdev->dev; > + > + ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks); > + > + /* continue without clock, assume externally managed */ > + if (ret < 0) { > + dev_warn(&pdev->dev, "Getting clocks, fail: %d\n", ret); > + ret = 0; > + } > + dev->num_clks = ret; > + > + ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks); > + if (ret) { > + dev_err(&pdev->dev, "Enabling clocks, fail: %d\n", ret); > + return ret; > + } > + > + np = of_parse_phandle(pdev->dev.of_node, "sram", 0); > + if (!np) { > + dev_warn(&pdev->dev, "sram node not found\n"); > + } else { > + ret = of_address_to_resource(np, 0, &sram); > + if (ret) { > + dev_err(&pdev->dev, "sram resource not available\n"); > + goto err_put_node; > + } > + dev->sram_buf.daddr = sram.start; > + dev->sram_buf.size = resource_size(&sram); > + dev_dbg(&pdev->dev, "%s: sram daddr: %pad, size: 0x%lx\n", > + __func__, &dev->sram_buf.daddr, dev->sram_buf.size); > + } > + > + dev->product_code = wave5_vdi_readl(dev, VPU_PRODUCT_CODE_REGISTER); > + ret = wave5_vdi_init(&pdev->dev); > + if (ret < 0) { > + dev_err(&pdev->dev, "wave5_vdi_init, fail: %d\n", ret); > + goto err_clk_dis; > + } > + dev->product = wave5_vpu_get_product_id(dev); > + > + INIT_LIST_HEAD(&dev->instances); > + ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); > + if (ret) { > + dev_err(&pdev->dev, "v4l2_device_register, fail: %d\n", ret); > + goto err_vdi_release; > + } > + > + if (match_data->flags & WAVE5_IS_DEC) { > + ret = wave5_vpu_dec_register_device(dev); > + if (ret) { > + dev_err(&pdev->dev, "wave5_vpu_dec_register_device, fail: %d\n", ret); > + goto err_v4l2_unregister; > + } > + } > + if (match_data->flags & WAVE5_IS_ENC) { > + ret = wave5_vpu_enc_register_device(dev); > + if (ret) { > + dev_err(&pdev->dev, "wave5_vpu_enc_register_device, fail: %d\n", ret); > + goto err_dec_unreg; > + } > + } > + > + dev->irq = platform_get_irq(pdev, 0); > + if (dev->irq < 0) { > + dev_err(&pdev->dev, "failed to get irq resource\n"); > + ret = -ENXIO; > + goto err_enc_unreg; > + } > + > + ret = devm_request_threaded_irq(&pdev->dev, dev->irq, wave5_vpu_irq, > + wave5_vpu_irq_thread, 0, "vpu_irq", dev); > + if (ret) { > + dev_err(&pdev->dev, "Register interrupt handler, fail: %d\n", ret); > + goto err_enc_unreg; > + } > + > + ret = wave5_vpu_load_firmware(&pdev->dev, match_data->fw_name); > + if (ret) { > + dev_err(&pdev->dev, "wave5_vpu_load_firmware, fail: %d\n", ret); > + goto err_enc_unreg; > + } > + > + dev_dbg(&pdev->dev, "Added wave5 driver with caps: %s %s and product code: 0x%x\n", > + (match_data->flags & WAVE5_IS_ENC) ? "'ENCODE'" : "", > + (match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : "", > + dev->product_code); > + return 0; > + > +err_enc_unreg: > + if (match_data->flags & WAVE5_IS_ENC) > + wave5_vpu_enc_unregister_device(dev); > +err_dec_unreg: > + if (match_data->flags & WAVE5_IS_DEC) > + wave5_vpu_dec_unregister_device(dev); > +err_v4l2_unregister: > + v4l2_device_unregister(&dev->v4l2_dev); > +err_vdi_release: > + wave5_vdi_release(&pdev->dev); > +err_clk_dis: > + clk_bulk_disable_unprepare(dev->num_clks, dev->clks); > +err_put_node: > + of_node_put(np); > + > + return ret; > +} > + > +static int wave5_vpu_remove(struct platform_device *pdev) > +{ > + struct vpu_device *dev = dev_get_drvdata(&pdev->dev); > + > + clk_bulk_disable_unprepare(dev->num_clks, dev->clks); > + wave5_vpu_enc_unregister_device(dev); > + wave5_vpu_dec_unregister_device(dev); > + v4l2_device_unregister(&dev->v4l2_dev); > + wave5_vdi_release(&pdev->dev); > + ida_destroy(&dev->inst_ida); > + > + return 0; > +} > + > +static const struct wave5_match_data wave511_data = { > + .flags = WAVE5_IS_DEC, > + .fw_name = "wave511_dec_fw.bin", > +}; > + > +static const struct wave5_match_data wave521_data = { > + .flags = WAVE5_IS_ENC, > + .fw_name = "wave521_enc_fw.bin", > +}; > + > +static const struct wave5_match_data wave521c_data = { > + .flags = WAVE5_IS_ENC | WAVE5_IS_DEC, > + .fw_name = "wave521c_codec_fw.bin", > +}; > + > +static const struct wave5_match_data default_match_data = { > + .flags = WAVE5_IS_ENC | WAVE5_IS_DEC, > + .fw_name = "chagall.bin", > +}; > + > +static const struct of_device_id wave5_dt_ids[] = { > + { .compatible = "cnm,cm511-vpu", .data = &wave511_data }, > + { .compatible = "cnm,cm517-vpu", .data = &default_match_data }, > + { .compatible = "cnm,cm521-vpu", .data = &wave521_data }, > + { .compatible = "cnm,cm521c-vpu", .data = &wave521c_data }, > + { .compatible = "cnm,cm521c-dual-vpu", .data = &wave521c_data }, > + { .compatible = "cnm,cm521e1-vpu", .data = &default_match_data }, > + { .compatible = "cnm,cm537-vpu", .data = &default_match_data }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, wave5_dt_ids); > + > +static struct platform_driver wave5_vpu_driver = { > + .driver = { > + .name = VPU_PLATFORM_DEVICE_NAME, > + .of_match_table = of_match_ptr(wave5_dt_ids), > + }, > + .probe = wave5_vpu_probe, > + .remove = wave5_vpu_remove, > +}; > + > +module_platform_driver(wave5_vpu_driver); > +MODULE_DESCRIPTION("chips&media VPU V4L2 driver"); > +MODULE_LICENSE("Dual BSD/GPL"); > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.h b/drivers/media/platform/chips-media/wave5/wave5-vpu.h > new file mode 100644 > index 000000000000..7156d8c3fee4 > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.h > @@ -0,0 +1,72 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ > +/* > + * Wave5 series multi-standard codec IP - basic types > + * > + * Copyright (C) 2021 CHIPS&MEDIA INC > + */ > +#ifndef __VPU_DRV_H__ > +#define __VPU_DRV_H__ > + > +#include <media/v4l2-ctrls.h> > +#include <media/v4l2-ioctl.h> > +#include <media/v4l2-event.h> > +#include <media/v4l2-fh.h> > +#include <media/videobuf2-v4l2.h> > +#include <media/videobuf2-dma-contig.h> > +#include <media/videobuf2-vmalloc.h> > +#include "wave5-vpuconfig.h" > +#include "wave5-vpuapi.h" > + > +#define VPU_BUF_SYNC_TO_DEVICE 0 > +#define VPU_BUF_SYNC_FROM_DEVICE 1 > + > +struct vpu_buffer { > + struct v4l2_m2m_buffer v4l2_m2m_buf; > + bool consumed; > +}; > + > +enum vpu_fmt_type { > + VPU_FMT_TYPE_CODEC = 0, > + VPU_FMT_TYPE_RAW = 1 > +}; > + > +struct vpu_format { > + unsigned int v4l2_pix_fmt; > + unsigned int max_width; > + unsigned int min_width; > + unsigned int max_height; > + unsigned int min_height; > +}; > + > +static inline struct vpu_instance *wave5_to_vpu_inst(struct v4l2_fh *vfh) > +{ > + return container_of(vfh, struct vpu_instance, v4l2_fh); > +} > + > +static inline struct vpu_instance *wave5_ctrl_to_vpu_inst(struct v4l2_ctrl *vctrl) > +{ > + return container_of(vctrl->handler, struct vpu_instance, v4l2_ctrl_hdl); > +} > + > +static inline struct vpu_buffer *wave5_to_vpu_buf(struct vb2_v4l2_buffer *vbuf) > +{ > + return container_of(vbuf, struct vpu_buffer, v4l2_m2m_buf.vb); > +} > + > +int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout); > + > +int wave5_vpu_dec_register_device(struct vpu_device *dev); > +void wave5_vpu_dec_unregister_device(struct vpu_device *dev); > +int wave5_vpu_enc_register_device(struct vpu_device *dev); > +void wave5_vpu_enc_unregister_device(struct vpu_device *dev); > +static inline bool wave5_vpu_both_queues_are_streaming(struct vpu_instance *inst) > +{ > + struct vb2_queue *vq_cap = > + v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); > + struct vb2_queue *vq_out = > + v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); > + > + return vb2_is_streaming(vq_cap) && vb2_is_streaming(vq_out); > +} > + > +#endif Regards, Hans ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v11 3/6] media: chips-media: wave5: Add the v4l2 layer 2022-12-12 14:19 ` Hans Verkuil @ 2023-04-26 13:22 ` Nicolas Dufresne 0 siblings, 0 replies; 22+ messages in thread From: Nicolas Dufresne @ 2023-04-26 13:22 UTC (permalink / raw) To: Hans Verkuil, Sebastian Fricke, linux-media, Mauro Carvalho Chehab, Nas Chung, Robert Beckett Cc: kernel, linux-kernel Hi Sebastian, Hans, Le lundi 12 décembre 2022 à 15:19 +0100, Hans Verkuil a écrit : > Hi Sebastian, > > Some review comments below. > > FYI: if you can post a v12 by Thursday, then I'll run that through my daily build > setup to check for smatch, sparse, etc. issues. > > The next three weeks I'm on vacation, so it will be on hold until I'm back. > > Regards, > > Hans > > On 07/12/2022 13:13, Sebastian Fricke wrote: > > From: Nas Chung <nas.chung@chipsnmedia.com> > > > > Add the decoder and encoder implementing the v4l2 > > API. This patch also adds the Makefile and the VIDEO_WAVE_VPU config > > > > Signed-off-by: Robert Beckett <bob.beckett@collabora.com> > > Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> > > Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> > > Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com> > > --- > > drivers/media/platform/chips-media/Kconfig | 1 + > > drivers/media/platform/chips-media/Makefile | 1 + > > .../media/platform/chips-media/wave5/Kconfig | 12 + > > .../media/platform/chips-media/wave5/Makefile | 10 + > > .../platform/chips-media/wave5/wave5-helper.c | 175 ++ > > .../platform/chips-media/wave5/wave5-helper.h | 28 + > > .../chips-media/wave5/wave5-vpu-dec.c | 1429 ++++++++++++++ > > .../chips-media/wave5/wave5-vpu-enc.c | 1746 +++++++++++++++++ > > .../platform/chips-media/wave5/wave5-vpu.c | 362 ++++ > > .../platform/chips-media/wave5/wave5-vpu.h | 72 + > > 10 files changed, 3836 insertions(+) > > create mode 100644 drivers/media/platform/chips-media/wave5/Kconfig > > create mode 100644 drivers/media/platform/chips-media/wave5/Makefile > > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-helper.c > > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-helper.h > > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c > > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c > > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu.c > > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu.h > > > > <snip> > > > +static int wave5_vpu_dec_querycap(struct file *file, void *fh, struct v4l2_capability *cap) > > +{ > > + strscpy(cap->driver, VPU_DEC_DRV_NAME, sizeof(cap->driver)); > > + strscpy(cap->card, VPU_DEC_DRV_NAME, sizeof(cap->card)); > > + strscpy(cap->bus_info, "platform:" VPU_DEC_DRV_NAME, sizeof(cap->bus_info)); > > No need to set bus_info, the core will fill this in for you these days (at least > for platform and PCI(e) devices). > > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_dec_enum_framesizes(struct file *f, void *fh, struct v4l2_frmsizeenum *fsize) > > +{ > > + const struct vpu_format *vpu_fmt; > > + > > + if (fsize->index) > > + return -EINVAL; > > + > > + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, dec_fmt_list[VPU_FMT_TYPE_CODEC]); > > + if (!vpu_fmt) { > > + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, dec_fmt_list[VPU_FMT_TYPE_RAW]); > > + if (!vpu_fmt) > > + return -EINVAL; > > + } > > + > > + fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; > > + fsize->stepwise.min_width = vpu_fmt->min_width; > > + fsize->stepwise.max_width = vpu_fmt->max_width; > > + fsize->stepwise.step_width = 1; > > + fsize->stepwise.min_height = vpu_fmt->min_height; > > + fsize->stepwise.max_height = vpu_fmt->max_height; > > + fsize->stepwise.step_height = 1; > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_dec_enum_fmt_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f) > > +{ > > + const struct vpu_format *vpu_fmt; > > + > > + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, dec_fmt_list[VPU_FMT_TYPE_RAW]); > > + if (!vpu_fmt) > > + return -EINVAL; > > + > > + f->pixelformat = vpu_fmt->v4l2_pix_fmt; > > + f->flags = 0; > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + const struct vpu_format *vpu_fmt; > > + > > + dev_dbg(inst->dev->dev, > > + "%s: fourcc: %u width: %u height: %u nm planes: %u colorspace: %u field: %u\n", > > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); > > + > > + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) > > + return -EINVAL; > > + > > + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_RAW]); > > + if (!vpu_fmt) { > > + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; > > + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; > > + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height); > > + } else { > > + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); > > + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); > > + const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); > > + > > + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; > > + f->fmt.pix_mp.num_planes = info->mem_planes; > > + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); > > + } > > + > > + f->fmt.pix_mp.flags = 0; > > + f->fmt.pix_mp.field = V4L2_FIELD_NONE; > > + f->fmt.pix_mp.colorspace = inst->colorspace; > > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > > + f->fmt.pix_mp.quantization = inst->quantization; > > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > > + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_dec_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + int i, ret; > > + > > + dev_dbg(inst->dev->dev, > > + "%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n", > > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); > > + > > + ret = wave5_vpu_dec_try_fmt_cap(file, fh, f); > > + if (ret) > > + return ret; > > + > > + inst->dst_fmt.width = f->fmt.pix_mp.width; > > + inst->dst_fmt.height = f->fmt.pix_mp.height; > > + inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat; > > + inst->dst_fmt.field = f->fmt.pix_mp.field; > > + inst->dst_fmt.flags = f->fmt.pix_mp.flags; > > + inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes; > > + for (i = 0; i < inst->dst_fmt.num_planes; i++) { > > + inst->dst_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; > > + inst->dst_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; > > + } > > + > > + if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12 || > > + inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12M) { > > + inst->cbcr_interleave = true; > > + inst->nv21 = false; > > + } else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21 || > > + inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21M) { > > + inst->cbcr_interleave = true; > > + inst->nv21 = true; > > + } else { > > + inst->cbcr_interleave = false; > > + inst->nv21 = false; > > + } > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_dec_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + int i; > > + > > + f->fmt.pix_mp.width = inst->dst_fmt.width; > > + f->fmt.pix_mp.height = inst->dst_fmt.height; > > + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; > > + f->fmt.pix_mp.field = inst->dst_fmt.field; > > + f->fmt.pix_mp.flags = inst->dst_fmt.flags; > > + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; > > + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { > > + f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->dst_fmt.plane_fmt[i].bytesperline; > > + f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->dst_fmt.plane_fmt[i].sizeimage; > > + } > > + > > + f->fmt.pix_mp.colorspace = inst->colorspace; > > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > > + f->fmt.pix_mp.quantization = inst->quantization; > > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_dec_enum_fmt_out(struct file *file, void *fh, struct v4l2_fmtdesc *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + const struct vpu_format *vpu_fmt; > > + > > + dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); > > + > > + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, dec_fmt_list[VPU_FMT_TYPE_CODEC]); > > + if (!vpu_fmt) > > + return -EINVAL; > > + > > + f->pixelformat = vpu_fmt->v4l2_pix_fmt; > > + f->flags = 0; > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + const struct vpu_format *vpu_fmt; > > + > > + dev_dbg(inst->dev->dev, > > + "%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n", > > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); > > + > > + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > > + return -EINVAL; > > + > > + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_CODEC]); > > + if (!vpu_fmt) { > > + f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; > > + f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; > > + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height); > > + } else { > > + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); > > + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); > > + > > + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; > > + f->fmt.pix_mp.num_planes = 1; > > + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); > > + } > > + > > + f->fmt.pix_mp.flags = 0; > > + f->fmt.pix_mp.field = V4L2_FIELD_NONE; > > + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + int i, ret; > > + > > + dev_dbg(inst->dev->dev, > > + "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > > + > > + ret = wave5_vpu_dec_try_fmt_out(file, fh, f); > > + if (ret) > > + return ret; > > + > > + inst->src_fmt.width = f->fmt.pix_mp.width; > > + inst->src_fmt.height = f->fmt.pix_mp.height; > > + inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat; > > + inst->src_fmt.field = f->fmt.pix_mp.field; > > + inst->src_fmt.flags = f->fmt.pix_mp.flags; > > + inst->src_fmt.num_planes = f->fmt.pix_mp.num_planes; > > + for (i = 0; i < inst->src_fmt.num_planes; i++) { > > + inst->src_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; > > + inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; > > + } > > + > > + inst->colorspace = f->fmt.pix_mp.colorspace; > > + inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; > > + inst->hsv_enc = f->fmt.pix_mp.hsv_enc; > > + inst->quantization = f->fmt.pix_mp.quantization; > > + inst->xfer_func = f->fmt.pix_mp.xfer_func; > > + > > + wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height); > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_dec_g_selection(struct file *file, void *fh, struct v4l2_selection *s) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + > > + dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target); > > + > > + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) > > + return -EINVAL; > > + switch (s->target) { > > + case V4L2_SEL_TGT_COMPOSE_BOUNDS: > > + case V4L2_SEL_TGT_COMPOSE_PADDED: > > + s->r.left = 0; > > + s->r.top = 0; > > + s->r.width = inst->dst_fmt.width; > > + s->r.height = inst->dst_fmt.height; > > + break; > > + case V4L2_SEL_TGT_COMPOSE: > > + case V4L2_SEL_TGT_COMPOSE_DEFAULT: > > + s->r.left = 0; > > + s->r.top = 0; > > + if (inst->state > VPU_INST_STATE_OPEN) { > > + s->r.width = inst->conf_win_width; > > + s->r.height = inst->conf_win_height; > > + } else { > > + s->r.width = inst->src_fmt.width; > > + s->r.height = inst->src_fmt.height; > > + } > > + break; > > + default: > > + return -EINVAL; > > + } > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_dec_s_selection(struct file *file, void *fh, struct v4l2_selection *s) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + > > + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) > > + return -EINVAL; > > + > > + if (s->target != V4L2_SEL_TGT_COMPOSE) > > + return -EINVAL; > > + > > + dev_dbg(inst->dev->dev, "V4L2_SEL_TGT_COMPOSE w: %u h: %u\n", > > + s->r.width, s->r.height); > > + > > + s->r.left = 0; > > + s->r.top = 0; > > + s->r.width = inst->dst_fmt.width; > > + s->r.height = inst->dst_fmt.height; > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_dec_decoder_cmd(struct file *file, void *fh, struct v4l2_decoder_cmd *dc) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + int ret; > > + > > + dev_dbg(inst->dev->dev, "decoder command: %u\n", dc->cmd); > > + > > + ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc); > > + if (ret) > > + return ret; > > + > > + if (!wave5_vpu_both_queues_are_streaming(inst)) > > + return 0; > > + > > + switch (dc->cmd) { > > + case V4L2_DEC_CMD_STOP: > > + inst->state = VPU_INST_STATE_STOP; > > + > > + ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0); > > + if (ret) { > > + dev_err(inst->dev->dev, > > + "Setting EOS for the bitstream, fail: %d\n", ret); > > + return ret; > > + } > > + break; > > + case V4L2_DEC_CMD_START: > > + break; > > + default: > > + return -EINVAL; > > + } > > + > > + return 0; > > +} > > + > > +static const struct v4l2_ioctl_ops wave5_vpu_dec_ioctl_ops = { > > + .vidioc_querycap = wave5_vpu_dec_querycap, > > + .vidioc_enum_framesizes = wave5_vpu_dec_enum_framesizes, > > + > > + .vidioc_enum_fmt_vid_cap = wave5_vpu_dec_enum_fmt_cap, > > + .vidioc_s_fmt_vid_cap_mplane = wave5_vpu_dec_s_fmt_cap, > > + .vidioc_g_fmt_vid_cap_mplane = wave5_vpu_dec_g_fmt_cap, > > + .vidioc_try_fmt_vid_cap_mplane = wave5_vpu_dec_try_fmt_cap, > > + > > + .vidioc_enum_fmt_vid_out = wave5_vpu_dec_enum_fmt_out, > > + .vidioc_s_fmt_vid_out_mplane = wave5_vpu_dec_s_fmt_out, > > + .vidioc_g_fmt_vid_out_mplane = wave5_vpu_g_fmt_out, > > + .vidioc_try_fmt_vid_out_mplane = wave5_vpu_dec_try_fmt_out, > > + > > + .vidioc_g_selection = wave5_vpu_dec_g_selection, > > + .vidioc_s_selection = wave5_vpu_dec_s_selection, > > + > > + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, > > + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, > > + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, > > + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, > > + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, > > + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, > > + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, > > + .vidioc_streamon = v4l2_m2m_ioctl_streamon, > > + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, > > + > > + .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd, > > + .vidioc_decoder_cmd = wave5_vpu_dec_decoder_cmd, > > + > > + .vidioc_subscribe_event = wave5_vpu_subscribe_event, > > + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, > > +}; > > + > > +static int wave5_vpu_dec_s_ctrl(struct v4l2_ctrl *ctrl) > > +{ > > + struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl); > > + > > + dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n", > > + __func__, ctrl->name, ctrl->val); > > + > > + switch (ctrl->id) { > > + case V4L2_CID_VPU_THUMBNAIL_MODE: > > + inst->thumbnail_mode = ctrl->val; > > + break; > > + case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE: > > + break; > > This case can be dropped: this control is a read-only control, so it can never > be set and this op will never be called. > > > + default: > > + return -EINVAL; > > + } > > + > > + return 0; > > +} > > + > > +static const struct v4l2_ctrl_ops wave5_vpu_dec_ctrl_ops = { > > + .s_ctrl = wave5_vpu_dec_s_ctrl, > > +}; > > + > > +static const struct v4l2_ctrl_config wave5_vpu_thumbnail_mode = { > > + .ops = &wave5_vpu_dec_ctrl_ops, > > + .id = V4L2_CID_VPU_THUMBNAIL_MODE, > > + .name = "thumbnail mode", > > Capitalize: "Thumbnail Mode". > > It's not documented, so that needs to be added. Document it either in > Documentation/userspace-api/media/drivers or in a public header where > this control is defined (see e.g. include/uapi/linux/aspeed-video.h). > > Also, it's defined as: > > #define V4L2_CID_VPU_THUMBNAIL_MODE (V4L2_CID_USER_BASE + 0x1001) > > But you need to reserve a range of controls for this driver in > include/uapi/linux/v4l2-controls.h (see e.g. V4L2_CID_USER_ASPEED_BASE). > > > + .type = V4L2_CTRL_TYPE_BOOLEAN, > > + .def = 0, > > + .min = 0, > > + .max = 1, > > + .step = 1, > > + .flags = V4L2_CTRL_FLAG_WRITE_ONLY, > > Why is this WRITE_ONLY? That's weird. > > > +}; > > + > > +static void wave5_set_default_dec_openparam(struct dec_open_param *open_param) > > +{ > > + open_param->bitstream_mode = BS_MODE_INTERRUPT; > > + open_param->stream_endian = VPU_STREAM_ENDIAN; > > + open_param->frame_endian = VPU_FRAME_ENDIAN; > > +} > > + > > +static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, > > + unsigned int *num_planes, unsigned int sizes[], > > + struct device *alloc_devs[]) > > +{ > > + struct vpu_instance *inst = vb2_get_drv_priv(q); > > + struct v4l2_pix_format_mplane inst_format = > > + (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; > > + unsigned int i; > > + int ret; > > + > > + dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, > > + *num_buffers, *num_planes, q->type); > > + > > + if (*num_planes) { > > + if (inst_format.num_planes != *num_planes) > > + return -EINVAL; > > + > > + for (i = 0; i < *num_planes; i++) { > > + if (sizes[i] < inst_format.plane_fmt[i].sizeimage) > > + return -EINVAL; > > + } > > + } else { > > + *num_planes = inst_format.num_planes; > > + > > + if (*num_planes == 1) { > > + sizes[0] = inst_format.width * inst_format.height * 3 / 2; > > + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > > + sizes[0] = inst_format.plane_fmt[0].sizeimage; > > + dev_dbg(inst->dev->dev, "%s: size[0]: %u\n", __func__, sizes[0]); > > + } else if (*num_planes == 2) { > > + sizes[0] = inst_format.width * inst_format.height; > > + sizes[1] = inst_format.width * inst_format.height / 2; > > + dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u\n", > > + __func__, sizes[0], sizes[1]); > > + } else if (*num_planes == 3) { > > + sizes[0] = inst_format.width * inst_format.height; > > + sizes[1] = inst_format.width * inst_format.height / 4; > > + sizes[2] = inst_format.width * inst_format.height / 4; > > + dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u | size[2]: %u\n", > > + __func__, sizes[0], sizes[1], sizes[2]); > > + } > > + } > > + > > So what happens below if you call REQBUFS followed by CREATE_BUFS some time later? > I'm not sure if this is all correct. Certainly the last else doesn't look right to me. I'm quite sure this driver can't in current state support create bufs on capture queue, as it does not have code to register the capture buffer against firmware. I suspect this is largely untested enabled feature. This must be reworked or removed. > > > + if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > > + struct dec_open_param open_param; > > + > > + memset(&open_param, 0, sizeof(struct dec_open_param)); > > + wave5_set_default_dec_openparam(&open_param); > > + > > + inst->bitstream_vbuf.size = ALIGN(inst->src_fmt.plane_fmt[0].sizeimage, 1024) * 4; > > + ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->bitstream_vbuf); > > + if (ret) { > > + dev_dbg(inst->dev->dev, "%s: alloc bitstream of size %zu fail: %d\n", > > + __func__, inst->bitstream_vbuf.size, ret); > > + return ret; > > + } > > + > > + inst->std = wave5_to_vpu_codstd(inst->src_fmt.pixelformat); > > + if (inst->std == STD_UNKNOWN) { > > + dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", > > + (char *)&inst->src_fmt.pixelformat); > > + ret = -EINVAL; > > + goto free_bitstream_vbuf; > > + } > > + open_param.bitstream_buffer = inst->bitstream_vbuf.daddr; > > + open_param.bitstream_buffer_size = inst->bitstream_vbuf.size; > > + > > + ret = wave5_vpu_dec_open(inst, &open_param); > > + if (ret) { > > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_open, fail: %d\n", > > + __func__, ret); > > + goto free_bitstream_vbuf; > > + } > > + > > + inst->state = VPU_INST_STATE_OPEN; > > + > > + if (inst->thumbnail_mode) > > + wave5_vpu_dec_give_command(inst, ENABLE_DEC_THUMBNAIL_MODE, NULL); > > + > > + } else if (inst->state == VPU_INST_STATE_INIT_SEQ && > > + q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { > > I'm fairly certain you can get here twice by calling CREATE_BUFS while already streaming. > > > + u32 non_linear_num; > > + u32 fb_stride, fb_height; > > + u32 luma_size, chroma_size; > > + > > + if (*num_buffers > inst->min_dst_buf_count && > > + *num_buffers < WAVE5_MAX_FBS) > > Since this driver supports create_bufs, the correct check here is > q->num_buffers + *num_buffers. > > > + inst->dst_buf_count = *num_buffers; > > I think this is set too early, if there is an error below, then > dst_buf_count has been updated, when it shouldn't. > > > + > > + *num_buffers = inst->dst_buf_count; > > + non_linear_num = inst->dst_buf_count; > > + > > + for (i = 0; i < non_linear_num; i++) { > > + struct frame_buffer *frame = &inst->frame_buf[i]; > > + struct vpu_buf *vframe = &inst->frame_vbuf[i]; > > + > > + fb_stride = inst->dst_fmt.width; > > + fb_height = ALIGN(inst->dst_fmt.height, 32); > > + luma_size = fb_stride * fb_height; > > + chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; > > + > > + vframe->size = luma_size + chroma_size; > > + ret = wave5_vdi_allocate_dma_memory(inst->dev, vframe); > > + if (ret) { > > + dev_dbg(inst->dev->dev, > > + "%s: Allocating FBC buf of size %zu, fail: %d\n", > > + __func__, vframe->size, ret); > > Shouldn't earlier allocs that succeeded be freed here? > > > + return ret; > > + } > > + > > + frame->buf_y = vframe->daddr; > > + frame->buf_cb = vframe->daddr + luma_size; > > + frame->buf_cr = (dma_addr_t)-1; > > + frame->size = vframe->size; > > + frame->width = inst->src_fmt.width; > > + frame->stride = fb_stride; > > + frame->map_type = COMPRESSED_FRAME_MAP; > > + frame->update_fb_info = true; > > + } > > + } else if (inst->state == VPU_INST_STATE_STOP && > > + q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { > > + *num_buffers = 0; > > Why? > > It's odd anyway, you can do a STREAMON, stream for a while, then STREAMOFF, > add more buffers and do STREAMON again. I'm not sure this will work in this > driver. > > > + } > > + > > + return 0; > > + > > +free_bitstream_vbuf: > > + wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf); > > + return ret; > > +} > > + > > +static int wave5_vpu_dec_start_streaming_open(struct vpu_instance *inst) > > +{ > > + struct dec_initial_info initial_info; > > + int ret = 0; > > + > > + memset(&initial_info, 0, sizeof(struct dec_initial_info)); > > + > > + ret = wave5_vpu_dec_issue_seq_init(inst); > > + if (ret) { > > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_issue_seq_init, fail: %d\n", > > + __func__, ret); > > + return ret; > > + } > > + > > + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) > > + dev_dbg(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__); > > + > > + ret = wave5_vpu_dec_complete_seq_init(inst, &initial_info); > > + if (ret) { > > + dev_dbg(inst->dev->dev, "%s: vpu_dec_complete_seq_init, fail: %d, reason: %u\n", > > + __func__, ret, initial_info.seq_init_err_reason); > > + } else { > > + static const struct v4l2_event vpu_event_src_ch = { > > + .type = V4L2_EVENT_SOURCE_CHANGE, > > + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, > > + }; > > + struct v4l2_ctrl *ctrl; > > + > > + dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n", > > + __func__, initial_info.pic_width, initial_info.pic_height, > > + initial_info.profile, initial_info.min_frame_buffer_count); > > + > > + inst->state = VPU_INST_STATE_INIT_SEQ; > > + inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1; > > + inst->dst_buf_count = inst->min_dst_buf_count; > > + > > + inst->conf_win_width = initial_info.pic_width - initial_info.pic_crop_rect.right; > > + inst->conf_win_height = initial_info.pic_height - initial_info.pic_crop_rect.bottom; > > + > > + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, > > + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE); > > + if (ctrl) > > + v4l2_ctrl_s_ctrl(ctrl, inst->min_dst_buf_count); > > + > > + if (initial_info.pic_width != inst->src_fmt.width || > > + initial_info.pic_height != inst->src_fmt.height) { > > + wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width, > > + initial_info.pic_height); > > + wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width, > > + initial_info.pic_height); > > + } > > + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch); > > + > > + wave5_handle_src_buffer(inst); > > + } > > + > > + return ret; > > +} > > + > > +static int wave5_vpu_dec_start_streaming_seek(struct vpu_instance *inst) > > +{ > > + struct dec_initial_info initial_info; > > + struct dec_param pic_param; > > + struct dec_output_info dec_output_info; > > + int ret = 0; > > + u32 fail_res = 0; > > + > > + memset(&pic_param, 0, sizeof(struct dec_param)); > > + > > + ret = wave5_vpu_dec_start_one_frame(inst, &pic_param, &fail_res); > > + if (ret && fail_res != WAVE5_SYSERR_QUEUEING_FAIL) { > > + struct vb2_v4l2_buffer *src_buf; > > + > > + src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); > > + inst->state = VPU_INST_STATE_STOP; > > + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); > > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_start_one_frame\n", __func__); > > + return ret; > > + } > > + > > + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) > > + dev_dbg(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__); > > + > > + ret = wave5_vpu_dec_get_output_info(inst, &dec_output_info); > > + if (ret) { > > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_get_output_info, fail: %d\n", > > + __func__, ret); > > + return ret; > > + } > > + > > + if (dec_output_info.sequence_changed) { > > + static const struct v4l2_event vpu_event_src_ch = { > > + .type = V4L2_EVENT_SOURCE_CHANGE, > > + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, > > + }; > > + struct v4l2_ctrl *ctrl; > > + > > + wave5_vpu_dec_give_command(inst, DEC_RESET_FRAMEBUF_INFO, NULL); > > + wave5_vpu_dec_give_command(inst, DEC_GET_SEQ_INFO, &initial_info); > > + > > + dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n", > > + __func__, initial_info.pic_width, initial_info.pic_height, > > + initial_info.profile, initial_info.min_frame_buffer_count); > > + > > + inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1; > > + inst->dst_buf_count = inst->min_dst_buf_count; > > + > > + inst->conf_win_width = initial_info.pic_width - initial_info.pic_crop_rect.right; > > + inst->conf_win_height = initial_info.pic_height - initial_info.pic_crop_rect.bottom; > > + > > + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, > > + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE); > > + if (ctrl) > > + v4l2_ctrl_s_ctrl(ctrl, inst->min_dst_buf_count); > > + > > + if (initial_info.pic_width != inst->src_fmt.width || > > + initial_info.pic_height != inst->src_fmt.height) { > > + wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width, > > + initial_info.pic_height); > > + wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width, > > + initial_info.pic_height); > > + } > > + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch); > > + > > + wave5_handle_src_buffer(inst); > > + } > > + > > + return ret; > > +} > > + > > +static void wave5_vpu_dec_buf_queue_src(struct vb2_buffer *vb) > > +{ > > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); > > + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); > > + struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); > > + > > + vpu_buf->consumed = false; > > + vbuf->sequence = inst->queued_src_buf_num++; > > + > > + if (inst->state == VPU_INST_STATE_PIC_RUN) { > > + wave5_handle_bitstream_buffer(inst); > > + inst->ops->start_process(inst); > > + } > > +} > > + > > +static void wave5_vpu_dec_buf_queue_dst(struct vb2_buffer *vb) > > +{ > > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); > > + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); > > + int ret; > > + > > + vbuf->sequence = inst->queued_dst_buf_num++; > > + ret = wave5_vpu_dec_clr_disp_flag(inst, vb->index); > > + if (ret) { > > + dev_dbg(inst->dev->dev, > > + "%s: Clearing the display flag of buffer index: %u, fail: %d\n", > > + __func__, vb->index, ret); > > + } > > + > > + if (inst->state == VPU_INST_STATE_INIT_SEQ) { > > + dma_addr_t buf_addr_y = 0, buf_addr_cb = 0, buf_addr_cr = 0; > > + u32 buf_size = 0; > > + u32 non_linear_num = inst->dst_buf_count; > > + u32 fb_stride = inst->dst_fmt.width; > > + u32 luma_size = fb_stride * inst->dst_fmt.height; > > + u32 chroma_size = (fb_stride / 2) * (inst->dst_fmt.height / 2); > > + > > + if (inst->dst_fmt.num_planes == 1) { > > + buf_size = vb2_plane_size(&vbuf->vb2_buf, 0); > > + buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); > > + buf_addr_cb = buf_addr_y + luma_size; > > + buf_addr_cr = buf_addr_cb + chroma_size; > > + } else if (inst->dst_fmt.num_planes == 2) { > > + buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) + > > + vb2_plane_size(&vbuf->vb2_buf, 1); > > + buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); > > + buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1); > > + buf_addr_cr = buf_addr_cb + chroma_size; > > + } else if (inst->dst_fmt.num_planes == 3) { > > + buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) + > > + vb2_plane_size(&vbuf->vb2_buf, 1) + > > + vb2_plane_size(&vbuf->vb2_buf, 2); > > + buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); > > + buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1); > > + buf_addr_cr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 2); > > + } > > + inst->frame_buf[vb->index + non_linear_num].buf_y = buf_addr_y; > > + inst->frame_buf[vb->index + non_linear_num].buf_cb = buf_addr_cb; > > + inst->frame_buf[vb->index + non_linear_num].buf_cr = buf_addr_cr; > > + inst->frame_buf[vb->index + non_linear_num].size = buf_size; > > + inst->frame_buf[vb->index + non_linear_num].width = inst->src_fmt.width; > > + inst->frame_buf[vb->index + non_linear_num].stride = fb_stride; > > + inst->frame_buf[vb->index + non_linear_num].map_type = LINEAR_FRAME_MAP; > > + inst->frame_buf[vb->index + non_linear_num].update_fb_info = true; > > + } > > + > > + if (!vb2_is_streaming(vb->vb2_queue)) > > + return; > > + > > + if (inst->state == VPU_INST_STATE_STOP && inst->eos == FALSE) > > + inst->ops->start_process(inst); > > +} > > + > > +static void wave5_vpu_dec_buf_queue(struct vb2_buffer *vb) > > +{ > > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); > > + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); > > + > > + dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n", > > + __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), > > + vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); > > + > > + v4l2_m2m_buf_queue(inst->v4l2_fh.m2m_ctx, vbuf); > > + > > + if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > > + wave5_vpu_dec_buf_queue_src(vb); > > + else if (vb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) > > + wave5_vpu_dec_buf_queue_dst(vb); > > +} > > + > > +static int wave5_vpu_dec_start_streaming(struct vb2_queue *q, unsigned int count) > > +{ > > + struct vpu_instance *inst = vb2_get_drv_priv(q); > > + int ret = 0; > > + > > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); > > + > > + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > > + wave5_handle_bitstream_buffer(inst); > > + if (inst->state == VPU_INST_STATE_OPEN) > > + ret = wave5_vpu_dec_start_streaming_open(inst); > > + else if (inst->state == VPU_INST_STATE_INIT_SEQ) > > + ret = wave5_vpu_dec_start_streaming_seek(inst); > > + > > + if (ret) { > > + struct vb2_v4l2_buffer *buf; > > + > > + while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { > > + dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4d | index %4d\n", > > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_QUEUED); > > + } > > + } > > + } > > + > > + return ret; > > +} > > + > > +static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q) > > +{ > > + struct vpu_instance *inst = vb2_get_drv_priv(q); > > + struct vb2_v4l2_buffer *buf; > > + bool check_cmd = TRUE; > > + > > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); > > + > > + while (check_cmd) { > > + struct queue_status_info q_status; > > + struct dec_output_info dec_output_info; > > + > > + wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status); > > + > > + if (q_status.instance_queue_count + q_status.report_queue_count == 0) > > + break; > > + > > + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) > > + break; > > + > > + if (wave5_vpu_dec_get_output_info(inst, &dec_output_info)) > > + dev_dbg(inst->dev->dev, "Getting decoding results from fw, fail\n"); > > + } > > + > > + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > > + while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { > > + dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4u | index %4u\n", > > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); > > + } > > + inst->queued_src_buf_num = 0; > > + } else { > > + unsigned int i; > > + int ret; > > + dma_addr_t rd_ptr, wr_ptr; > > + > > + while ((buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx))) { > > + u32 plane; > > + > > + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", > > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > > + > > + for (plane = 0; plane < inst->dst_fmt.num_planes; plane++) > > + vb2_set_plane_payload(&buf->vb2_buf, plane, 0); > > + > > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); > > + } > > + > > + for (i = 0; i < inst->dst_buf_count; i++) { > > + ret = wave5_vpu_dec_set_disp_flag(inst, i); > > + if (ret) { > > + dev_dbg(inst->dev->dev, > > + "%s: Setting display flag of buf index: %u, fail: %d\n", > > + __func__, i, ret); > > + } > > + } > > + > > + ret = wave5_vpu_dec_get_bitstream_buffer(inst, &rd_ptr, &wr_ptr, NULL); > > + if (ret) { > > + dev_err(inst->dev->dev, > > + "Getting bitstream buf, fail: %d\n", ret); > > + return; > > + } > > + ret = wave5_vpu_dec_set_rd_ptr(inst, wr_ptr, TRUE); > > + if (ret) { > > + dev_err(inst->dev->dev, > > + "Setting read pointer for the decoder, fail: %d\n", ret); > > + return; > > + } > > + if (inst->eos) { > > + inst->eos = FALSE; > > + inst->state = VPU_INST_STATE_INIT_SEQ; > > + } > > + inst->queued_dst_buf_num = 0; > > + } > > +} > > + > > +static const struct vb2_ops wave5_vpu_dec_vb2_ops = { > > + .queue_setup = wave5_vpu_dec_queue_setup, > > + .wait_prepare = vb2_ops_wait_prepare, > > + .wait_finish = vb2_ops_wait_finish, > > + .buf_queue = wave5_vpu_dec_buf_queue, > > + .start_streaming = wave5_vpu_dec_start_streaming, > > + .stop_streaming = wave5_vpu_dec_stop_streaming, > > +}; > > + > > +static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, > > + struct v4l2_pix_format_mplane *dst_fmt) > > +{ > > + unsigned int dst_pix_fmt = dec_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; > > + const struct v4l2_format_info *dst_fmt_info = v4l2_format_info(dst_pix_fmt); > > + > > + src_fmt->pixelformat = dec_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; > > + src_fmt->field = V4L2_FIELD_NONE; > > + src_fmt->flags = 0; > > + src_fmt->num_planes = 1; > > + wave5_update_pix_fmt(src_fmt, 720, 480); > > + > > + dst_fmt->pixelformat = dst_pix_fmt; > > + dst_fmt->field = V4L2_FIELD_NONE; > > + dst_fmt->flags = 0; > > + dst_fmt->num_planes = dst_fmt_info->mem_planes; > > + wave5_update_pix_fmt(dst_fmt, 736, 480); > > +} > > + > > +static int wave5_vpu_dec_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) > > +{ > > + return wave5_vpu_queue_init(priv, src_vq, dst_vq, &wave5_vpu_dec_vb2_ops); > > +} > > + > > +static const struct vpu_instance_ops wave5_vpu_dec_inst_ops = { > > + .start_process = wave5_vpu_dec_start_decode, > > + .stop_process = wave5_vpu_dec_stop_decode, > > + .finish_process = wave5_vpu_dec_finish_decode, > > +}; > > + > > +static void wave5_vpu_dec_device_run(void *priv) > > +{ > > + struct vpu_instance *inst = priv; > > + > > + inst->ops->start_process(inst); > > + > > + inst->state = VPU_INST_STATE_PIC_RUN; > > +} > > + > > +static void wave5_vpu_dec_job_abort(void *priv) > > +{ > > + struct vpu_instance *inst = priv; > > + > > + inst->ops->stop_process(inst); > > +} > > + > > +static const struct v4l2_m2m_ops wave5_vpu_dec_m2m_ops = { > > + .device_run = wave5_vpu_dec_device_run, > > + .job_abort = wave5_vpu_dec_job_abort, > > +}; > > + > > +static int wave5_vpu_open_dec(struct file *filp) > > +{ > > + struct video_device *vdev = video_devdata(filp); > > + struct vpu_device *dev = video_drvdata(filp); > > + struct vpu_instance *inst = NULL; > > + int ret = 0; > > + > > + inst = kzalloc(sizeof(*inst), GFP_KERNEL); > > + if (!inst) > > + return -ENOMEM; > > + > > + inst->dev = dev; > > + inst->type = VPU_INST_TYPE_DEC; > > + inst->ops = &wave5_vpu_dec_inst_ops; > > + > > + v4l2_fh_init(&inst->v4l2_fh, vdev); > > + filp->private_data = &inst->v4l2_fh; > > + v4l2_fh_add(&inst->v4l2_fh); > > + > > + INIT_LIST_HEAD(&inst->list); > > + list_add_tail(&inst->list, &dev->instances); > > + > > + inst->v4l2_m2m_dev = v4l2_m2m_init(&wave5_vpu_dec_m2m_ops); > > + if (IS_ERR(inst->v4l2_m2m_dev)) { > > + ret = PTR_ERR(inst->v4l2_m2m_dev); > > + dev_err(inst->dev->dev, "v4l2_m2m_init, fail: %d\n", ret); > > + goto cleanup_inst; > > + } > > + > > + inst->v4l2_fh.m2m_ctx = > > + v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_dec_queue_init); > > + if (IS_ERR(inst->v4l2_fh.m2m_ctx)) { > > + ret = PTR_ERR(inst->v4l2_fh.m2m_ctx); > > + goto cleanup_inst; > > + } > > + > > + v4l2_ctrl_handler_init(&inst->v4l2_ctrl_hdl, 10); > > + v4l2_ctrl_new_custom(&inst->v4l2_ctrl_hdl, &wave5_vpu_thumbnail_mode, NULL); > > + v4l2_ctrl_new_std(&inst->v4l2_ctrl_hdl, &wave5_vpu_dec_ctrl_ops, > > + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 1); > > + > > + if (inst->v4l2_ctrl_hdl.error) { > > + ret = -ENODEV; > > + goto cleanup_inst; > > + } > > + > > + inst->v4l2_fh.ctrl_handler = &inst->v4l2_ctrl_hdl; > > + v4l2_ctrl_handler_setup(&inst->v4l2_ctrl_hdl); > > + > > + wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); > > + inst->colorspace = V4L2_COLORSPACE_REC709; > > + inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; > > + inst->hsv_enc = 0; > > + inst->quantization = V4L2_QUANTIZATION_DEFAULT; > > + inst->xfer_func = V4L2_XFER_FUNC_DEFAULT; > > + > > + init_completion(&inst->irq_done); > > + ret = kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL); > > + if (ret) { > > + dev_err(inst->dev->dev, "failed to allocate fifo\n"); > > + goto cleanup_inst; > > + } > > + > > + inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); > > + if (inst->id < 0) { > > + dev_warn(inst->dev->dev, "Allocating instance ID, fail: %d\n", inst->id); > > + ret = inst->id; > > + goto cleanup_inst; > > + } > > + > > + return 0; > > + > > +cleanup_inst: > > + wave5_cleanup_instance(inst); > > + return ret; > > +} > > + > > +static int wave5_vpu_dec_release(struct file *filp) > > +{ > > + return wave5_vpu_release_device(filp, wave5_vpu_dec_close, "decoder"); > > +} > > + > > +static const struct v4l2_file_operations wave5_vpu_dec_fops = { > > + .owner = THIS_MODULE, > > + .open = wave5_vpu_open_dec, > > + .release = wave5_vpu_dec_release, > > + .unlocked_ioctl = video_ioctl2, > > + .poll = v4l2_m2m_fop_poll, > > + .mmap = v4l2_m2m_fop_mmap, > > +}; > > + > > +int wave5_vpu_dec_register_device(struct vpu_device *dev) > > +{ > > + struct video_device *vdev_dec; > > + int ret; > > + > > + vdev_dec = devm_kzalloc(dev->v4l2_dev.dev, sizeof(*vdev_dec), GFP_KERNEL); > > + if (!vdev_dec) > > + return -ENOMEM; > > + > > + dev->video_dev_dec = vdev_dec; > > + > > + strscpy(vdev_dec->name, VPU_DEC_DEV_NAME, sizeof(vdev_dec->name)); > > + vdev_dec->fops = &wave5_vpu_dec_fops; > > + vdev_dec->ioctl_ops = &wave5_vpu_dec_ioctl_ops; > > + vdev_dec->release = video_device_release_empty; > > + vdev_dec->v4l2_dev = &dev->v4l2_dev; > > + vdev_dec->vfl_dir = VFL_DIR_M2M; > > + vdev_dec->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; > > + vdev_dec->lock = &dev->dev_lock; > > + > > + ret = video_register_device(vdev_dec, VFL_TYPE_VIDEO, -1); > > + if (ret) > > + return ret; > > + > > + video_set_drvdata(vdev_dec, dev); > > + > > + return 0; > > +} > > + > > +void wave5_vpu_dec_unregister_device(struct vpu_device *dev) > > +{ > > + video_unregister_device(dev->video_dev_dec); > > +} > > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c > > new file mode 100644 > > index 000000000000..285111c2d9cd > > --- /dev/null > > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c > > @@ -0,0 +1,1746 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > > +/* > > + * Wave5 series multi-standard codec IP - encoder interface > > + * > > + * Copyright (C) 2021 CHIPS&MEDIA INC > > + */ > > + > > +#include "wave5-helper.h" > > + > > +#define VPU_ENC_DEV_NAME "C&M Wave5 VPU encoder" > > +#define VPU_ENC_DRV_NAME "wave5-enc" > > + > > +static const struct vpu_format enc_fmt_list[FMT_TYPES][MAX_FMTS] = { > > + [VPU_FMT_TYPE_CODEC] = { > > + { > > + .v4l2_pix_fmt = V4L2_PIX_FMT_HEVC, > > + .max_width = W5_MAX_ENC_PIC_WIDTH, > > + .min_width = W5_MIN_ENC_PIC_WIDTH, > > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > > + }, > > + { > > + .v4l2_pix_fmt = V4L2_PIX_FMT_H264, > > + .max_width = W5_MAX_ENC_PIC_WIDTH, > > + .min_width = W5_MIN_ENC_PIC_WIDTH, > > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > > + }, > > + }, > > + [VPU_FMT_TYPE_RAW] = { > > + { > > + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420, > > + .max_width = W5_MAX_ENC_PIC_WIDTH, > > + .min_width = W5_MIN_ENC_PIC_WIDTH, > > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > > + }, > > + { > > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV12, > > + .max_width = W5_MAX_ENC_PIC_WIDTH, > > + .min_width = W5_MIN_ENC_PIC_WIDTH, > > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > > + }, > > + { > > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV21, > > + .max_width = W5_MAX_ENC_PIC_WIDTH, > > + .min_width = W5_MIN_ENC_PIC_WIDTH, > > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > > + }, > > + { > > + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M, > > + .max_width = W5_MAX_ENC_PIC_WIDTH, > > + .min_width = W5_MIN_ENC_PIC_WIDTH, > > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > > + }, > > + { > > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV12M, > > + .max_width = W5_MAX_ENC_PIC_WIDTH, > > + .min_width = W5_MIN_ENC_PIC_WIDTH, > > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > > + }, > > + { > > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, > > + .max_width = W5_MAX_ENC_PIC_WIDTH, > > + .min_width = W5_MIN_ENC_PIC_WIDTH, > > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > > + }, > > + } > > +}; > > + > > +static enum wave_std wave5_to_vpu_wavestd(unsigned int v4l2_pix_fmt) > > +{ > > + switch (v4l2_pix_fmt) { > > + case V4L2_PIX_FMT_H264: > > + return W_AVC_ENC; > > + case V4L2_PIX_FMT_HEVC: > > + return W_HEVC_ENC; > > + default: > > + return STD_UNKNOWN; > > + } > > +} > > + > > +static struct vb2_v4l2_buffer *wave5_get_valid_src_buf(struct vpu_instance *inst) > > +{ > > + struct v4l2_m2m_buffer *v4l2_m2m_buf; > > + > > + v4l2_m2m_for_each_src_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { > > + struct vb2_v4l2_buffer *vb2_v4l2_buf; > > + struct vpu_buffer *vpu_buf = NULL; > > + > > + vb2_v4l2_buf = &v4l2_m2m_buf->vb; > > + vpu_buf = wave5_to_vpu_buf(vb2_v4l2_buf); > > + > > + if (!vpu_buf->consumed) { > > + dev_dbg(inst->dev->dev, "%s: src buf (index: %u) has not been consumed\n", > > + __func__, vb2_v4l2_buf->vb2_buf.index); > > + return vb2_v4l2_buf; > > + } > > + } > > + > > + return NULL; > > +} > > + > > +static struct vb2_v4l2_buffer *wave5_get_valid_dst_buf(struct vpu_instance *inst) > > +{ > > + struct v4l2_m2m_buffer *v4l2_m2m_buf; > > + > > + v4l2_m2m_for_each_dst_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { > > + struct vb2_v4l2_buffer *vb2_v4l2_buf; > > + struct vpu_buffer *vpu_buf = NULL; > > + > > + vb2_v4l2_buf = &v4l2_m2m_buf->vb; > > + vpu_buf = wave5_to_vpu_buf(vb2_v4l2_buf); > > + > > + if (!vpu_buf->consumed) { > > + dev_dbg(inst->dev->dev, "%s: dst buf (index: %u) has not been consumed\n", > > + __func__, vb2_v4l2_buf->vb2_buf.index); > > + return vb2_v4l2_buf; > > + } > > + } > > + > > + return NULL; > > +} > > + > > +static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width, > > + unsigned int height) > > +{ > > + switch (pix_mp->pixelformat) { > > + case V4L2_PIX_FMT_YUV420: > > + case V4L2_PIX_FMT_NV12: > > + case V4L2_PIX_FMT_NV21: > > + pix_mp->width = width; > > + pix_mp->height = height; > > + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); > > + pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height * 3 / 2; > > + break; > > + case V4L2_PIX_FMT_YUV420M: > > + pix_mp->width = width; > > + pix_mp->height = height; > > + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); > > + pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height; > > + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; > > + pix_mp->plane_fmt[1].sizeimage = round_up(width, 32) * height / 4; > > + pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; > > + pix_mp->plane_fmt[2].sizeimage = round_up(width, 32) * height / 4; > > + break; > > + case V4L2_PIX_FMT_NV12M: > > + case V4L2_PIX_FMT_NV21M: > > + pix_mp->width = width; > > + pix_mp->height = height; > > + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); > > + pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height; > > + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); > > + pix_mp->plane_fmt[1].sizeimage = round_up(width, 32) * height / 2; > > + break; > > + default: > > + pix_mp->width = width; > > + pix_mp->height = height; > > + pix_mp->plane_fmt[0].bytesperline = 0; > > + pix_mp->plane_fmt[0].sizeimage = width * height; > > + break; > > + } > > +} > > + > > +static void wave5_vpu_enc_start_encode(struct vpu_instance *inst) > > +{ > > + u32 max_cmd_q = 0; > > + > > + max_cmd_q = (inst->src_buf_count < COMMAND_QUEUE_DEPTH) ? > > + inst->src_buf_count : COMMAND_QUEUE_DEPTH; > > + > > + if (inst->state == VPU_INST_STATE_STOP) > > + max_cmd_q = 1; > > + > > + while (max_cmd_q) { > > + struct vb2_v4l2_buffer *src_buf; > > + struct vb2_v4l2_buffer *dst_buf; > > + struct vpu_buffer *src_vbuf; > > + struct vpu_buffer *dst_vbuf; > > + struct frame_buffer frame_buf; > > + struct enc_param pic_param; > > + u32 stride = ALIGN(inst->dst_fmt.width, 32); > > + u32 luma_size = (stride * inst->dst_fmt.height); > > + u32 chroma_size = ((stride / 2) * (inst->dst_fmt.height / 2)); > > + u32 fail_res; > > + int ret; > > + > > + memset(&pic_param, 0, sizeof(struct enc_param)); > > + memset(&frame_buf, 0, sizeof(struct frame_buffer)); > > + > > + src_buf = wave5_get_valid_src_buf(inst); > > + dst_buf = wave5_get_valid_dst_buf(inst); > > + > > + if (!dst_buf) { > > + dev_dbg(inst->dev->dev, "%s: No valid dst buf\n", __func__); > > + break; > > + } > > + > > + dst_vbuf = wave5_to_vpu_buf(dst_buf); > > + pic_param.pic_stream_buffer_addr = > > + vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); > > + pic_param.pic_stream_buffer_size = > > + vb2_plane_size(&dst_buf->vb2_buf, 0); > > + > > + if (!src_buf) { > > + dev_dbg(inst->dev->dev, "%s: No valid src buf\n", __func__); > > + if (inst->state == VPU_INST_STATE_STOP) > > + pic_param.src_end_flag = true; > > + else > > + break; > > + } else { > > + src_vbuf = wave5_to_vpu_buf(src_buf); > > + if (inst->src_fmt.num_planes == 1) { > > + frame_buf.buf_y = > > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); > > + frame_buf.buf_cb = frame_buf.buf_y + luma_size; > > + frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; > > + } else if (inst->src_fmt.num_planes == 2) { > > + frame_buf.buf_y = > > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); > > + frame_buf.buf_cb = > > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); > > + frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; > > + } else if (inst->src_fmt.num_planes == 3) { > > + frame_buf.buf_y = > > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); > > + frame_buf.buf_cb = > > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); > > + frame_buf.buf_cr = > > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 2); > > + } > > + frame_buf.stride = stride; > > + pic_param.src_idx = src_buf->vb2_buf.index; > > + } > > + > > + pic_param.source_frame = &frame_buf; > > + pic_param.code_option.implicit_header_encode = 1; > > + ret = wave5_vpu_enc_start_one_frame(inst, &pic_param, &fail_res); > > + if (ret) { > > + if (fail_res == WAVE5_SYSERR_QUEUEING_FAIL) > > + break; > > + > > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame fail: %d\n", > > + __func__, ret); > > + src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); > > + if (!src_buf) { > > + dev_dbg(inst->dev->dev, > > + "%s: Removing src buf failed, the queue is empty\n", > > + __func__); > > + continue; > > + } > > + dst_buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx); > > + if (!dst_buf) { > > + dev_dbg(inst->dev->dev, > > + "%s: Removing dst buf failed, the queue is empty\n", > > + __func__); > > + continue; > > + } > > + inst->state = VPU_INST_STATE_STOP; > > + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); > > + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR); > > + } else { > > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame success\n", > > + __func__); > > + if (src_buf) > > + src_vbuf->consumed = true; > > + if (dst_buf) > > + dst_vbuf->consumed = true; > > + } > > + > > + max_cmd_q--; > > + } > > +} > > + > > +static void wave5_vpu_enc_stop_encode(struct vpu_instance *inst) > > +{ > > + inst->state = VPU_INST_STATE_STOP; > > + > > + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); > > +} > > + > > +static void wave5_vpu_enc_finish_encode(struct vpu_instance *inst) > > +{ > > + int ret; > > + struct enc_output_info enc_output_info; > > + u32 irq_status; > > + struct vb2_v4l2_buffer *dst_buf = NULL; > > + struct v4l2_m2m_buffer *v4l2_m2m_buf = NULL; > > + > > + if (kfifo_out(&inst->irq_status, &irq_status, sizeof(int))) > > + wave5_vpu_clear_interrupt_ex(inst, irq_status); > > + > > + ret = wave5_vpu_enc_get_output_info(inst, &enc_output_info); > > + if (ret) { > > + dev_dbg(inst->dev->dev, > > + "%s: vpu_enc_get_output_info fail: %d reason: %u | info: %u\n", > > + __func__, ret, enc_output_info.error_reason, enc_output_info.warn_info); > > + return; > > + } > > + > > + v4l2_m2m_for_each_dst_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { > > + dst_buf = &v4l2_m2m_buf->vb; > > + if (enc_output_info.bitstream_buffer == > > + vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0)) > > + break; > > + } > > + > > + if (enc_output_info.enc_src_idx >= 0) { > > + struct vb2_v4l2_buffer *src_buf = > > + v4l2_m2m_src_buf_remove_by_idx(inst->v4l2_fh.m2m_ctx, > > + enc_output_info.enc_src_idx); > > + > > + inst->timestamp = src_buf->vb2_buf.timestamp; > > + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); > > + } > > + > > + if (enc_output_info.recon_frame_index == RECON_IDX_FLAG_ENC_END) { > > + static const struct v4l2_event vpu_event_eos = { > > + .type = V4L2_EVENT_EOS > > + }; > > + > > + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, 0); > > + dst_buf->vb2_buf.timestamp = inst->timestamp; > > + dst_buf->field = V4L2_FIELD_NONE; > > + dst_buf->flags |= V4L2_BUF_FLAG_LAST; > > + v4l2_m2m_dst_buf_remove_by_buf(inst->v4l2_fh.m2m_ctx, dst_buf); > > + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); > > + > > + inst->state = VPU_INST_STATE_PIC_RUN; > > + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos); > > + > > + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); > > + } else { > > + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, enc_output_info.bitstream_size); > > + > > + dst_buf->vb2_buf.timestamp = inst->timestamp; > > + dst_buf->field = V4L2_FIELD_NONE; > > + if (enc_output_info.pic_type == PIC_TYPE_I) { > > + if (enc_output_info.enc_vcl_nut == 19 || > > + enc_output_info.enc_vcl_nut == 20) > > + dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME; > > + else > > + dst_buf->flags |= V4L2_BUF_FLAG_PFRAME; > > + } else if (enc_output_info.pic_type == PIC_TYPE_P) { > > + dst_buf->flags |= V4L2_BUF_FLAG_PFRAME; > > + } else if (enc_output_info.pic_type == PIC_TYPE_B) { > > + dst_buf->flags |= V4L2_BUF_FLAG_BFRAME; > > + } > > + > > + v4l2_m2m_dst_buf_remove_by_buf(inst->v4l2_fh.m2m_ctx, dst_buf); > > + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); > > + > > + dev_dbg(inst->dev->dev, "%s: frame_cycle %8u\n", > > + __func__, enc_output_info.frame_cycle); > > + } > > +} > > + > > +static int wave5_vpu_enc_querycap(struct file *file, void *fh, struct v4l2_capability *cap) > > +{ > > + strscpy(cap->driver, VPU_ENC_DRV_NAME, sizeof(cap->driver)); > > + strscpy(cap->card, VPU_ENC_DRV_NAME, sizeof(cap->card)); > > + strscpy(cap->bus_info, "platform:" VPU_ENC_DRV_NAME, sizeof(cap->bus_info)); > > Can be dropped. > > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_enum_framesizes(struct file *f, void *fh, struct v4l2_frmsizeenum *fsize) > > +{ > > + const struct vpu_format *vpu_fmt; > > + > > + if (fsize->index) > > + return -EINVAL; > > + > > + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, enc_fmt_list[VPU_FMT_TYPE_CODEC]); > > + if (!vpu_fmt) { > > + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, enc_fmt_list[VPU_FMT_TYPE_RAW]); > > + if (!vpu_fmt) > > + return -EINVAL; > > + } > > + > > + fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; > > + fsize->stepwise.min_width = vpu_fmt->min_width; > > + fsize->stepwise.max_width = vpu_fmt->max_width; > > + fsize->stepwise.step_width = 1; > > + fsize->stepwise.min_height = vpu_fmt->min_height; > > + fsize->stepwise.max_height = vpu_fmt->max_height; > > + fsize->stepwise.step_height = 1; > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_enum_fmt_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + const struct vpu_format *vpu_fmt; > > + > > + dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); > > + > > + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, enc_fmt_list[VPU_FMT_TYPE_CODEC]); > > + if (!vpu_fmt) > > + return -EINVAL; > > + > > + f->pixelformat = vpu_fmt->v4l2_pix_fmt; > > + f->flags = 0; > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + const struct vpu_format *vpu_fmt; > > + > > + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > > + > > + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) > > + return -EINVAL; > > + > > + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]); > > + if (!vpu_fmt) { > > + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; > > + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; > > + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height); > > + } else { > > + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); > > + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); > > + > > + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; > > + f->fmt.pix_mp.num_planes = 1; > > + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); > > + } > > + > > + f->fmt.pix_mp.flags = 0; > > + f->fmt.pix_mp.field = V4L2_FIELD_NONE; > > + f->fmt.pix_mp.colorspace = inst->colorspace; > > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > > + f->fmt.pix_mp.quantization = inst->quantization; > > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > > + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + int i, ret; > > + > > + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > > + > > + ret = wave5_vpu_enc_try_fmt_cap(file, fh, f); > > + if (ret) > > + return ret; > > + > > + inst->dst_fmt.width = f->fmt.pix_mp.width; > > + inst->dst_fmt.height = f->fmt.pix_mp.height; > > + inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat; > > + inst->dst_fmt.field = f->fmt.pix_mp.field; > > + inst->dst_fmt.flags = f->fmt.pix_mp.flags; > > + inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes; > > + for (i = 0; i < inst->dst_fmt.num_planes; i++) { > > + inst->dst_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; > > + inst->dst_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; > > + } > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + int i; > > + > > + f->fmt.pix_mp.width = inst->dst_fmt.width; > > + f->fmt.pix_mp.height = inst->dst_fmt.height; > > + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; > > + f->fmt.pix_mp.field = inst->dst_fmt.field; > > + f->fmt.pix_mp.flags = inst->dst_fmt.flags; > > + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; > > + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { > > + f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->dst_fmt.plane_fmt[i].bytesperline; > > + f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->dst_fmt.plane_fmt[i].sizeimage; > > + } > > + > > + f->fmt.pix_mp.colorspace = inst->colorspace; > > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > > + f->fmt.pix_mp.quantization = inst->quantization; > > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_enum_fmt_out(struct file *file, void *fh, struct v4l2_fmtdesc *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + const struct vpu_format *vpu_fmt; > > + > > + dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); > > + > > + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, enc_fmt_list[VPU_FMT_TYPE_RAW]); > > + if (!vpu_fmt) > > + return -EINVAL; > > + > > + f->pixelformat = vpu_fmt->v4l2_pix_fmt; > > + f->flags = 0; > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + const struct vpu_format *vpu_fmt; > > + > > + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > > + > > + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > > + return -EINVAL; > > + > > + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_RAW]); > > + if (!vpu_fmt) { > > + f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; > > + f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; > > + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height); > > + } else { > > + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); > > + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); > > + const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); > > + > > + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; > > + f->fmt.pix_mp.num_planes = info->mem_planes; > > + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); > > + } > > + > > + f->fmt.pix_mp.flags = 0; > > + f->fmt.pix_mp.field = V4L2_FIELD_NONE; > > + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + int i, ret; > > + > > + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > > + > > + ret = wave5_vpu_enc_try_fmt_out(file, fh, f); > > + if (ret) > > + return ret; > > + > > + inst->src_fmt.width = f->fmt.pix_mp.width; > > + inst->src_fmt.height = f->fmt.pix_mp.height; > > + inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat; > > + inst->src_fmt.field = f->fmt.pix_mp.field; > > + inst->src_fmt.flags = f->fmt.pix_mp.flags; > > + inst->src_fmt.num_planes = f->fmt.pix_mp.num_planes; > > + for (i = 0; i < inst->src_fmt.num_planes; i++) { > > + inst->src_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; > > + inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; > > + } > > + > > + if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12 || > > + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12M) { > > + inst->cbcr_interleave = true; > > + inst->nv21 = false; > > + } else if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21 || > > + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21M) { > > + inst->cbcr_interleave = true; > > + inst->nv21 = true; > > + } else { > > + inst->cbcr_interleave = false; > > + inst->nv21 = false; > > + } > > + > > + inst->colorspace = f->fmt.pix_mp.colorspace; > > + inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; > > + inst->hsv_enc = f->fmt.pix_mp.hsv_enc; > > + inst->quantization = f->fmt.pix_mp.quantization; > > + inst->xfer_func = f->fmt.pix_mp.xfer_func; > > + > > + wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height); > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_g_selection(struct file *file, void *fh, struct v4l2_selection *s) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + > > + dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target); > > + > > + if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { > > + switch (s->target) { > > + case V4L2_SEL_TGT_CROP_DEFAULT: > > + case V4L2_SEL_TGT_CROP_BOUNDS: > > + s->r.left = 0; > > + s->r.top = 0; > > + s->r.width = inst->dst_fmt.width; > > + s->r.height = inst->dst_fmt.height; > > + break; > > + case V4L2_SEL_TGT_CROP: > > + s->r.left = 0; > > + s->r.top = 0; > > + s->r.width = inst->dst_fmt.width; > > + s->r.height = inst->dst_fmt.height; > > + dev_dbg(inst->dev->dev, "%s: V4L2_SEL_TGT_CROP width: %u | height: %u\n", > > + __func__, s->r.width, s->r.height); > > + break; > > + default: > > + return -EINVAL; > > + } > > + } else { > > + return -EINVAL; > > + } > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_s_selection(struct file *file, void *fh, struct v4l2_selection *s) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + > > + if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) > > + return -EINVAL; > > + > > + if (s->target != V4L2_SEL_TGT_CROP) > > + return -EINVAL; > > + > > + dev_dbg(inst->dev->dev, "%s: V4L2_SEL_TGT_CROP width: %u | height: %u\n", > > + __func__, s->r.width, s->r.height); > > + > > + s->r.left = 0; > > + s->r.top = 0; > > + s->r.width = inst->src_fmt.width; > > + s->r.height = inst->src_fmt.height; > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_encoder_cmd(struct file *file, void *fh, struct v4l2_encoder_cmd *ec) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + int ret; > > + > > + ret = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, ec); > > + if (ret) > > + return ret; > > + > > + if (!wave5_vpu_both_queues_are_streaming(inst)) > > + return 0; > > + > > + switch (ec->cmd) { > > + case V4L2_ENC_CMD_STOP: > > + inst->state = VPU_INST_STATE_STOP; > > + inst->ops->start_process(inst); > > + break; > > + case V4L2_ENC_CMD_START: > > + break; > > + default: > > + return -EINVAL; > > + } > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + > > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, a->type); > > + > > + if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > > + return -EINVAL; > > + > > + a->parm.output.capability = V4L2_CAP_TIMEPERFRAME; > > + a->parm.output.timeperframe.numerator = 1; > > + a->parm.output.timeperframe.denominator = inst->frame_rate; > > + > > + dev_dbg(inst->dev->dev, "%s: numerator: %u | denominator: %u\n", > > + __func__, a->parm.output.timeperframe.numerator, > > + a->parm.output.timeperframe.denominator); > > + > > + return 0; > > +} > > + > > +static int wave5_vpu_enc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a) > > +{ > > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > > + > > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, a->type); > > + > > + if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > > + return -EINVAL; > > + > > + a->parm.output.capability = V4L2_CAP_TIMEPERFRAME; > > + if (a->parm.output.timeperframe.denominator && a->parm.output.timeperframe.numerator) { > > + inst->frame_rate = a->parm.output.timeperframe.denominator / > > + a->parm.output.timeperframe.numerator; > > + } else { > > + a->parm.output.timeperframe.numerator = 1; > > + a->parm.output.timeperframe.denominator = inst->frame_rate; > > + } > > + > > + dev_dbg(inst->dev->dev, "%s: numerator: %u | denominator: %u\n", > > + __func__, a->parm.output.timeperframe.numerator, > > + a->parm.output.timeperframe.denominator); > > + > > + return 0; > > +} > > + > > +static const struct v4l2_ioctl_ops wave5_vpu_enc_ioctl_ops = { > > + .vidioc_querycap = wave5_vpu_enc_querycap, > > + .vidioc_enum_framesizes = wave5_vpu_enc_enum_framesizes, > > + > > + .vidioc_enum_fmt_vid_cap = wave5_vpu_enc_enum_fmt_cap, > > + .vidioc_s_fmt_vid_cap_mplane = wave5_vpu_enc_s_fmt_cap, > > + .vidioc_g_fmt_vid_cap_mplane = wave5_vpu_enc_g_fmt_cap, > > + .vidioc_try_fmt_vid_cap_mplane = wave5_vpu_enc_try_fmt_cap, > > + > > + .vidioc_enum_fmt_vid_out = wave5_vpu_enc_enum_fmt_out, > > + .vidioc_s_fmt_vid_out_mplane = wave5_vpu_enc_s_fmt_out, > > + .vidioc_g_fmt_vid_out_mplane = wave5_vpu_g_fmt_out, > > + .vidioc_try_fmt_vid_out_mplane = wave5_vpu_enc_try_fmt_out, > > + > > + .vidioc_g_selection = wave5_vpu_enc_g_selection, > > + .vidioc_s_selection = wave5_vpu_enc_s_selection, > > + > > + .vidioc_g_parm = wave5_vpu_enc_g_parm, > > + .vidioc_s_parm = wave5_vpu_enc_s_parm, > > + > > + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, > > + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, > > + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, > > + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, > > + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, > > + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, > > + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, > > + .vidioc_streamon = v4l2_m2m_ioctl_streamon, > > + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, > > + > > + .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd, > > + .vidioc_encoder_cmd = wave5_vpu_enc_encoder_cmd, > > + > > + .vidioc_subscribe_event = wave5_vpu_subscribe_event, > > + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, > > +}; > > + > > +static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl) > > +{ > > + struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl); > > + > > + dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n", __func__, ctrl->name, ctrl->val); > > + > > + switch (ctrl->id) { > > + case V4L2_CID_HFLIP: > > + inst->mirror_direction |= (ctrl->val << 1); > > + break; > > + case V4L2_CID_VFLIP: > > + inst->mirror_direction |= ctrl->val; > > + break; > > + case V4L2_CID_ROTATE: > > + inst->rot_angle = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_VBV_SIZE: > > + inst->vbv_buf_size = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: > > + switch (ctrl->val) { > > + case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR: > > + inst->rc_mode = 0; > > + break; > > + case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR: > > + inst->rc_mode = 1; > > + break; > > + default: > > + return -EINVAL; > > + } > > + break; > > + case V4L2_CID_MPEG_VIDEO_BITRATE: > > + inst->bit_rate = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_GOP_SIZE: > > + inst->enc_param.avc_idr_period = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE: > > + inst->enc_param.independ_slice_mode = ctrl->val; > > + inst->enc_param.avc_slice_mode = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB: > > + inst->enc_param.independ_slice_mode_arg = ctrl->val; > > + inst->enc_param.avc_slice_arg = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: > > + inst->rc_enable = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE: > > + inst->enc_param.mb_level_rc_enable = ctrl->val; > > + inst->enc_param.cu_level_rc_enable = ctrl->val; > > + inst->enc_param.hvs_qp_enable = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: > > + switch (ctrl->val) { > > + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN: > > + inst->enc_param.profile = HEVC_PROFILE_MAIN; > > + inst->bit_depth = 8; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE: > > + inst->enc_param.profile = HEVC_PROFILE_STILLPICTURE; > > + inst->enc_param.en_still_picture = 1; > > + inst->bit_depth = 8; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10: > > + inst->enc_param.profile = HEVC_PROFILE_MAIN10; > > + inst->bit_depth = 10; > > + break; > > + default: > > + return -EINVAL; > > + } > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: > > + switch (ctrl->val) { > > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_1: > > + inst->enc_param.level = 10 * 3; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2: > > + inst->enc_param.level = 20 * 3; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1: > > + inst->enc_param.level = 21 * 3; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3: > > + inst->enc_param.level = 30 * 3; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1: > > + inst->enc_param.level = 31 * 3; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4: > > + inst->enc_param.level = 40 * 3; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1: > > + inst->enc_param.level = 41 * 3; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5: > > + inst->enc_param.level = 50 * 3; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1: > > + inst->enc_param.level = 51 * 3; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2: > > + inst->enc_param.level = 52 * 3; > > + break; > > + default: > > + return -EINVAL; > > + } > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: > > + inst->enc_param.min_qp_i = ctrl->val; > > + inst->enc_param.min_qp_p = ctrl->val; > > + inst->enc_param.min_qp_b = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: > > + inst->enc_param.max_qp_i = ctrl->val; > > + inst->enc_param.max_qp_p = ctrl->val; > > + inst->enc_param.max_qp_b = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: > > + inst->enc_param.intra_qp = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE: > > + switch (ctrl->val) { > > + case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED: > > + inst->enc_param.disable_deblk = 1; > > + inst->enc_param.sao_enable = 0; > > + inst->enc_param.lf_cross_slice_boundary_enable = 0; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED: > > + inst->enc_param.disable_deblk = 0; > > + inst->enc_param.sao_enable = 1; > > + inst->enc_param.lf_cross_slice_boundary_enable = 1; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY: > > + inst->enc_param.disable_deblk = 0; > > + inst->enc_param.sao_enable = 1; > > + inst->enc_param.lf_cross_slice_boundary_enable = 0; > > + break; > > + default: > > + return -EINVAL; > > + } > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2: > > + inst->enc_param.beta_offset_div2 = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2: > > + inst->enc_param.tc_offset_div2 = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE: > > + switch (ctrl->val) { > > + case V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE: > > + inst->enc_param.decoding_refresh_type = 0; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA: > > + inst->enc_param.decoding_refresh_type = 1; > > + break; > > + case V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR: > > + inst->enc_param.decoding_refresh_type = 2; > > + break; > > + default: > > + return -EINVAL; > > + } > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD: > > + inst->enc_param.intra_period = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU: > > + inst->enc_param.lossless_enable = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED: > > + inst->enc_param.const_intra_pred_flag = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT: > > + inst->enc_param.wpp_enable = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING: > > + inst->enc_param.strong_intra_smooth_enable = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1: > > + inst->enc_param.max_num_merge = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION: > > + inst->enc_param.tmvp_enable = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_PROFILE: > > + switch (ctrl->val) { > > + case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: > > + case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: > > + inst->enc_param.profile = H264_PROFILE_BP; > > + inst->bit_depth = 8; > > + break; > > + case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: > > + inst->enc_param.profile = H264_PROFILE_MP; > > + inst->bit_depth = 8; > > + break; > > + case V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED: > > + inst->enc_param.profile = H264_PROFILE_EXTENDED; > > + inst->bit_depth = 8; > > + break; > > + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: > > + inst->enc_param.profile = H264_PROFILE_HP; > > + inst->bit_depth = 8; > > + break; > > + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10: > > + inst->enc_param.profile = H264_PROFILE_HIGH10; > > + inst->bit_depth = 10; > > + break; > > + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422: > > + inst->enc_param.profile = H264_PROFILE_HIGH422; > > + inst->bit_depth = 10; > > + break; > > + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE: > > + inst->enc_param.profile = H264_PROFILE_HIGH444; > > + inst->bit_depth = 10; > > + break; > > + default: > > + return -EINVAL; > > + } > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_LEVEL: > > + switch (ctrl->val) { > > + case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: > > + inst->enc_param.level = 10; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_1B: > > + inst->enc_param.level = 9; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: > > + inst->enc_param.level = 11; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: > > + inst->enc_param.level = 12; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: > > + inst->enc_param.level = 13; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: > > + inst->enc_param.level = 20; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: > > + inst->enc_param.level = 21; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: > > + inst->enc_param.level = 22; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: > > + inst->enc_param.level = 30; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: > > + inst->enc_param.level = 31; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: > > + inst->enc_param.level = 32; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: > > + inst->enc_param.level = 40; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_4_1: > > + inst->enc_param.level = 41; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_4_2: > > + inst->enc_param.level = 42; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_5_0: > > + inst->enc_param.level = 50; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LEVEL_5_1: > > + inst->enc_param.level = 51; > > + break; > > + default: > > + return -EINVAL; > > + } > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: > > + inst->enc_param.min_qp_i = ctrl->val; > > + inst->enc_param.min_qp_p = ctrl->val; > > + inst->enc_param.min_qp_b = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: > > + inst->enc_param.max_qp_i = ctrl->val; > > + inst->enc_param.max_qp_p = ctrl->val; > > + inst->enc_param.max_qp_b = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: > > + inst->enc_param.intra_qp = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE: > > + switch (ctrl->val) { > > + case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED: > > + inst->enc_param.disable_deblk = 1; > > + inst->enc_param.lf_cross_slice_boundary_enable = 1; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED: > > + inst->enc_param.disable_deblk = 0; > > + inst->enc_param.lf_cross_slice_boundary_enable = 1; > > + break; > > + case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY: > > + inst->enc_param.disable_deblk = 0; > > + inst->enc_param.lf_cross_slice_boundary_enable = 0; > > + break; > > + default: > > + return -EINVAL; > > + } > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA: > > + inst->enc_param.beta_offset_div2 = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA: > > + inst->enc_param.tc_offset_div2 = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM: > > + inst->enc_param.transform8x8_enable = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: > > + inst->enc_param.const_intra_pred_flag = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET: > > + inst->enc_param.chroma_cb_qp_offset = ctrl->val; > > + inst->enc_param.chroma_cr_qp_offset = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD: > > + inst->enc_param.intra_period = ctrl->val; > > + break; > > + case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: > > + inst->enc_param.entropy_coding_mode = ctrl->val; > > + break; > > + case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT: > > + break; > > + default: > > + return -EINVAL; > > + } > > + > > + return 0; > > +} > > + > > +static const struct v4l2_ctrl_ops wave5_vpu_enc_ctrl_ops = { > > + .s_ctrl = wave5_vpu_enc_s_ctrl, > > +}; > > + > > +static void wave5_set_enc_openparam(struct enc_open_param *open_param, > > + struct vpu_instance *inst) > > +{ > > + struct enc_wave_param input = inst->enc_param; > > + u32 num_ctu_row = ALIGN(inst->dst_fmt.height, 64) / 64; > > + u32 num_mb_row = ALIGN(inst->dst_fmt.height, 16) / 16; > > + > > + open_param->wave_param.gop_preset_idx = PRESET_IDX_IPP_SINGLE; > > + open_param->wave_param.hvs_qp_scale = 2; > > + open_param->wave_param.hvs_max_delta_qp = 10; > > + open_param->wave_param.skip_intra_trans = 1; > > + open_param->wave_param.intra_nx_n_enable = 1; > > + open_param->wave_param.nr_intra_weight_y = 7; > > + open_param->wave_param.nr_intra_weight_cb = 7; > > + open_param->wave_param.nr_intra_weight_cr = 7; > > + open_param->wave_param.nr_inter_weight_y = 4; > > + open_param->wave_param.nr_inter_weight_cb = 4; > > + open_param->wave_param.nr_inter_weight_cr = 4; > > + open_param->wave_param.rdo_skip = 1; > > + open_param->wave_param.lambda_scaling_enable = 1; > > + > > + open_param->stream_endian = VPU_STREAM_ENDIAN; > > + open_param->source_endian = VPU_SOURCE_ENDIAN; > > + open_param->line_buf_int_en = true; > > + open_param->pic_width = inst->dst_fmt.width; > > + open_param->pic_height = inst->dst_fmt.height; > > + open_param->frame_rate_info = inst->frame_rate; > > + open_param->rc_enable = inst->rc_enable; > > + if (inst->rc_enable) { > > + open_param->wave_param.initial_rc_qp = -1; > > + open_param->wave_param.rc_weight_param = 16; > > + open_param->wave_param.rc_weight_buf = 128; > > + } > > + open_param->wave_param.mb_level_rc_enable = input.mb_level_rc_enable; > > + open_param->wave_param.cu_level_rc_enable = input.cu_level_rc_enable; > > + open_param->wave_param.hvs_qp_enable = input.hvs_qp_enable; > > + open_param->bit_rate = inst->bit_rate; > > + open_param->vbv_buffer_size = inst->vbv_buf_size; > > + if (inst->rc_mode == 0) > > + open_param->vbv_buffer_size = 3000; > > + open_param->wave_param.profile = input.profile; > > + open_param->wave_param.en_still_picture = input.en_still_picture; > > + open_param->wave_param.level = input.level; > > + open_param->wave_param.internal_bit_depth = inst->bit_depth; > > + open_param->wave_param.intra_qp = input.intra_qp; > > + open_param->wave_param.min_qp_i = input.min_qp_i; > > + open_param->wave_param.max_qp_i = input.max_qp_i; > > + open_param->wave_param.min_qp_p = input.min_qp_p; > > + open_param->wave_param.max_qp_p = input.max_qp_p; > > + open_param->wave_param.min_qp_b = input.min_qp_b; > > + open_param->wave_param.max_qp_b = input.max_qp_b; > > + open_param->wave_param.disable_deblk = input.disable_deblk; > > + open_param->wave_param.lf_cross_slice_boundary_enable = > > + input.lf_cross_slice_boundary_enable; > > + open_param->wave_param.tc_offset_div2 = input.tc_offset_div2; > > + open_param->wave_param.beta_offset_div2 = input.beta_offset_div2; > > + open_param->wave_param.decoding_refresh_type = input.decoding_refresh_type; > > + open_param->wave_param.intra_period = input.intra_period; > > + if (inst->std == W_HEVC_ENC) { > > + if (input.intra_period == 0) { > > + open_param->wave_param.decoding_refresh_type = DEC_REFRESH_TYPE_IDR; > > + open_param->wave_param.intra_period = input.avc_idr_period; > > + } > > + } else { > > + open_param->wave_param.avc_idr_period = input.avc_idr_period; > > + } > > + open_param->wave_param.entropy_coding_mode = input.entropy_coding_mode; > > + open_param->wave_param.lossless_enable = input.lossless_enable; > > + open_param->wave_param.const_intra_pred_flag = input.const_intra_pred_flag; > > + open_param->wave_param.wpp_enable = input.wpp_enable; > > + open_param->wave_param.strong_intra_smooth_enable = input.strong_intra_smooth_enable; > > + open_param->wave_param.max_num_merge = input.max_num_merge; > > + open_param->wave_param.tmvp_enable = input.tmvp_enable; > > + open_param->wave_param.transform8x8_enable = input.transform8x8_enable; > > + open_param->wave_param.chroma_cb_qp_offset = input.chroma_cb_qp_offset; > > + open_param->wave_param.chroma_cr_qp_offset = input.chroma_cr_qp_offset; > > + open_param->wave_param.independ_slice_mode = input.independ_slice_mode; > > + open_param->wave_param.independ_slice_mode_arg = input.independ_slice_mode_arg; > > + open_param->wave_param.avc_slice_mode = input.avc_slice_mode; > > + open_param->wave_param.avc_slice_arg = input.avc_slice_arg; > > + open_param->wave_param.intra_mb_refresh_mode = input.intra_mb_refresh_mode; > > + if (input.intra_mb_refresh_mode != REFRESH_MB_MODE_NONE) { > > + if (num_mb_row >= input.intra_mb_refresh_arg) > > + open_param->wave_param.intra_mb_refresh_arg = > > + num_mb_row / input.intra_mb_refresh_arg; > > + else > > + open_param->wave_param.intra_mb_refresh_arg = num_mb_row; > > + } > > + open_param->wave_param.intra_refresh_mode = input.intra_refresh_mode; > > + if (input.intra_refresh_mode != 0) { > > + if (num_ctu_row >= input.intra_refresh_arg) > > + open_param->wave_param.intra_refresh_arg = > > + num_ctu_row / input.intra_refresh_arg; > > + else > > + open_param->wave_param.intra_refresh_arg = num_ctu_row; > > + } > > +} > > + > > +static int wave5_vpu_enc_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, > > + unsigned int *num_planes, unsigned int sizes[], > > + struct device *alloc_devs[]) > > +{ > > + struct vpu_instance *inst = vb2_get_drv_priv(q); > > + struct v4l2_pix_format_mplane inst_format = > > + (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; > > + unsigned int i; > > + int ret; > > + > > + dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, > > + *num_buffers, *num_planes, q->type); > > + > > + if (*num_planes) { > > + if (inst_format.num_planes != *num_planes) > > + return -EINVAL; > > + > > + for (i = 0; i < *num_planes; i++) { > > + if (sizes[i] < inst_format.plane_fmt[i].sizeimage) > > + return -EINVAL; > > + } > > + } else { > > + *num_planes = inst_format.num_planes; > > + for (i = 0; i < *num_planes; i++) { > > + sizes[i] = inst_format.plane_fmt[i].sizeimage; > > + dev_dbg(inst->dev->dev, "%s: size[%u]: %u\n", __func__, i, sizes[i]); > > + } > > + } > > + > > + dev_dbg(inst->dev->dev, "%s: size: %u\n", __func__, sizes[0]); > > + > > Same concerns here as for the queue_setup in the decoder. > > > + if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > > + unsigned int non_linear_num = 0; > > + u32 fb_stride = 0; > > + u32 fb_height = 0; > > + struct enc_open_param open_param; > > + struct enc_initial_info initial_info; > > + struct v4l2_ctrl *ctrl; > > + > > + memset(&open_param, 0, sizeof(struct enc_open_param)); > > + > > + inst->std = wave5_to_vpu_wavestd(inst->dst_fmt.pixelformat); > > + if (inst->std == STD_UNKNOWN) { > > + dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", > > + (char *)&inst->dst_fmt.pixelformat); > > + return -EINVAL; > > + } > > + > > + wave5_set_enc_openparam(&open_param, inst); > > + > > + ret = wave5_vpu_enc_open(inst, &open_param); > > + if (ret) { > > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_open, fail: %d\n", > > + __func__, ret); > > + return ret; > > + } > > + > > + inst->state = VPU_INST_STATE_OPEN; > > + > > + if (inst->mirror_direction) { > > + wave5_vpu_enc_give_command(inst, ENABLE_MIRRORING, NULL); > > + wave5_vpu_enc_give_command(inst, SET_MIRROR_DIRECTION, > > + &inst->mirror_direction); > > + } > > + if (inst->rot_angle) { > > + wave5_vpu_enc_give_command(inst, ENABLE_ROTATION, NULL); > > + wave5_vpu_enc_give_command(inst, SET_ROTATION_ANGLE, &inst->rot_angle); > > + } > > + > > + ret = wave5_vpu_enc_issue_seq_init(inst); > > + if (ret) { > > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_issue_seq_init, fail: %d\n", > > + __func__, ret); > > + return ret; > > + } > > + > > + if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) { > > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_wait_interrupt failed\n", __func__); > > + return -EINVAL; > > + } > > + > > + ret = wave5_vpu_enc_complete_seq_init(inst, &initial_info); > > + if (ret) > > + return ret; > > + > > + dev_dbg(inst->dev->dev, "%s: min_frame_buffer: %u | min_source_buffer: %u\n", > > + __func__, initial_info.min_frame_buffer_count, > > + initial_info.min_src_frame_count); > > + inst->state = VPU_INST_STATE_INIT_SEQ; > > + inst->min_src_buf_count = initial_info.min_src_frame_count + > > + COMMAND_QUEUE_DEPTH; > > + > > + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, > > + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT); > > + if (ctrl) > > + v4l2_ctrl_s_ctrl(ctrl, inst->min_src_buf_count); > > + > > + inst->min_dst_buf_count = initial_info.min_frame_buffer_count; > > + inst->src_buf_count = inst->min_src_buf_count; > > + > > + if (*num_buffers > inst->src_buf_count) > > + inst->src_buf_count = *num_buffers; > > + > > + *num_buffers = inst->src_buf_count; > > + non_linear_num = inst->min_dst_buf_count; > > + > > + fb_stride = ALIGN(inst->dst_fmt.width, 32); > > + fb_height = ALIGN(inst->dst_fmt.height, 32); > > + > > + for (i = 0; i < non_linear_num; i++) { > > + u32 luma_size = fb_stride * fb_height; > > + u32 chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; > > + > > + inst->frame_vbuf[i].size = luma_size + chroma_size; > > + ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->frame_vbuf[i]); > > + if (ret < 0) { > > + dev_dbg(inst->dev->dev, "%s: failed to allocate FBC buffer %zu\n", > > + __func__, inst->frame_vbuf[i].size); > > + goto free_buffers; > > + } > > + > > + inst->frame_buf[i].buf_y = inst->frame_vbuf[i].daddr; > > + inst->frame_buf[i].buf_cb = (dma_addr_t)-1; > > + inst->frame_buf[i].buf_cr = (dma_addr_t)-1; > > + inst->frame_buf[i].update_fb_info = true; > > + inst->frame_buf[i].size = inst->frame_vbuf[i].size; > > + } > > + > > + ret = wave5_vpu_enc_register_frame_buffer(inst, non_linear_num, fb_stride, > > + fb_height, COMPRESSED_FRAME_MAP); > > + if (ret) { > > + dev_dbg(inst->dev->dev, > > + "%s: wave5_vpu_enc_register_frame_buffer, fail: %d\n", > > + __func__, ret); > > + goto free_buffers; > > + } > > + > > + inst->state = VPU_INST_STATE_PIC_RUN; > > + } > > + > > + if (inst->state == VPU_INST_STATE_INIT_SEQ && > > + q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > > + *num_buffers = inst->src_buf_count; > > + dev_dbg(inst->dev->dev, "%s: src buf num: %u", __func__, *num_buffers); > > + } > > + > > + return 0; > > + > > +free_buffers: > > + for (i = 0; i < inst->min_dst_buf_count; i++) > > + wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[i]); > > + return ret; > > +} > > + > > +static void wave5_vpu_enc_buf_queue(struct vb2_buffer *vb) > > +{ > > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); > > + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); > > + struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); > > + > > + dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n", > > + __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), > > + vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); > > + > > + if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > > + vbuf->sequence = inst->queued_src_buf_num++; > > + else > > + vbuf->sequence = inst->queued_dst_buf_num++; > > + > > + vpu_buf->consumed = FALSE; > > + v4l2_m2m_buf_queue(inst->v4l2_fh.m2m_ctx, vbuf); > > + > > + if (vb2_start_streaming_called(vb->vb2_queue)) > > + inst->ops->start_process(inst); > > +} > > + > > +static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q) > > +{ > > + struct vpu_instance *inst = vb2_get_drv_priv(q); > > + struct vb2_v4l2_buffer *buf; > > + bool check_cmd = true; > > + > > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); > > + > > + if (wave5_vpu_both_queues_are_streaming(inst)) > > + inst->state = VPU_INST_STATE_STOP; > > + > > + while (check_cmd) { > > + struct queue_status_info q_status; > > + struct enc_output_info enc_output_info; > > + > > + wave5_vpu_enc_give_command(inst, ENC_GET_QUEUE_STATUS, &q_status); > > + > > + if (q_status.instance_queue_count + q_status.report_queue_count == 0) > > + break; > > + > > + if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) > > + break; > > + > > + if (wave5_vpu_enc_get_output_info(inst, &enc_output_info)) > > + dev_dbg(inst->dev->dev, "Getting encoding results from fw, fail\n"); > > + } > > + > > + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > > + while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { > > + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", > > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); > > + } > > + } else { > > + while ((buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx))) { > > + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", > > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > > + vb2_set_plane_payload(&buf->vb2_buf, 0, 0); > > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); > > + } > > + } > > +} > > + > > +static const struct vb2_ops wave5_vpu_enc_vb2_ops = { > > + .queue_setup = wave5_vpu_enc_queue_setup, > > + .wait_prepare = vb2_ops_wait_prepare, > > + .wait_finish = vb2_ops_wait_finish, > > + .buf_queue = wave5_vpu_enc_buf_queue, > > + .stop_streaming = wave5_vpu_enc_stop_streaming, > > +}; > > + > > +static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, > > + struct v4l2_pix_format_mplane *dst_fmt) > > +{ > > + unsigned int src_pix_fmt = enc_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; > > + const struct v4l2_format_info *src_fmt_info = v4l2_format_info(src_pix_fmt); > > + > > + src_fmt->pixelformat = src_pix_fmt; > > + src_fmt->field = V4L2_FIELD_NONE; > > + src_fmt->flags = 0; > > + src_fmt->num_planes = src_fmt_info->mem_planes; > > + wave5_update_pix_fmt(src_fmt, 416, 240); > > + > > + dst_fmt->pixelformat = enc_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; > > + dst_fmt->field = V4L2_FIELD_NONE; > > + dst_fmt->flags = 0; > > + dst_fmt->num_planes = 1; > > + wave5_update_pix_fmt(dst_fmt, 416, 240); > > +} > > + > > +static int wave5_vpu_enc_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) > > +{ > > + return wave5_vpu_queue_init(priv, src_vq, dst_vq, &wave5_vpu_enc_vb2_ops); > > +} > > + > > +static const struct vpu_instance_ops wave5_vpu_enc_inst_ops = { > > + .start_process = wave5_vpu_enc_start_encode, > > + .stop_process = wave5_vpu_enc_stop_encode, > > + .finish_process = wave5_vpu_enc_finish_encode, > > +}; > > + > > +static void wave5_vpu_enc_device_run(void *priv) > > +{ > > + struct vpu_instance *inst = priv; > > + > > + inst->ops->start_process(inst); > > +} > > + > > +static int wave5_vpu_enc_job_ready(void *priv) > > +{ > > + struct vpu_instance *inst = priv; > > + > > + if (inst->state == VPU_INST_STATE_STOP) > > + return 0; > > + > > + return 1; > > +} > > + > > +static void wave5_vpu_enc_job_abort(void *priv) > > +{ > > + struct vpu_instance *inst = priv; > > + > > + inst->ops->stop_process(inst); > > +} > > + > > +static const struct v4l2_m2m_ops wave5_vpu_enc_m2m_ops = { > > + .device_run = wave5_vpu_enc_device_run, > > + .job_ready = wave5_vpu_enc_job_ready, > > + .job_abort = wave5_vpu_enc_job_abort, > > +}; > > + > > +static int wave5_vpu_open_enc(struct file *filp) > > +{ > > + struct video_device *vdev = video_devdata(filp); > > + struct vpu_device *dev = video_drvdata(filp); > > + struct vpu_instance *inst = NULL; > > + struct v4l2_ctrl_handler *v4l2_ctrl_hdl; > > + int ret = 0; > > + > > + inst = kzalloc(sizeof(*inst), GFP_KERNEL); > > + if (!inst) > > + return -ENOMEM; > > + v4l2_ctrl_hdl = &inst->v4l2_ctrl_hdl; > > + > > + inst->dev = dev; > > + inst->type = VPU_INST_TYPE_ENC; > > + inst->ops = &wave5_vpu_enc_inst_ops; > > + > > + v4l2_fh_init(&inst->v4l2_fh, vdev); > > + filp->private_data = &inst->v4l2_fh; > > + v4l2_fh_add(&inst->v4l2_fh); > > + > > + INIT_LIST_HEAD(&inst->list); > > + list_add_tail(&inst->list, &dev->instances); > > + > > + inst->v4l2_m2m_dev = v4l2_m2m_init(&wave5_vpu_enc_m2m_ops); > > + if (IS_ERR(inst->v4l2_m2m_dev)) { > > + ret = PTR_ERR(inst->v4l2_m2m_dev); > > + dev_err(inst->dev->dev, "v4l2_m2m_init, fail: %d\n", ret); > > + goto cleanup_inst; > > + } > > + > > + inst->v4l2_fh.m2m_ctx = > > + v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_enc_queue_init); > > + if (IS_ERR(inst->v4l2_fh.m2m_ctx)) { > > + ret = PTR_ERR(inst->v4l2_fh.m2m_ctx); > > + goto cleanup_inst; > > + } > > + > > + v4l2_ctrl_handler_init(v4l2_ctrl_hdl, 50); > > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, > > + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, 0, > > + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN); > > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, > > + V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 0, > > + V4L2_MPEG_VIDEO_HEVC_LEVEL_1); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, > > + 0, 63, 1, 8); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP, > > + 0, 63, 1, 51); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP, > > + 0, 63, 1, 30); > > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE, > > + V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, 0, > > + V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2, > > + -6, 6, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2, > > + -6, 6, 1, 0); > > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE, > > + V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR, 0, > > + V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD, > > + 0, 2047, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU, > > + 0, 1, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED, > > + 0, 1, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT, > > + 0, 1, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING, > > + 0, 1, 1, 1); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1, > > + 1, 2, 1, 2); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION, > > + 0, 1, 1, 1); > > + > > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_PROFILE, > > + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE, 0, > > + V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE); > > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_LEVEL, > > + V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 0, > > + V4L2_MPEG_VIDEO_H264_LEVEL_1_0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_MIN_QP, > > + 0, 63, 1, 8); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_MAX_QP, > > + 0, 63, 1, 51); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, > > + 0, 63, 1, 30); > > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE, > > + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, 0, > > + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA, > > + -6, 6, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA, > > + -6, 6, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM, > > + 0, 1, 1, 1); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION, > > + 0, 1, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET, > > + -12, 12, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_I_PERIOD, > > + 0, 2047, 1, 0); > > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE, > > + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, 0, > > + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC); > > + > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_HFLIP, > > + 0, 1, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_VFLIP, > > + 0, 1, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_ROTATE, > > + 0, 270, 90, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_VBV_SIZE, > > + 10, 3000, 1, 3000); > > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_BITRATE_MODE, > > + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0, > > + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_BITRATE, > > + 0, 700000000, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_GOP_SIZE, > > + 0, 2047, 1, 0); > > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE, > > + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB, 0, > > + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, > > + 0, 0xFFFF, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE, > > + 0, 1, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE, > > + 0, 1, 1, 0); > > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > > + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1); > > + > > + if (v4l2_ctrl_hdl->error) { > > + ret = -ENODEV; > > + goto cleanup_inst; > > + } > > + > > + inst->v4l2_fh.ctrl_handler = v4l2_ctrl_hdl; > > + v4l2_ctrl_handler_setup(v4l2_ctrl_hdl); > > + > > + wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); > > + inst->colorspace = V4L2_COLORSPACE_REC709; > > + inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; > > + inst->hsv_enc = 0; > > + inst->quantization = V4L2_QUANTIZATION_DEFAULT; > > + inst->xfer_func = V4L2_XFER_FUNC_DEFAULT; > > + inst->frame_rate = 30; > > + > > + init_completion(&inst->irq_done); > > + ret = kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL); > > + if (ret) { > > + dev_err(inst->dev->dev, "Allocating fifo, fail: %d\n", ret); > > + goto cleanup_inst; > > + } > > + > > + inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); > > + if (inst->id < 0) { > > + dev_warn(inst->dev->dev, "Allocating instance ID, fail: %d\n", inst->id); > > + ret = inst->id; > > + goto cleanup_inst; > > + } > > + > > + return 0; > > + > > +cleanup_inst: > > + wave5_cleanup_instance(inst); > > + return ret; > > +} > > + > > +static int wave5_vpu_enc_release(struct file *filp) > > +{ > > + return wave5_vpu_release_device(filp, wave5_vpu_enc_close, "encoder"); > > +} > > + > > +static const struct v4l2_file_operations wave5_vpu_enc_fops = { > > + .owner = THIS_MODULE, > > + .open = wave5_vpu_open_enc, > > + .release = wave5_vpu_enc_release, > > + .unlocked_ioctl = video_ioctl2, > > + .poll = v4l2_m2m_fop_poll, > > + .mmap = v4l2_m2m_fop_mmap, > > +}; > > + > > +int wave5_vpu_enc_register_device(struct vpu_device *dev) > > +{ > > + struct video_device *vdev_enc; > > + int ret; > > + > > + vdev_enc = devm_kzalloc(dev->v4l2_dev.dev, sizeof(*vdev_enc), GFP_KERNEL); > > + if (!vdev_enc) > > + return -ENOMEM; > > + > > + dev->video_dev_enc = vdev_enc; > > + > > + strscpy(vdev_enc->name, VPU_ENC_DEV_NAME, sizeof(vdev_enc->name)); > > + vdev_enc->fops = &wave5_vpu_enc_fops; > > + vdev_enc->ioctl_ops = &wave5_vpu_enc_ioctl_ops; > > + vdev_enc->release = video_device_release_empty; > > + vdev_enc->v4l2_dev = &dev->v4l2_dev; > > + vdev_enc->vfl_dir = VFL_DIR_M2M; > > + vdev_enc->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; > > + vdev_enc->lock = &dev->dev_lock; > > + > > + ret = video_register_device(vdev_enc, VFL_TYPE_VIDEO, -1); > > + if (ret) > > + return ret; > > + > > + video_set_drvdata(vdev_enc, dev); > > + > > + return 0; > > +} > > + > > +void wave5_vpu_enc_unregister_device(struct vpu_device *dev) > > +{ > > + video_unregister_device(dev->video_dev_enc); > > +} > > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers/media/platform/chips-media/wave5/wave5-vpu.c > > new file mode 100644 > > index 000000000000..9c602168cffc > > --- /dev/null > > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c > > @@ -0,0 +1,362 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > > +/* > > + * Wave5 series multi-standard codec IP - platform driver > > + * > > + * Copyright (C) 2021 CHIPS&MEDIA INC > > + */ > > +#include <linux/kernel.h> > > +#include <linux/module.h> > > +#include <linux/platform_device.h> > > +#include <linux/clk.h> > > +#include <linux/of_address.h> > > +#include <linux/firmware.h> > > +#include <linux/interrupt.h> > > +#include "wave5-vpu.h" > > +#include "wave5-regdefine.h" > > +#include "wave5-vpuconfig.h" > > +#include "wave5.h" > > + > > +#define VPU_PLATFORM_DEVICE_NAME "vdec" > > +#define VPU_CLK_NAME "vcodec" > > + > > +#define WAVE5_IS_ENC BIT(0) > > +#define WAVE5_IS_DEC BIT(1) > > + > > +struct wave5_match_data { > > + int flags; > > + const char *fw_name; > > +}; > > + > > +int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout) > > +{ > > + int ret; > > + > > + ret = wait_for_completion_timeout(&inst->irq_done, > > + msecs_to_jiffies(timeout)); > > + if (!ret) > > + return -ETIMEDOUT; > > + > > + reinit_completion(&inst->irq_done); > > + > > + return 0; > > +} > > + > > +static void wave5_vpu_get_interrupt_for_inst(struct vpu_instance *inst, u32 status) > > +{ > > + struct vpu_device *dev = inst->dev; > > + u32 seq_done; > > + u32 cmd_done; > > + int val; > > + > > + seq_done = wave5_vdi_readl(dev, W5_RET_SEQ_DONE_INSTANCE_INFO); > > + cmd_done = wave5_vdi_readl(dev, W5_RET_QUEUE_CMD_DONE_INST); > > + > > + if (status & BIT(INT_WAVE5_INIT_SEQ)) { > > + if (seq_done & BIT(inst->id)) { > > + seq_done &= ~BIT(inst->id); > > + wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done); > > + val = BIT(INT_WAVE5_INIT_SEQ); > > + kfifo_in(&inst->irq_status, &val, sizeof(int)); > > + } > > + } > > + if (status & BIT(INT_WAVE5_ENC_SET_PARAM)) { > > + if (seq_done & BIT(inst->id)) { > > + seq_done &= ~BIT(inst->id); > > + wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done); > > + val = BIT(INT_WAVE5_ENC_SET_PARAM); > > + kfifo_in(&inst->irq_status, &val, sizeof(int)); > > + } > > + } > > + if (status & BIT(INT_WAVE5_DEC_PIC) || > > + status & BIT(INT_WAVE5_ENC_PIC)) { > > + if (cmd_done & BIT(inst->id)) { > > + cmd_done &= ~BIT(inst->id); > > + wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST, cmd_done); > > + val = BIT(INT_WAVE5_DEC_PIC); > > + kfifo_in(&inst->irq_status, &val, sizeof(int)); > > + } > > + } > > +} > > + > > +static irqreturn_t wave5_vpu_irq(int irq, void *dev_id) > > +{ > > + struct vpu_device *dev = dev_id; > > + > > + if (wave5_vdi_readl(dev, W5_VPU_VPU_INT_STS)) { > > + struct vpu_instance *inst; > > + u32 irq_status = wave5_vdi_readl(dev, W5_VPU_VINT_REASON); > > + > > + list_for_each_entry(inst, &dev->instances, list) { > > + wave5_vpu_get_interrupt_for_inst(inst, irq_status); > > + } > > + > > + wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_status); > > + wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1); > > + > > + return IRQ_WAKE_THREAD; > > + } > > + > > + return IRQ_HANDLED; > > +} > > + > > +static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id) > > +{ > > + struct vpu_device *dev = dev_id; > > + struct vpu_instance *inst; > > + int irq_status, ret; > > + u32 val; > > + > > + list_for_each_entry(inst, &dev->instances, list) { > > + while (kfifo_len(&inst->irq_status)) { > > + struct vpu_instance *curr; > > + > > + curr = v4l2_m2m_get_curr_priv(inst->v4l2_m2m_dev); > > + if (curr) { > > + inst->ops->finish_process(inst); > > + } else { > > + ret = kfifo_out(&inst->irq_status, &irq_status, sizeof(int)); > > + if (!ret) > > + break; > > + > > + val = wave5_vdi_readl(dev, W5_VPU_VINT_REASON_USR); > > + val &= ~irq_status; > > + wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_USR, val); > > + complete(&inst->irq_done); > > + } > > + } > > + } > > + > > + return IRQ_HANDLED; > > +} > > + > > +static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name) > > +{ > > + const struct firmware *fw; > > + int ret; > > + u32 revision; > > + unsigned int product_id; > > + > > + ret = request_firmware(&fw, fw_name, dev); > > + if (ret) { > > + dev_err(dev, "request_firmware, fail: %d\n", ret); > > + return ret; > > + } > > + > > + ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw->data, fw->size); > > + if (ret) { > > + dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret); > > + goto release_fw; > > + } > > + release_firmware(fw); > > + > > + ret = wave5_vpu_get_version_info(dev, &revision, &product_id); > > + if (ret) { > > + dev_err(dev, "vpu_get_version_info fail: %d\n", ret); > > + goto err_without_release; > > + } > > + > > + dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n", > > + __func__, product_id, revision); > > + > > + return 0; > > + > > +release_fw: > > + release_firmware(fw); > > +err_without_release: > > + return ret; > > +} > > + > > +static int wave5_vpu_probe(struct platform_device *pdev) > > +{ > > + int ret; > > + struct vpu_device *dev; > > + struct device_node *np; > > + const struct wave5_match_data *match_data; > > + struct resource sram; > > + > > + match_data = device_get_match_data(&pdev->dev); > > + if (!match_data) { > > + dev_err(&pdev->dev, "missing device match data\n"); > > + return -EINVAL; > > + } > > + > > + /* physical addresses limited to 32 bits */ > > + dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); > > + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); > > + > > + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); > > + if (!dev) > > + return -ENOMEM; > > + > > + dev->vdb_register = devm_platform_ioremap_resource(pdev, 0); > > + if (IS_ERR(dev->vdb_register)) > > + return PTR_ERR(dev->vdb_register); > > + ida_init(&dev->inst_ida); > > + > > + mutex_init(&dev->dev_lock); > > + mutex_init(&dev->hw_lock); > > + dev_set_drvdata(&pdev->dev, dev); > > + dev->dev = &pdev->dev; > > + > > + ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks); > > + > > + /* continue without clock, assume externally managed */ > > + if (ret < 0) { > > + dev_warn(&pdev->dev, "Getting clocks, fail: %d\n", ret); > > + ret = 0; > > + } > > + dev->num_clks = ret; > > + > > + ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks); > > + if (ret) { > > + dev_err(&pdev->dev, "Enabling clocks, fail: %d\n", ret); > > + return ret; > > + } > > + > > + np = of_parse_phandle(pdev->dev.of_node, "sram", 0); > > + if (!np) { > > + dev_warn(&pdev->dev, "sram node not found\n"); > > + } else { > > + ret = of_address_to_resource(np, 0, &sram); > > + if (ret) { > > + dev_err(&pdev->dev, "sram resource not available\n"); > > + goto err_put_node; > > + } > > + dev->sram_buf.daddr = sram.start; > > + dev->sram_buf.size = resource_size(&sram); > > + dev_dbg(&pdev->dev, "%s: sram daddr: %pad, size: 0x%lx\n", > > + __func__, &dev->sram_buf.daddr, dev->sram_buf.size); > > + } > > + > > + dev->product_code = wave5_vdi_readl(dev, VPU_PRODUCT_CODE_REGISTER); > > + ret = wave5_vdi_init(&pdev->dev); > > + if (ret < 0) { > > + dev_err(&pdev->dev, "wave5_vdi_init, fail: %d\n", ret); > > + goto err_clk_dis; > > + } > > + dev->product = wave5_vpu_get_product_id(dev); > > + > > + INIT_LIST_HEAD(&dev->instances); > > + ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); > > + if (ret) { > > + dev_err(&pdev->dev, "v4l2_device_register, fail: %d\n", ret); > > + goto err_vdi_release; > > + } > > + > > + if (match_data->flags & WAVE5_IS_DEC) { > > + ret = wave5_vpu_dec_register_device(dev); > > + if (ret) { > > + dev_err(&pdev->dev, "wave5_vpu_dec_register_device, fail: %d\n", ret); > > + goto err_v4l2_unregister; > > + } > > + } > > + if (match_data->flags & WAVE5_IS_ENC) { > > + ret = wave5_vpu_enc_register_device(dev); > > + if (ret) { > > + dev_err(&pdev->dev, "wave5_vpu_enc_register_device, fail: %d\n", ret); > > + goto err_dec_unreg; > > + } > > + } > > + > > + dev->irq = platform_get_irq(pdev, 0); > > + if (dev->irq < 0) { > > + dev_err(&pdev->dev, "failed to get irq resource\n"); > > + ret = -ENXIO; > > + goto err_enc_unreg; > > + } > > + > > + ret = devm_request_threaded_irq(&pdev->dev, dev->irq, wave5_vpu_irq, > > + wave5_vpu_irq_thread, 0, "vpu_irq", dev); > > + if (ret) { > > + dev_err(&pdev->dev, "Register interrupt handler, fail: %d\n", ret); > > + goto err_enc_unreg; > > + } > > + > > + ret = wave5_vpu_load_firmware(&pdev->dev, match_data->fw_name); > > + if (ret) { > > + dev_err(&pdev->dev, "wave5_vpu_load_firmware, fail: %d\n", ret); > > + goto err_enc_unreg; > > + } > > + > > + dev_dbg(&pdev->dev, "Added wave5 driver with caps: %s %s and product code: 0x%x\n", > > + (match_data->flags & WAVE5_IS_ENC) ? "'ENCODE'" : "", > > + (match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : "", > > + dev->product_code); > > + return 0; > > + > > +err_enc_unreg: > > + if (match_data->flags & WAVE5_IS_ENC) > > + wave5_vpu_enc_unregister_device(dev); > > +err_dec_unreg: > > + if (match_data->flags & WAVE5_IS_DEC) > > + wave5_vpu_dec_unregister_device(dev); > > +err_v4l2_unregister: > > + v4l2_device_unregister(&dev->v4l2_dev); > > +err_vdi_release: > > + wave5_vdi_release(&pdev->dev); > > +err_clk_dis: > > + clk_bulk_disable_unprepare(dev->num_clks, dev->clks); > > +err_put_node: > > + of_node_put(np); > > + > > + return ret; > > +} > > + > > +static int wave5_vpu_remove(struct platform_device *pdev) > > +{ > > + struct vpu_device *dev = dev_get_drvdata(&pdev->dev); > > + > > + clk_bulk_disable_unprepare(dev->num_clks, dev->clks); > > + wave5_vpu_enc_unregister_device(dev); > > + wave5_vpu_dec_unregister_device(dev); > > + v4l2_device_unregister(&dev->v4l2_dev); > > + wave5_vdi_release(&pdev->dev); > > + ida_destroy(&dev->inst_ida); > > + > > + return 0; > > +} > > + > > +static const struct wave5_match_data wave511_data = { > > + .flags = WAVE5_IS_DEC, > > + .fw_name = "wave511_dec_fw.bin", > > +}; > > + > > +static const struct wave5_match_data wave521_data = { > > + .flags = WAVE5_IS_ENC, > > + .fw_name = "wave521_enc_fw.bin", > > +}; > > + > > +static const struct wave5_match_data wave521c_data = { > > + .flags = WAVE5_IS_ENC | WAVE5_IS_DEC, > > + .fw_name = "wave521c_codec_fw.bin", > > +}; > > + > > +static const struct wave5_match_data default_match_data = { > > + .flags = WAVE5_IS_ENC | WAVE5_IS_DEC, > > + .fw_name = "chagall.bin", > > +}; > > + > > +static const struct of_device_id wave5_dt_ids[] = { > > + { .compatible = "cnm,cm511-vpu", .data = &wave511_data }, > > + { .compatible = "cnm,cm517-vpu", .data = &default_match_data }, > > + { .compatible = "cnm,cm521-vpu", .data = &wave521_data }, > > + { .compatible = "cnm,cm521c-vpu", .data = &wave521c_data }, > > + { .compatible = "cnm,cm521c-dual-vpu", .data = &wave521c_data }, > > + { .compatible = "cnm,cm521e1-vpu", .data = &default_match_data }, > > + { .compatible = "cnm,cm537-vpu", .data = &default_match_data }, > > + { /* sentinel */ } > > +}; > > +MODULE_DEVICE_TABLE(of, wave5_dt_ids); > > + > > +static struct platform_driver wave5_vpu_driver = { > > + .driver = { > > + .name = VPU_PLATFORM_DEVICE_NAME, > > + .of_match_table = of_match_ptr(wave5_dt_ids), > > + }, > > + .probe = wave5_vpu_probe, > > + .remove = wave5_vpu_remove, > > +}; > > + > > +module_platform_driver(wave5_vpu_driver); > > +MODULE_DESCRIPTION("chips&media VPU V4L2 driver"); > > +MODULE_LICENSE("Dual BSD/GPL"); > > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.h b/drivers/media/platform/chips-media/wave5/wave5-vpu.h > > new file mode 100644 > > index 000000000000..7156d8c3fee4 > > --- /dev/null > > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.h > > @@ -0,0 +1,72 @@ > > +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ > > +/* > > + * Wave5 series multi-standard codec IP - basic types > > + * > > + * Copyright (C) 2021 CHIPS&MEDIA INC > > + */ > > +#ifndef __VPU_DRV_H__ > > +#define __VPU_DRV_H__ > > + > > +#include <media/v4l2-ctrls.h> > > +#include <media/v4l2-ioctl.h> > > +#include <media/v4l2-event.h> > > +#include <media/v4l2-fh.h> > > +#include <media/videobuf2-v4l2.h> > > +#include <media/videobuf2-dma-contig.h> > > +#include <media/videobuf2-vmalloc.h> > > +#include "wave5-vpuconfig.h" > > +#include "wave5-vpuapi.h" > > + > > +#define VPU_BUF_SYNC_TO_DEVICE 0 > > +#define VPU_BUF_SYNC_FROM_DEVICE 1 > > + > > +struct vpu_buffer { > > + struct v4l2_m2m_buffer v4l2_m2m_buf; > > + bool consumed; > > +}; > > + > > +enum vpu_fmt_type { > > + VPU_FMT_TYPE_CODEC = 0, > > + VPU_FMT_TYPE_RAW = 1 > > +}; > > + > > +struct vpu_format { > > + unsigned int v4l2_pix_fmt; > > + unsigned int max_width; > > + unsigned int min_width; > > + unsigned int max_height; > > + unsigned int min_height; > > +}; > > + > > +static inline struct vpu_instance *wave5_to_vpu_inst(struct v4l2_fh *vfh) > > +{ > > + return container_of(vfh, struct vpu_instance, v4l2_fh); > > +} > > + > > +static inline struct vpu_instance *wave5_ctrl_to_vpu_inst(struct v4l2_ctrl *vctrl) > > +{ > > + return container_of(vctrl->handler, struct vpu_instance, v4l2_ctrl_hdl); > > +} > > + > > +static inline struct vpu_buffer *wave5_to_vpu_buf(struct vb2_v4l2_buffer *vbuf) > > +{ > > + return container_of(vbuf, struct vpu_buffer, v4l2_m2m_buf.vb); > > +} > > + > > +int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout); > > + > > +int wave5_vpu_dec_register_device(struct vpu_device *dev); > > +void wave5_vpu_dec_unregister_device(struct vpu_device *dev); > > +int wave5_vpu_enc_register_device(struct vpu_device *dev); > > +void wave5_vpu_enc_unregister_device(struct vpu_device *dev); > > +static inline bool wave5_vpu_both_queues_are_streaming(struct vpu_instance *inst) > > +{ > > + struct vb2_queue *vq_cap = > > + v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); > > + struct vb2_queue *vq_out = > > + v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); > > + > > + return vb2_is_streaming(vq_cap) && vb2_is_streaming(vq_out); > > +} > > + > > +#endif > > Regards, > > Hans ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v11 3/6] media: chips-media: wave5: Add the v4l2 layer 2022-12-07 12:13 ` [PATCH v11 3/6] media: chips-media: wave5: Add the v4l2 layer Sebastian Fricke 2022-12-12 14:19 ` Hans Verkuil @ 2023-04-26 14:44 ` Nicolas Dufresne 1 sibling, 0 replies; 22+ messages in thread From: Nicolas Dufresne @ 2023-04-26 14:44 UTC (permalink / raw) To: Sebastian Fricke, linux-media, Mauro Carvalho Chehab, Nas Chung, Robert Beckett Cc: kernel, hverkuil-cisco, linux-kernel Hi, Le mercredi 07 décembre 2022 à 13:13 +0100, Sebastian Fricke a écrit : > From: Nas Chung <nas.chung@chipsnmedia.com> > > Add the decoder and encoder implementing the v4l2 > API. This patch also adds the Makefile and the VIDEO_WAVE_VPU config > > Signed-off-by: Robert Beckett <bob.beckett@collabora.com> > Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> > Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> > Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com> > --- > drivers/media/platform/chips-media/Kconfig | 1 + > drivers/media/platform/chips-media/Makefile | 1 + > .../media/platform/chips-media/wave5/Kconfig | 12 + > .../media/platform/chips-media/wave5/Makefile | 10 + > .../platform/chips-media/wave5/wave5-helper.c | 175 ++ > .../platform/chips-media/wave5/wave5-helper.h | 28 + > .../chips-media/wave5/wave5-vpu-dec.c | 1429 ++++++++++++++ > .../chips-media/wave5/wave5-vpu-enc.c | 1746 +++++++++++++++++ > .../platform/chips-media/wave5/wave5-vpu.c | 362 ++++ > .../platform/chips-media/wave5/wave5-vpu.h | 72 + > 10 files changed, 3836 insertions(+) > create mode 100644 drivers/media/platform/chips-media/wave5/Kconfig > create mode 100644 drivers/media/platform/chips-media/wave5/Makefile > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-helper.c > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-helper.h > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu.c > create mode 100644 drivers/media/platform/chips-media/wave5/wave5-vpu.h > > diff --git a/drivers/media/platform/chips-media/Kconfig b/drivers/media/platform/chips-media/Kconfig > index f87a0d693df7..ad350eb6b1fc 100644 > --- a/drivers/media/platform/chips-media/Kconfig > +++ b/drivers/media/platform/chips-media/Kconfig > @@ -3,3 +3,4 @@ > comment "Chips&Media media platform drivers" > > source "drivers/media/platform/chips-media/coda/Kconfig" > +source "drivers/media/platform/chips-media/wave5/Kconfig" > diff --git a/drivers/media/platform/chips-media/Makefile b/drivers/media/platform/chips-media/Makefile > index 5ee693f651c1..6b5d99de8b54 100644 > --- a/drivers/media/platform/chips-media/Makefile > +++ b/drivers/media/platform/chips-media/Makefile > @@ -1,3 +1,4 @@ > # SPDX-License-Identifier: GPL-2.0-only > > obj-y += coda/ > +obj-y += wave5/ > diff --git a/drivers/media/platform/chips-media/wave5/Kconfig b/drivers/media/platform/chips-media/wave5/Kconfig > new file mode 100644 > index 000000000000..a3b949356cd5 > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/Kconfig > @@ -0,0 +1,12 @@ > +# SPDX-License-Identifier: GPL-2.0 > +config VIDEO_WAVE_VPU > + tristate "Chips&Media Wave Codec Driver" > + depends on VIDEO_DEV > + select VIDEOBUF2_DMA_CONTIG > + select VIDEOBUF2_VMALLOC > + select V4L2_MEM2MEM_DEV > + help > + Chips&Media stateful encoder and decoder driver. > + The driver supports HEVC and H264 formats. > + To compile this driver as modules, choose M here: the > + modules will be called wave5. > diff --git a/drivers/media/platform/chips-media/wave5/Makefile b/drivers/media/platform/chips-media/wave5/Makefile > new file mode 100644 > index 000000000000..3d738a03bd8e > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/Makefile > @@ -0,0 +1,10 @@ > +# SPDX-License-Identifier: GPL-2.0 > + > +obj-$(CONFIG_VIDEO_WAVE_VPU) += wave5.o > +wave5-objs += wave5-hw.o \ > + wave5-vpuapi.o \ > + wave5-vdi.o \ > + wave5-vpu-dec.o \ > + wave5-vpu.o \ > + wave5-vpu-enc.o \ > + wave5-helper.o > diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.c b/drivers/media/platform/chips-media/wave5/wave5-helper.c > new file mode 100644 > index 000000000000..2851f3f0b580 > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.c > @@ -0,0 +1,175 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > +/* > + * Wave5 series multi-standard codec IP - decoder interface > + * > + * Copyright (C) 2021 CHIPS&MEDIA INC > + */ > + > +#include "wave5-helper.h" > + > +void wave5_cleanup_instance(struct vpu_instance *inst) > +{ > + int i; > + > + for (i = 0; i < inst->dst_buf_count; i++) > + wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[i]); > + > + wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf); > + v4l2_ctrl_handler_free(&inst->v4l2_ctrl_hdl); > + if (inst->v4l2_m2m_dev != NULL) > + v4l2_m2m_release(inst->v4l2_m2m_dev); > + if (inst->v4l2_fh.vdev != NULL) { > + v4l2_fh_del(&inst->v4l2_fh); > + v4l2_fh_exit(&inst->v4l2_fh); > + } > + list_del_init(&inst->list); > + kfifo_free(&inst->irq_status); > + ida_free(&inst->dev->inst_ida, inst->id); > + kfree(inst); > +} > + > +int wave5_vpu_release_device(struct file *filp, > + int (*close_func)(struct vpu_instance *inst, u32 *fail_res), > + char *name) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(filp->private_data); > + > + v4l2_m2m_ctx_release(inst->v4l2_fh.m2m_ctx); > + if (inst->state != VPU_INST_STATE_NONE) { > + u32 fail_res; > + int retry_count = 10; > + int ret; > + > + do { > + fail_res = 0; > + ret = close_func(inst, &fail_res); > + if (ret && ret != -EIO) > + break; > + if (fail_res != WAVE5_SYSERR_VPU_STILL_RUNNING) > + break; > + if (!wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT)) > + break; > + } while (--retry_count); > + > + if (fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING) { > + dev_err(inst->dev->dev, "%s close failed, device is still running\n", > + name); > + return -EBUSY; > + } > + if (ret && ret != -EIO) { > + dev_err(inst->dev->dev, "%s close, fail: %d\n", name, ret); > + return ret; > + } > + } > + > + wave5_cleanup_instance(inst); > + > + return 0; > +} > + > +int wave5_vpu_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq, > + const struct vb2_ops *ops) > +{ > + struct vpu_instance *inst = priv; > + int ret; > + > + src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; > + src_vq->io_modes = VB2_MMAP | VB2_DMABUF; > + src_vq->mem_ops = &vb2_dma_contig_memops; > + src_vq->ops = ops; > + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; > + src_vq->buf_struct_size = sizeof(struct vpu_buffer); > + src_vq->drv_priv = inst; > + src_vq->lock = &inst->dev->dev_lock; > + src_vq->dev = inst->dev->v4l2_dev.dev; > + ret = vb2_queue_init(src_vq); > + if (ret) > + return ret; > + > + dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; > + dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; > + dst_vq->mem_ops = &vb2_dma_contig_memops; > + dst_vq->ops = ops; > + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; > + dst_vq->buf_struct_size = sizeof(struct vpu_buffer); > + dst_vq->drv_priv = inst; > + dst_vq->lock = &inst->dev->dev_lock; > + dst_vq->dev = inst->dev->v4l2_dev.dev; > + ret = vb2_queue_init(dst_vq); > + if (ret) > + return ret; > + > + return 0; > +} > + > +int wave5_vpu_subscribe_event(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + bool is_decoder = inst->type == VPU_INST_TYPE_DEC; > + > + dev_dbg(inst->dev->dev, "%s: [%s] type: %u id: %u | flags: %u\n", __func__, > + is_decoder ? "decoder" : "encoder", sub->type, sub->id, sub->flags); > + > + switch (sub->type) { > + case V4L2_EVENT_EOS: > + return v4l2_event_subscribe(fh, sub, 0, NULL); > + case V4L2_EVENT_SOURCE_CHANGE: > + if (is_decoder) > + return v4l2_src_change_event_subscribe(fh, sub); > + return -EINVAL; > + case V4L2_EVENT_CTRL: > + return v4l2_ctrl_subscribe_event(fh, sub); Maybe a comment for which control this is added for. I think it is for MIN_BUFFER_FOR_CAPTURE, am I right ? > + default: > + return -EINVAL; > + } > +} > + > +int wave5_vpu_g_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i; > + > + f->fmt.pix_mp.width = inst->src_fmt.width; > + f->fmt.pix_mp.height = inst->src_fmt.height; > + f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; > + f->fmt.pix_mp.field = inst->src_fmt.field; > + f->fmt.pix_mp.flags = inst->src_fmt.flags; > + f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; > + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { > + f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->src_fmt.plane_fmt[i].bytesperline; > + f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->src_fmt.plane_fmt[i].sizeimage; > + } > + > + f->fmt.pix_mp.colorspace = inst->colorspace; > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > + f->fmt.pix_mp.quantization = inst->quantization; > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > + > + return 0; > +} > + > +const struct vpu_format *wave5_find_vpu_fmt(unsigned int v4l2_pix_fmt, > + const struct vpu_format fmt_list[MAX_FMTS]) > +{ > + unsigned int index; > + > + for (index = 0; index < MAX_FMTS; index++) { > + if (fmt_list[index].v4l2_pix_fmt == v4l2_pix_fmt) > + return &fmt_list[index]; > + } > + > + return NULL; > +} > + > +const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx, > + const struct vpu_format fmt_list[MAX_FMTS]) > +{ > + if (idx >= MAX_FMTS) > + return NULL; > + > + if (!fmt_list[idx].v4l2_pix_fmt) > + return NULL; > + > + return &fmt_list[idx]; > +} > diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.h b/drivers/media/platform/chips-media/wave5/wave5-helper.h > new file mode 100644 > index 000000000000..d586d624275e > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ > +/* > + * Wave5 series multi-standard codec IP - basic types > + * > + * Copyright (C) 2021 CHIPS&MEDIA INC > + */ > + > +#ifndef __WAVE_HELPER_H__ > +#define __WAVE_HELPER_H__ > + > +#include "wave5-vpu.h" > + > +#define FMT_TYPES 2 > +#define MAX_FMTS 6 > + > +void wave5_cleanup_instance(struct vpu_instance *inst); > +int wave5_vpu_release_device(struct file *filp, > + int (*close_func)(struct vpu_instance *inst, u32 *fail_res), > + char *name); > +int wave5_vpu_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq, > + const struct vb2_ops *ops); > +int wave5_vpu_subscribe_event(struct v4l2_fh *fh, const struct v4l2_event_subscription *sub); > +int wave5_vpu_g_fmt_out(struct file *file, void *fh, struct v4l2_format *f); > +const struct vpu_format *wave5_find_vpu_fmt(unsigned int v4l2_pix_fmt, > + const struct vpu_format fmt_list[MAX_FMTS]); > +const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx, > + const struct vpu_format fmt_list[MAX_FMTS]); > +#endif > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c > new file mode 100644 > index 000000000000..f32118d59fb8 > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c > @@ -0,0 +1,1429 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > +/* > + * Wave5 series multi-standard codec IP - decoder interface > + * > + * Copyright (C) 2021 CHIPS&MEDIA INC > + */ > + > +#include "wave5-helper.h" > + > +#define VPU_DEC_DEV_NAME "C&M Wave5 VPU decoder" > +#define VPU_DEC_DRV_NAME "wave5-dec" > +#define V4L2_CID_VPU_THUMBNAIL_MODE (V4L2_CID_USER_BASE + 0x1001) Hidden controls can only be assumed to be untested, remove or fix. Are you sure this isn't the same as V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE used by other decoders ? > + > +static const struct vpu_format dec_fmt_list[FMT_TYPES][MAX_FMTS] = { > + [VPU_FMT_TYPE_CODEC] = { > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_HEVC, > + .max_width = 8192, > + .min_width = 8, > + .max_height = 4320, > + .min_height = 8, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_H264, > + .max_width = 8192, > + .min_width = 32, > + .max_height = 4320, > + .min_height = 32, nit: Applications driving stateful decoder don't do deep parsing. The application typically is only aware of the display width/height as exposed by containers, and so the OUTPUT queue (or H264 format) will be configured based on this information. The driver should not fail if the coded width/height match the requirement, e.g 32x32 coded, with 5x5 display. Support for smaller resolutions is commonly broken in most decoders due to this confusion. > + }, > + }, > + [VPU_FMT_TYPE_RAW] = { > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420, > + .max_width = 8192, > + .min_width = 8, > + .max_height = 4320, > + .min_height = 8, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV12, > + .max_width = 8192, > + .min_width = 8, > + .max_height = 4320, > + .min_height = 8, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV21, > + .max_width = 8192, > + .min_width = 8, > + .max_height = 4320, > + .min_height = 8, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M, > + .max_width = 8192, > + .min_width = 8, > + .max_height = 4320, > + .min_height = 8, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV12M, > + .max_width = 8192, > + .min_width = 8, > + .max_height = 4320, > + .min_height = 8, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, > + .max_width = 8192, > + .min_width = 8, > + .max_height = 4320, > + .min_height = 8, > + }, As there is a per-codec minimum, and no secondary buffers, the min_width/height will have to be adjusted accordingly. I haven't reviewed that part of the code yet, this is my expectation. > + } > +}; > + > +static enum wave_std wave5_to_vpu_codstd(unsigned int v4l2_pix_fmt) > +{ > + switch (v4l2_pix_fmt) { > + case V4L2_PIX_FMT_H264: > + return W_AVC_DEC; > + case V4L2_PIX_FMT_HEVC: > + return W_HEVC_DEC; > + default: > + return STD_UNKNOWN; > + } Any reason this is not enclosed in struct vpu_format ? > +} > + > +static void wave5_handle_bitstream_buffer(struct vpu_instance *inst) > +{ > + struct v4l2_m2m_buffer *buf, *n; > + int ret; > + > + v4l2_m2m_for_each_src_buf_safe(inst->v4l2_fh.m2m_ctx, buf, n) { > + struct vb2_v4l2_buffer *vbuf = &buf->vb; > + struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); > + size_t src_size = vb2_get_plane_payload(&vbuf->vb2_buf, 0); > + void *src_buf = vb2_plane_vaddr(&vbuf->vb2_buf, 0); > + dma_addr_t rd_ptr = 0; > + dma_addr_t wr_ptr = 0; > + size_t remain_size = 0; > + size_t offset; > + > + if (vpu_buf->consumed) { I think consumed boolean is misleading. We should instead called this copied, or committed. This is will highlight the defect that in order to throttle (to avoid over committing to the ring buffer), we only mark these done when the HW have completed an operation. I believe the appropriate logic is that the src buffer that has been copied into the ring buffer, should only be marked done when they actually have been consumed (with the real meaning). A consumed src buffer is a buffer which the data is no longer held in the ring buffer. This is verified using the ring buffer read pointer. > + dev_dbg(inst->dev->dev, "already consumed src buf (%u)\n", > + vbuf->vb2_buf.index); > + continue; > + } > + > + if (!src_buf) { > + dev_dbg(inst->dev->dev, > + "%s: Acquiring kernel pointer to src buf (%u), fail\n", > + __func__, vbuf->vb2_buf.index); > + break; > + } > + > + ret = wave5_vpu_dec_get_bitstream_buffer(inst, &rd_ptr, &wr_ptr, &remain_size); > + if (ret) { > + dev_err(inst->dev->dev, "Getting the bitstream buffer, fail: %d\n", > + ret); > + return; > + } > + > + if (remain_size < src_size) { > + dev_dbg(inst->dev->dev, > + "%s: remaining size: %zu < source size: %zu for src buf (%u)\n", > + __func__, remain_size, src_size, vbuf->vb2_buf.index); > + break; > + } > + > + offset = wr_ptr - inst->bitstream_vbuf.daddr; > + if (wr_ptr + src_size > inst->bitstream_vbuf.daddr + inst->bitstream_vbuf.size) { > + size_t size; > + > + size = inst->bitstream_vbuf.daddr + inst->bitstream_vbuf.size - wr_ptr; > + ret = wave5_vdi_write_memory(inst->dev, &inst->bitstream_vbuf, offset, > + (u8 *)src_buf, size, VDI_128BIT_LITTLE_ENDIAN); > + if (ret < 0) { > + dev_dbg(inst->dev->dev, > + "%s: 1/2 write src buf (%u) into bitstream buf, fail: %d\n", > + __func__, vbuf->vb2_buf.index, ret); > + break; > + } > + ret = wave5_vdi_write_memory(inst->dev, &inst->bitstream_vbuf, 0, > + (u8 *)src_buf + size, src_size - size, > + VDI_128BIT_LITTLE_ENDIAN); > + if (ret < 0) { > + dev_dbg(inst->dev->dev, > + "%s: 2/2 write src buf (%u) into bitstream buf, fail: %d\n", > + __func__, vbuf->vb2_buf.index, ret); > + break; > + } > + } else { > + ret = wave5_vdi_write_memory(inst->dev, &inst->bitstream_vbuf, offset, > + (u8 *)src_buf, src_size, > + VDI_128BIT_LITTLE_ENDIAN); > + if (ret < 0) { > + dev_dbg(inst->dev->dev, > + "%s: write src buf (%u) into bitstream buf, fail: %d", > + __func__, vbuf->vb2_buf.index, ret); > + break; > + } > + } > + > + ret = wave5_vpu_dec_update_bitstream_buffer(inst, src_size); While copying to the ring buffer here is a good optimization, I believe this part have no place here. This should be serialized into device_run, along with all the state management. We found that activating the HW in various places creates hard to fix races, and complexify the driver state machine handling. A small improvement to the M2M framework to make this happen, we will make the required modification. > + if (ret) { > + dev_dbg(inst->dev->dev, > + "vpu_dec_update_bitstream_buffer fail: %d for src buf (%u)\n", > + ret, vbuf->vb2_buf.index); > + break; > + } > + > + vpu_buf->consumed = true; > + } > +} > + > +static void wave5_handle_src_buffer(struct vpu_instance *inst) > +{ > + struct vb2_v4l2_buffer *src_buf; > + > + src_buf = v4l2_m2m_next_src_buf(inst->v4l2_fh.m2m_ctx); > + if (src_buf) { > + struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(src_buf); > + > + if (vpu_buf->consumed) { > + dev_dbg(inst->dev->dev, "%s: already consumed buffer\n", __func__); > + src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); > + inst->timestamp = src_buf->vb2_buf.timestamp; > + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); > + } > + } This is missing a colleralation with the ringbuffer read pointer position as explained earlier. > +} > + > +static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width, > + unsigned int height) > +{ > + switch (pix_mp->pixelformat) { > + case V4L2_PIX_FMT_YUV420: > + case V4L2_PIX_FMT_NV12: > + case V4L2_PIX_FMT_NV21: > + pix_mp->width = round_up(width, 32); > + pix_mp->height = round_up(height, 16); This is a hidden step, should be part of the raw format frame enumeration. > + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); > + pix_mp->plane_fmt[0].sizeimage = width * height * 3 / 2; > + break; > + case V4L2_PIX_FMT_YUV420M: > + pix_mp->width = round_up(width, 32); > + pix_mp->height = round_up(height, 16); > + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); > + pix_mp->plane_fmt[0].sizeimage = width * height; > + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; > + pix_mp->plane_fmt[1].sizeimage = width * height / 4; > + pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; > + pix_mp->plane_fmt[2].sizeimage = width * height / 4; > + break; > + case V4L2_PIX_FMT_NV12M: > + case V4L2_PIX_FMT_NV21M: > + pix_mp->width = round_up(width, 32); > + pix_mp->height = round_up(height, 16); > + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); > + pix_mp->plane_fmt[0].sizeimage = width * height; > + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); > + pix_mp->plane_fmt[1].sizeimage = width * height / 2; > + break; > + default: > + pix_mp->width = width; > + pix_mp->height = height; > + pix_mp->plane_fmt[0].bytesperline = 0; > + pix_mp->plane_fmt[0].sizeimage = width * height; > + break; All this is duplicated from v4l2-common.c. Please use the helpers instead, it will ease the proper implementation of framesize enumeration and avoid possibly getting wrong stride calculation errors. Also, is it true that this driver strictly needs a 1:1 match of the stride or can it support anything that fits the step ? > + } > +} > + > +static void wave5_vpu_dec_start_decode(struct vpu_instance *inst) > +{ > + struct dec_param pic_param; > + int ret; > + u32 fail_res = 0; > + > + memset(&pic_param, 0, sizeof(struct dec_param)); > + > + if (inst->state == VPU_INST_STATE_INIT_SEQ) { > + u32 non_linear_num = inst->dst_buf_count; > + u32 linear_num = inst->dst_buf_count; > + u32 stride = inst->dst_fmt.width; > + > + ret = wave5_vpu_dec_register_frame_buffer_ex(inst, non_linear_num, linear_num, > + stride, inst->dst_fmt.height, > + COMPRESSED_FRAME_MAP); This is what I believe is incompatible with CREATE_BUFS. This is one time frame buffer registration, meaning the HW will never be aware of any newly creates buffers. > + if (ret) > + dev_dbg(inst->dev->dev, "%s: vpu_dec_register_frame_buffer_ex fail: %d", > + __func__, ret); > + } > + > + ret = wave5_vpu_dec_start_one_frame(inst, &pic_param, &fail_res); > + if (ret && fail_res != WAVE5_SYSERR_QUEUEING_FAIL) { > + struct vb2_v4l2_buffer *src_buf; > + > + src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); > + inst->state = VPU_INST_STATE_STOP; > + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); > + } The fact you start streaming should be enough as a condition for device_run to be called. You should not have to trigger the HW outside of a job. > +} > + > +static void wave5_vpu_dec_stop_decode(struct vpu_instance *inst) This can easily be confused with the CMD_STOP operation, while its the implementation of the M2M abort function. Would be nice to rename accordingly. > +{ > + unsigned int i; > + int ret; > + > + inst->state = VPU_INST_STATE_STOP; > + > + ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0); After reading through, this special call is more of less some sort of EOS signal to let the HW drain. Please wrap this call into something with a name that will make this action readable and obvious. I think the fact that you have to drain the HW on abort should gain a comment, it does not seems like the most efficient way to abort a decode operation. By adding a comment, can you emphase that this is the only reliable method with this firmware ? > + if (ret) { > + dev_warn(inst->dev->dev, > + "Setting EOS for the bitstream, fail: %d\n", ret); > + } > + > + for (i = 0; i < inst->dst_buf_count; i++) { > + ret = wave5_vpu_dec_clr_disp_flag(inst, i); > + if (ret) { > + dev_dbg(inst->dev->dev, > + "%s: Clearing the display flag of buffer index: %u, fail: %d\n", > + __func__, i, ret); > + } > + } > + > + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); > +} > + > +static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst) > +{ > + struct dec_output_info dec_output_info; > + int ret; > + u32 irq_status; > + > + if (kfifo_out(&inst->irq_status, &irq_status, sizeof(int))) > + wave5_vpu_clear_interrupt_ex(inst, irq_status); In general, I notice that everything this is called, the HW is going idle. The jobs lifetime should match the time the HW is active. For this reason, I would always finish the job here. This also avoid having to finish jobs outside of abort and device_run calls, which is more robust. > + > + ret = wave5_vpu_dec_get_output_info(inst, &dec_output_info); > + if (ret) { > + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); > + return; > + } > + if (dec_output_info.index_frame_decoded == DECODED_IDX_FLAG_NO_FB && > + dec_output_info.index_frame_display == DISPLAY_IDX_FLAG_NO_FB) { > + dev_dbg(inst->dev->dev, "%s: no more frame buffer\n", __func__); > + } else { > + wave5_handle_src_buffer(inst); > + > + if (dec_output_info.index_frame_display >= 0) { > + struct vb2_v4l2_buffer *dst_buf = > + v4l2_m2m_dst_buf_remove_by_idx(inst->v4l2_fh.m2m_ctx, > + dec_output_info.index_frame_display); > + int stride = dec_output_info.disp_frame.stride; > + int height = dec_output_info.disp_pic_height - > + dec_output_info.rc_display.bottom; > + > + if (inst->dst_fmt.num_planes == 1) { > + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, > + (stride * height * 3 / 2)); > + } else if (inst->dst_fmt.num_planes == 2) { > + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, > + (stride * height)); > + vb2_set_plane_payload(&dst_buf->vb2_buf, 1, > + ((stride / 2) * height)); > + } else if (inst->dst_fmt.num_planes == 3) { > + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, > + (stride * height)); > + vb2_set_plane_payload(&dst_buf->vb2_buf, 1, > + ((stride / 2) * (height / 2))); > + vb2_set_plane_payload(&dst_buf->vb2_buf, 2, > + ((stride / 2) * (height / 2))); > + } Here it seems like the stride may not match the one negotiated, which would be quite dramatic if that was true. Please validate the stride according to the one negotiated with the application and simply use the size image you already calculated earlier. > + > + dst_buf->vb2_buf.timestamp = inst->timestamp; > + dst_buf->field = V4L2_FIELD_NONE; No interlaced support, is that a TODO, or just not supported by the HW ? I would assume the first really, in which case it would be nice to add fixmes or any kind of comment anywhere interlacing is ignored. > + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); > + > + dev_dbg(inst->dev->dev, "%s: frame_cycle %8u\n", > + __func__, dec_output_info.frame_cycle); This is even more strange, since we emit a buffer to the user, but don't finish a job ... > + } else if (dec_output_info.index_frame_display == DISPLAY_IDX_FLAG_SEQ_END && > + !inst->eos) { > + static const struct v4l2_event vpu_event_eos = { > + .type = V4L2_EVENT_EOS > + }; > + struct vb2_v4l2_buffer *dst_buf = > + v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx); > + > + if (!dst_buf) > + return; > + > + if (inst->dst_fmt.num_planes == 1) { > + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, > + vb2_plane_size(&dst_buf->vb2_buf, 0)); > + } else if (inst->dst_fmt.num_planes == 2) { > + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, > + vb2_plane_size(&dst_buf->vb2_buf, 0)); > + vb2_set_plane_payload(&dst_buf->vb2_buf, 1, > + vb2_plane_size(&dst_buf->vb2_buf, 1)); > + } else if (inst->dst_fmt.num_planes == 3) { > + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, > + vb2_plane_size(&dst_buf->vb2_buf, 0)); > + vb2_set_plane_payload(&dst_buf->vb2_buf, 1, > + vb2_plane_size(&dst_buf->vb2_buf, 1)); > + vb2_set_plane_payload(&dst_buf->vb2_buf, 2, > + vb2_plane_size(&dst_buf->vb2_buf, 2)); > + } Everything is indexed, should be a for loop. And with my comment abot, this code is just duplicate of the above. > + > + dst_buf->vb2_buf.timestamp = inst->timestamp; > + dst_buf->flags |= V4L2_BUF_FLAG_LAST; > + dst_buf->field = V4L2_FIELD_NONE; > + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); > + > + inst->eos = TRUE; > + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos); > + > + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); > + } > + } > +} > + > +static int wave5_vpu_dec_querycap(struct file *file, void *fh, struct v4l2_capability *cap) > +{ > + strscpy(cap->driver, VPU_DEC_DRV_NAME, sizeof(cap->driver)); > + strscpy(cap->card, VPU_DEC_DRV_NAME, sizeof(cap->card)); > + strscpy(cap->bus_info, "platform:" VPU_DEC_DRV_NAME, sizeof(cap->bus_info)); > + > + return 0; > +} > + > +static int wave5_vpu_dec_enum_framesizes(struct file *f, void *fh, struct v4l2_frmsizeenum *fsize) > +{ > + const struct vpu_format *vpu_fmt; > + > + if (fsize->index) > + return -EINVAL; > + > + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, dec_fmt_list[VPU_FMT_TYPE_CODEC]); > + if (!vpu_fmt) { > + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, dec_fmt_list[VPU_FMT_TYPE_RAW]); > + if (!vpu_fmt) > + return -EINVAL; > + } > + > + fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; > + fsize->stepwise.min_width = vpu_fmt->min_width; > + fsize->stepwise.max_width = vpu_fmt->max_width; > + fsize->stepwise.step_width = 1; > + fsize->stepwise.min_height = vpu_fmt->min_height; > + fsize->stepwise.max_height = vpu_fmt->max_height; > + fsize->stepwise.step_height = 1; Step of 1 for the compressed format, but you should have a proper step of the raw formats. > + > + return 0; > +} > + > +static int wave5_vpu_dec_enum_fmt_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f) > +{ > + const struct vpu_format *vpu_fmt; > + > + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, dec_fmt_list[VPU_FMT_TYPE_RAW]); > + if (!vpu_fmt) > + return -EINVAL; > + > + f->pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->flags = 0; > + > + return 0; > +} > + > +static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, > + "%s: fourcc: %u width: %u height: %u nm planes: %u colorspace: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); > + > + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) > + return -EINVAL; > + > + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_RAW]); > + if (!vpu_fmt) { > + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; > + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; > + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height); > + } else { > + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); > + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); > + const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); > + > + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->fmt.pix_mp.num_planes = info->mem_planes; > + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); > + } > + > + f->fmt.pix_mp.flags = 0; > + f->fmt.pix_mp.field = V4L2_FIELD_NONE; > + f->fmt.pix_mp.colorspace = inst->colorspace; > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > + f->fmt.pix_mp.quantization = inst->quantization; > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); > + > + return 0; > +} > + > +static int wave5_vpu_dec_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i, ret; > + > + dev_dbg(inst->dev->dev, > + "%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); > + > + ret = wave5_vpu_dec_try_fmt_cap(file, fh, f); > + if (ret) > + return ret; > + > + inst->dst_fmt.width = f->fmt.pix_mp.width; > + inst->dst_fmt.height = f->fmt.pix_mp.height; > + inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat; > + inst->dst_fmt.field = f->fmt.pix_mp.field; > + inst->dst_fmt.flags = f->fmt.pix_mp.flags; > + inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes; > + for (i = 0; i < inst->dst_fmt.num_planes; i++) { > + inst->dst_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; > + inst->dst_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; > + } > + > + if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12 || > + inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12M) { > + inst->cbcr_interleave = true; > + inst->nv21 = false; > + } else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21 || > + inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21M) { > + inst->cbcr_interleave = true; > + inst->nv21 = true; > + } else { > + inst->cbcr_interleave = false; > + inst->nv21 = false; > + } > + > + return 0; > +} > + > +static int wave5_vpu_dec_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i; > + > + f->fmt.pix_mp.width = inst->dst_fmt.width; > + f->fmt.pix_mp.height = inst->dst_fmt.height; > + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; > + f->fmt.pix_mp.field = inst->dst_fmt.field; > + f->fmt.pix_mp.flags = inst->dst_fmt.flags; > + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; > + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { > + f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->dst_fmt.plane_fmt[i].bytesperline; > + f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->dst_fmt.plane_fmt[i].sizeimage; > + } > + > + f->fmt.pix_mp.colorspace = inst->colorspace; > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > + f->fmt.pix_mp.quantization = inst->quantization; > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > + > + return 0; > +} > + > +static int wave5_vpu_dec_enum_fmt_out(struct file *file, void *fh, struct v4l2_fmtdesc *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); > + > + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, dec_fmt_list[VPU_FMT_TYPE_CODEC]); > + if (!vpu_fmt) > + return -EINVAL; > + > + f->pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->flags = 0; You implement the source change event, yet you don't advertise it with V4L2_FMT_FLAG_DYN_RESOLUTION. > + > + return 0; > + > + > +static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, > + "%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); > + > + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + return -EINVAL; > + > + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_CODEC]); > + if (!vpu_fmt) { > + f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; > + f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; > + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height); > + } else { > + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); > + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); > + > + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->fmt.pix_mp.num_planes = 1; > + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); > + } > + > + f->fmt.pix_mp.flags = 0; > + f->fmt.pix_mp.field = V4L2_FIELD_NONE; > + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); > + > + return 0; > +} > + > +static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i, ret; > + > + dev_dbg(inst->dev->dev, > + "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > + > + ret = wave5_vpu_dec_try_fmt_out(file, fh, f); > + if (ret) > + return ret; > + > + inst->src_fmt.width = f->fmt.pix_mp.width; > + inst->src_fmt.height = f->fmt.pix_mp.height; > + inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat; > + inst->src_fmt.field = f->fmt.pix_mp.field; > + inst->src_fmt.flags = f->fmt.pix_mp.flags; > + inst->src_fmt.num_planes = f->fmt.pix_mp.num_planes; > + for (i = 0; i < inst->src_fmt.num_planes; i++) { > + inst->src_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; > + inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; > + } If possible of course, we should be more flexible here to help with the fact we enable DMABuf importation. Notably by allowing larger size image, and if possible larger bytesperline (aligned of course). Note that DMABuf importation is incorrect in GStreamer, so this should be validate with another software (or gstreamer needs to be fixed). > + > + inst->colorspace = f->fmt.pix_mp.colorspace; > + inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; > + inst->hsv_enc = f->fmt.pix_mp.hsv_enc; > + inst->quantization = f->fmt.pix_mp.quantization; > + inst->xfer_func = f->fmt.pix_mp.xfer_func; > + > + wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height); > + > + return 0; > +} > + > +static int wave5_vpu_dec_g_selection(struct file *file, void *fh, struct v4l2_selection *s) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + > + dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target); > + > + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) > + return -EINVAL; > + switch (s->target) { > + case V4L2_SEL_TGT_COMPOSE_BOUNDS: > + case V4L2_SEL_TGT_COMPOSE_PADDED: > + s->r.left = 0; > + s->r.top = 0; > + s->r.width = inst->dst_fmt.width; > + s->r.height = inst->dst_fmt.height; > + break; > + case V4L2_SEL_TGT_COMPOSE: > + case V4L2_SEL_TGT_COMPOSE_DEFAULT: > + s->r.left = 0; > + s->r.top = 0; > + if (inst->state > VPU_INST_STATE_OPEN) { > + s->r.width = inst->conf_win_width; > + s->r.height = inst->conf_win_height; > + } else { > + s->r.width = inst->src_fmt.width; > + s->r.height = inst->src_fmt.height; > + } > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int wave5_vpu_dec_s_selection(struct file *file, void *fh, struct v4l2_selection *s) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + > + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) > + return -EINVAL; > + > + if (s->target != V4L2_SEL_TGT_COMPOSE) > + return -EINVAL; > + > + dev_dbg(inst->dev->dev, "V4L2_SEL_TGT_COMPOSE w: %u h: %u\n", > + s->r.width, s->r.height); > + > + s->r.left = 0; > + s->r.top = 0; > + s->r.width = inst->dst_fmt.width; > + s->r.height = inst->dst_fmt.height; I'm surprised the decoder enables application selected crops. Was this validate in any ways ? How can this work considering there is not secondary buffers ? Maybe this was copy pasted from the encoder ? > + > + return 0; > +} > + > +static int wave5_vpu_dec_decoder_cmd(struct file *file, void *fh, struct v4l2_decoder_cmd *dc) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int ret; > + > + dev_dbg(inst->dev->dev, "decoder command: %u\n", dc->cmd); > + > + ret = v4l2_m2m_ioctl_try_decoder_cmd(file, fh, dc); > + if (ret) > + return ret; > + > + if (!wave5_vpu_both_queues_are_streaming(inst)) As per the initialization sequence, application may call command stop before it received the initial source change, in this case the capture queue will not be streaming yet. As per this HW design, this should be no problem, since the HW will queue it, and process the content of the ring buffer, which will lead to source change event and application configuring the capture queue on time. > + return 0; > + > + switch (dc->cmd) { > + case V4L2_DEC_CMD_STOP: > + inst->state = VPU_INST_STATE_STOP; > + > + ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0); This should likely be moved into device_run, and v4l2_m2m_decoder_cmd (or v4l2_m2m_ioctl_encoder_cmd to your convenience) should be used instead. This ensure all job submission is done through device_run and prevent over committing. > + if (ret) { > + dev_err(inst->dev->dev, > + "Setting EOS for the bitstream, fail: %d\n", ret); > + return ret; > + } > + break; > + case V4L2_DEC_CMD_START: > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static const struct v4l2_ioctl_ops wave5_vpu_dec_ioctl_ops = { > + .vidioc_querycap = wave5_vpu_dec_querycap, > + .vidioc_enum_framesizes = wave5_vpu_dec_enum_framesizes, > + > + .vidioc_enum_fmt_vid_cap = wave5_vpu_dec_enum_fmt_cap, > + .vidioc_s_fmt_vid_cap_mplane = wave5_vpu_dec_s_fmt_cap, > + .vidioc_g_fmt_vid_cap_mplane = wave5_vpu_dec_g_fmt_cap, > + .vidioc_try_fmt_vid_cap_mplane = wave5_vpu_dec_try_fmt_cap, > + > + .vidioc_enum_fmt_vid_out = wave5_vpu_dec_enum_fmt_out, > + .vidioc_s_fmt_vid_out_mplane = wave5_vpu_dec_s_fmt_out, > + .vidioc_g_fmt_vid_out_mplane = wave5_vpu_g_fmt_out, > + .vidioc_try_fmt_vid_out_mplane = wave5_vpu_dec_try_fmt_out, > + > + .vidioc_g_selection = wave5_vpu_dec_g_selection, > + .vidioc_s_selection = wave5_vpu_dec_s_selection, > + > + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, > + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, > + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, > + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, > + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, > + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, > + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, > + .vidioc_streamon = v4l2_m2m_ioctl_streamon, > + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, > + > + .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd, > + .vidioc_decoder_cmd = wave5_vpu_dec_decoder_cmd, > + > + .vidioc_subscribe_event = wave5_vpu_subscribe_event, > + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, > +}; > + > +static int wave5_vpu_dec_s_ctrl(struct v4l2_ctrl *ctrl) > +{ > + struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl); > + > + dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n", > + __func__, ctrl->name, ctrl->val); > + > + switch (ctrl->id) { > + case V4L2_CID_VPU_THUMBNAIL_MODE: > + inst->thumbnail_mode = ctrl->val; > + break; > + case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE: > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static const struct v4l2_ctrl_ops wave5_vpu_dec_ctrl_ops = { > + .s_ctrl = wave5_vpu_dec_s_ctrl, > +}; > + > +static const struct v4l2_ctrl_config wave5_vpu_thumbnail_mode = { > + .ops = &wave5_vpu_dec_ctrl_ops, > + .id = V4L2_CID_VPU_THUMBNAIL_MODE, > + .name = "thumbnail mode", > + .type = V4L2_CTRL_TYPE_BOOLEAN, > + .def = 0, > + .min = 0, > + .max = 1, > + .step = 1, > + .flags = V4L2_CTRL_FLAG_WRITE_ONLY, > +}; > + > +static void wave5_set_default_dec_openparam(struct dec_open_param *open_param) > +{ > + open_param->bitstream_mode = BS_MODE_INTERRUPT; > + open_param->stream_endian = VPU_STREAM_ENDIAN; > + open_param->frame_endian = VPU_FRAME_ENDIAN; > +} > + > +static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, > + unsigned int *num_planes, unsigned int sizes[], > + struct device *alloc_devs[]) > +{ > + struct vpu_instance *inst = vb2_get_drv_priv(q); > + struct v4l2_pix_format_mplane inst_format = > + (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; > + unsigned int i; > + int ret; > + > + dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, > + *num_buffers, *num_planes, q->type); > + > + if (*num_planes) { > + if (inst_format.num_planes != *num_planes) > + return -EINVAL; > + > + for (i = 0; i < *num_planes; i++) { > + if (sizes[i] < inst_format.plane_fmt[i].sizeimage) > + return -EINVAL; > + } > + } else { > + *num_planes = inst_format.num_planes; > + > + if (*num_planes == 1) { > + sizes[0] = inst_format.width * inst_format.height * 3 / 2; > + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + sizes[0] = inst_format.plane_fmt[0].sizeimage; > + dev_dbg(inst->dev->dev, "%s: size[0]: %u\n", __func__, sizes[0]); > + } else if (*num_planes == 2) { > + sizes[0] = inst_format.width * inst_format.height; > + sizes[1] = inst_format.width * inst_format.height / 2; > + dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u\n", > + __func__, sizes[0], sizes[1]); > + } else if (*num_planes == 3) { > + sizes[0] = inst_format.width * inst_format.height; > + sizes[1] = inst_format.width * inst_format.height / 4; > + sizes[2] = inst_format.width * inst_format.height / 4; > + dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u | size[2]: %u\n", > + __func__, sizes[0], sizes[1], sizes[2]); > + } More duplication of v4l2-common. > + } > + > + if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { I think the following have no place in this function. This should be tied to the jobs. > + struct dec_open_param open_param; > + > + memset(&open_param, 0, sizeof(struct dec_open_param)); > + wave5_set_default_dec_openparam(&open_param); > + > + inst->bitstream_vbuf.size = ALIGN(inst->src_fmt.plane_fmt[0].sizeimage, 1024) * 4; > + ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->bitstream_vbuf); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: alloc bitstream of size %zu fail: %d\n", > + __func__, inst->bitstream_vbuf.size, ret); > + return ret; > + } > + > + inst->std = wave5_to_vpu_codstd(inst->src_fmt.pixelformat); > + if (inst->std == STD_UNKNOWN) { > + dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", > + (char *)&inst->src_fmt.pixelformat); > + ret = -EINVAL; > + goto free_bitstream_vbuf; > + } > + open_param.bitstream_buffer = inst->bitstream_vbuf.daddr; > + open_param.bitstream_buffer_size = inst->bitstream_vbuf.size; > + > + ret = wave5_vpu_dec_open(inst, &open_param); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_open, fail: %d\n", > + __func__, ret); > + goto free_bitstream_vbuf; > + } > + > + inst->state = VPU_INST_STATE_OPEN; State machine are impossible to validate when state are changed as random places. Please add a set_state function with appropriate fencing and tracing. > + > + if (inst->thumbnail_mode) > + wave5_vpu_dec_give_command(inst, ENABLE_DEC_THUMBNAIL_MODE, NULL); > + > + } else if (inst->state == VPU_INST_STATE_INIT_SEQ && > + q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { > + u32 non_linear_num; > + u32 fb_stride, fb_height; > + u32 luma_size, chroma_size; > + > + if (*num_buffers > inst->min_dst_buf_count && > + *num_buffers < WAVE5_MAX_FBS) > + inst->dst_buf_count = *num_buffers; > + > + *num_buffers = inst->dst_buf_count; > + non_linear_num = inst->dst_buf_count; > + > + for (i = 0; i < non_linear_num; i++) { > + struct frame_buffer *frame = &inst->frame_buf[i]; > + struct vpu_buf *vframe = &inst->frame_vbuf[i]; > + > + fb_stride = inst->dst_fmt.width; > + fb_height = ALIGN(inst->dst_fmt.height, 32); > + luma_size = fb_stride * fb_height; > + chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; > + > + vframe->size = luma_size + chroma_size; > + ret = wave5_vdi_allocate_dma_memory(inst->dev, vframe); > + if (ret) { > + dev_dbg(inst->dev->dev, > + "%s: Allocating FBC buf of size %zu, fail: %d\n", > + __func__, vframe->size, ret); > + return ret; > + } > + > + frame->buf_y = vframe->daddr; > + frame->buf_cb = vframe->daddr + luma_size; > + frame->buf_cr = (dma_addr_t)-1; > + frame->size = vframe->size; > + frame->width = inst->src_fmt.width; > + frame->stride = fb_stride; > + frame->map_type = COMPRESSED_FRAME_MAP; > + frame->update_fb_info = true; > + } > + } else if (inst->state == VPU_INST_STATE_STOP && > + q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { > + *num_buffers = 0; > + } > + > + return 0; > + > +free_bitstream_vbuf: > + wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf); > + return ret; > +} > + > +static int wave5_vpu_dec_start_streaming_open(struct vpu_instance *inst) > +{ > + struct dec_initial_info initial_info; > + int ret = 0; > + > + memset(&initial_info, 0, sizeof(struct dec_initial_info)); > + > + ret = wave5_vpu_dec_issue_seq_init(inst); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_issue_seq_init, fail: %d\n", > + __func__, ret); > + return ret; > + } > + > + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) > + dev_dbg(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__); > + > + ret = wave5_vpu_dec_complete_seq_init(inst, &initial_info); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: vpu_dec_complete_seq_init, fail: %d, reason: %u\n", > + __func__, ret, initial_info.seq_init_err_reason); > + } else { > + static const struct v4l2_event vpu_event_src_ch = { > + .type = V4L2_EVENT_SOURCE_CHANGE, > + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, > + }; > + struct v4l2_ctrl *ctrl; > + > + dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n", > + __func__, initial_info.pic_width, initial_info.pic_height, > + initial_info.profile, initial_info.min_frame_buffer_count); > + > + inst->state = VPU_INST_STATE_INIT_SEQ; > + inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1; > + inst->dst_buf_count = inst->min_dst_buf_count; > + > + inst->conf_win_width = initial_info.pic_width - initial_info.pic_crop_rect.right; > + inst->conf_win_height = initial_info.pic_height - initial_info.pic_crop_rect.bottom; > + > + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, > + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE); > + if (ctrl) > + v4l2_ctrl_s_ctrl(ctrl, inst->min_dst_buf_count); > + > + if (initial_info.pic_width != inst->src_fmt.width || > + initial_info.pic_height != inst->src_fmt.height) { > + wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width, > + initial_info.pic_height); > + wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width, > + initial_info.pic_height); > + } > + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch); > + > + wave5_handle_src_buffer(inst); > + } > + > + return ret; > +} > + > +static int wave5_vpu_dec_start_streaming_seek(struct vpu_instance *inst) > +{ > + struct dec_initial_info initial_info; > + struct dec_param pic_param; > + struct dec_output_info dec_output_info; > + int ret = 0; > + u32 fail_res = 0; > + > + memset(&pic_param, 0, sizeof(struct dec_param)); > + > + ret = wave5_vpu_dec_start_one_frame(inst, &pic_param, &fail_res); > + if (ret && fail_res != WAVE5_SYSERR_QUEUEING_FAIL) { > + struct vb2_v4l2_buffer *src_buf; > + > + src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); > + inst->state = VPU_INST_STATE_STOP; > + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_start_one_frame\n", __func__); > + return ret; > + } > + > + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) > + dev_dbg(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__); > + > + ret = wave5_vpu_dec_get_output_info(inst, &dec_output_info); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_get_output_info, fail: %d\n", > + __func__, ret); > + return ret; > + } > + > + if (dec_output_info.sequence_changed) { > + static const struct v4l2_event vpu_event_src_ch = { > + .type = V4L2_EVENT_SOURCE_CHANGE, > + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, > + }; Just commenting at a random spot, but testing with GStreamer 1.22, and work in progress rework showed the the resolution change mechanism are not working as specified. This needs to be reworked. > + struct v4l2_ctrl *ctrl; > + > + wave5_vpu_dec_give_command(inst, DEC_RESET_FRAMEBUF_INFO, NULL); > + wave5_vpu_dec_give_command(inst, DEC_GET_SEQ_INFO, &initial_info); > + > + dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n", > + __func__, initial_info.pic_width, initial_info.pic_height, > + initial_info.profile, initial_info.min_frame_buffer_count); > + > + inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1; > + inst->dst_buf_count = inst->min_dst_buf_count; > + > + inst->conf_win_width = initial_info.pic_width - initial_info.pic_crop_rect.right; > + inst->conf_win_height = initial_info.pic_height - initial_info.pic_crop_rect.bottom; > + > + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, > + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE); > + if (ctrl) > + v4l2_ctrl_s_ctrl(ctrl, inst->min_dst_buf_count); > + > + if (initial_info.pic_width != inst->src_fmt.width || > + initial_info.pic_height != inst->src_fmt.height) { > + wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width, > + initial_info.pic_height); > + wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width, > + initial_info.pic_height); > + } > + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch); > + > + wave5_handle_src_buffer(inst); > + } > + > + return ret; > +} > + > +static void wave5_vpu_dec_buf_queue_src(struct vb2_buffer *vb) > +{ > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); > + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); > + struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); > + > + vpu_buf->consumed = false; > + vbuf->sequence = inst->queued_src_buf_num++; > + > + if (inst->state == VPU_INST_STATE_PIC_RUN) { > + wave5_handle_bitstream_buffer(inst); > + inst->ops->start_process(inst); > + } > +} > + > +static void wave5_vpu_dec_buf_queue_dst(struct vb2_buffer *vb) > +{ > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); > + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); > + int ret; > + > + vbuf->sequence = inst->queued_dst_buf_num++; > + ret = wave5_vpu_dec_clr_disp_flag(inst, vb->index); > + if (ret) { > + dev_dbg(inst->dev->dev, > + "%s: Clearing the display flag of buffer index: %u, fail: %d\n", > + __func__, vb->index, ret); > + } > + > + if (inst->state == VPU_INST_STATE_INIT_SEQ) { > + dma_addr_t buf_addr_y = 0, buf_addr_cb = 0, buf_addr_cr = 0; > + u32 buf_size = 0; > + u32 non_linear_num = inst->dst_buf_count; > + u32 fb_stride = inst->dst_fmt.width; > + u32 luma_size = fb_stride * inst->dst_fmt.height; > + u32 chroma_size = (fb_stride / 2) * (inst->dst_fmt.height / 2); > + > + if (inst->dst_fmt.num_planes == 1) { > + buf_size = vb2_plane_size(&vbuf->vb2_buf, 0); > + buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); > + buf_addr_cb = buf_addr_y + luma_size; > + buf_addr_cr = buf_addr_cb + chroma_size; > + } else if (inst->dst_fmt.num_planes == 2) { > + buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) + > + vb2_plane_size(&vbuf->vb2_buf, 1); > + buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); > + buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1); > + buf_addr_cr = buf_addr_cb + chroma_size; > + } else if (inst->dst_fmt.num_planes == 3) { > + buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) + > + vb2_plane_size(&vbuf->vb2_buf, 1) + > + vb2_plane_size(&vbuf->vb2_buf, 2); > + buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); > + buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1); > + buf_addr_cr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 2); > + } > + inst->frame_buf[vb->index + non_linear_num].buf_y = buf_addr_y; > + inst->frame_buf[vb->index + non_linear_num].buf_cb = buf_addr_cb; > + inst->frame_buf[vb->index + non_linear_num].buf_cr = buf_addr_cr; > + inst->frame_buf[vb->index + non_linear_num].size = buf_size; > + inst->frame_buf[vb->index + non_linear_num].width = inst->src_fmt.width; > + inst->frame_buf[vb->index + non_linear_num].stride = fb_stride; > + inst->frame_buf[vb->index + non_linear_num].map_type = LINEAR_FRAME_MAP; > + inst->frame_buf[vb->index + non_linear_num].update_fb_info = true; > + } > + > + if (!vb2_is_streaming(vb->vb2_queue)) > + return; > + > + if (inst->state == VPU_INST_STATE_STOP && inst->eos == FALSE) > + inst->ops->start_process(inst); > +} > + > +static void wave5_vpu_dec_buf_queue(struct vb2_buffer *vb) > +{ > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); > + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); > + > + dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n", > + __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), > + vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); > + > + v4l2_m2m_buf_queue(inst->v4l2_fh.m2m_ctx, vbuf); > + > + if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + wave5_vpu_dec_buf_queue_src(vb); > + else if (vb->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) > + wave5_vpu_dec_buf_queue_dst(vb); > +} > + > +static int wave5_vpu_dec_start_streaming(struct vb2_queue *q, unsigned int count) > +{ > + struct vpu_instance *inst = vb2_get_drv_priv(q); > + int ret = 0; > + > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); > + > + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > + wave5_handle_bitstream_buffer(inst); > + if (inst->state == VPU_INST_STATE_OPEN) > + ret = wave5_vpu_dec_start_streaming_open(inst); > + else if (inst->state == VPU_INST_STATE_INIT_SEQ) > + ret = wave5_vpu_dec_start_streaming_seek(inst); > + > + if (ret) { > + struct vb2_v4l2_buffer *buf; > + > + while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { > + dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4d | index %4d\n", > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_QUEUED); > + } > + } > + } > + > + return ret; > +} > + > +static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q) > +{ > + struct vpu_instance *inst = vb2_get_drv_priv(q); > + struct vb2_v4l2_buffer *buf; > + bool check_cmd = TRUE; > + > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); > + > + while (check_cmd) { > + struct queue_status_info q_status; > + struct dec_output_info dec_output_info; > + > + wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status); > + > + if (q_status.instance_queue_count + q_status.report_queue_count == 0) > + break; > + > + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) > + break; > + > + if (wave5_vpu_dec_get_output_info(inst, &dec_output_info)) > + dev_dbg(inst->dev->dev, "Getting decoding results from fw, fail\n"); > + } > + > + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > + while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { > + dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4u | index %4u\n", > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); > + } > + inst->queued_src_buf_num = 0; > + } else { > + unsigned int i; > + int ret; > + dma_addr_t rd_ptr, wr_ptr; > + > + while ((buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx))) { > + u32 plane; > + > + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > + > + for (plane = 0; plane < inst->dst_fmt.num_planes; plane++) > + vb2_set_plane_payload(&buf->vb2_buf, plane, 0); > + > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); > + } > + > + for (i = 0; i < inst->dst_buf_count; i++) { > + ret = wave5_vpu_dec_set_disp_flag(inst, i); > + if (ret) { > + dev_dbg(inst->dev->dev, > + "%s: Setting display flag of buf index: %u, fail: %d\n", > + __func__, i, ret); > + } > + } > + > + ret = wave5_vpu_dec_get_bitstream_buffer(inst, &rd_ptr, &wr_ptr, NULL); > + if (ret) { > + dev_err(inst->dev->dev, > + "Getting bitstream buf, fail: %d\n", ret); > + return; > + } > + ret = wave5_vpu_dec_set_rd_ptr(inst, wr_ptr, TRUE); > + if (ret) { > + dev_err(inst->dev->dev, > + "Setting read pointer for the decoder, fail: %d\n", ret); > + return; > + } > + if (inst->eos) { > + inst->eos = FALSE; > + inst->state = VPU_INST_STATE_INIT_SEQ; > + } > + inst->queued_dst_buf_num = 0; > + } > +} > + > +static const struct vb2_ops wave5_vpu_dec_vb2_ops = { > + .queue_setup = wave5_vpu_dec_queue_setup, > + .wait_prepare = vb2_ops_wait_prepare, > + .wait_finish = vb2_ops_wait_finish, > + .buf_queue = wave5_vpu_dec_buf_queue, > + .start_streaming = wave5_vpu_dec_start_streaming, > + .stop_streaming = wave5_vpu_dec_stop_streaming, > +}; > + > +static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, > + struct v4l2_pix_format_mplane *dst_fmt) > +{ > + unsigned int dst_pix_fmt = dec_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; > + const struct v4l2_format_info *dst_fmt_info = v4l2_format_info(dst_pix_fmt); > + > + src_fmt->pixelformat = dec_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; > + src_fmt->field = V4L2_FIELD_NONE; > + src_fmt->flags = 0; > + src_fmt->num_planes = 1; > + wave5_update_pix_fmt(src_fmt, 720, 480); > + > + dst_fmt->pixelformat = dst_pix_fmt; > + dst_fmt->field = V4L2_FIELD_NONE; > + dst_fmt->flags = 0; > + dst_fmt->num_planes = dst_fmt_info->mem_planes; > + wave5_update_pix_fmt(dst_fmt, 736, 480); > +} > + > +static int wave5_vpu_dec_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) > +{ > + return wave5_vpu_queue_init(priv, src_vq, dst_vq, &wave5_vpu_dec_vb2_ops); > +} > + > +static const struct vpu_instance_ops wave5_vpu_dec_inst_ops = { > + .start_process = wave5_vpu_dec_start_decode, > + .stop_process = wave5_vpu_dec_stop_decode, > + .finish_process = wave5_vpu_dec_finish_decode, > +}; > + > +static void wave5_vpu_dec_device_run(void *priv) > +{ > + struct vpu_instance *inst = priv; > + > + inst->ops->start_process(inst); > + > + inst->state = VPU_INST_STATE_PIC_RUN; > +} > + > +static void wave5_vpu_dec_job_abort(void *priv) > +{ > + struct vpu_instance *inst = priv; > + > + inst->ops->stop_process(inst); > +} > + > +static const struct v4l2_m2m_ops wave5_vpu_dec_m2m_ops = { > + .device_run = wave5_vpu_dec_device_run, > + .job_abort = wave5_vpu_dec_job_abort, > +}; > + > +static int wave5_vpu_open_dec(struct file *filp) > +{ > + struct video_device *vdev = video_devdata(filp); > + struct vpu_device *dev = video_drvdata(filp); > + struct vpu_instance *inst = NULL; > + int ret = 0; > + > + inst = kzalloc(sizeof(*inst), GFP_KERNEL); > + if (!inst) > + return -ENOMEM; > + > + inst->dev = dev; > + inst->type = VPU_INST_TYPE_DEC; > + inst->ops = &wave5_vpu_dec_inst_ops; > + > + v4l2_fh_init(&inst->v4l2_fh, vdev); > + filp->private_data = &inst->v4l2_fh; > + v4l2_fh_add(&inst->v4l2_fh); > + > + INIT_LIST_HEAD(&inst->list); > + list_add_tail(&inst->list, &dev->instances); > + > + inst->v4l2_m2m_dev = v4l2_m2m_init(&wave5_vpu_dec_m2m_ops); > + if (IS_ERR(inst->v4l2_m2m_dev)) { > + ret = PTR_ERR(inst->v4l2_m2m_dev); > + dev_err(inst->dev->dev, "v4l2_m2m_init, fail: %d\n", ret); > + goto cleanup_inst; > + } > + > + inst->v4l2_fh.m2m_ctx = > + v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_dec_queue_init); > + if (IS_ERR(inst->v4l2_fh.m2m_ctx)) { > + ret = PTR_ERR(inst->v4l2_fh.m2m_ctx); > + goto cleanup_inst; > + } > + > + v4l2_ctrl_handler_init(&inst->v4l2_ctrl_hdl, 10); > + v4l2_ctrl_new_custom(&inst->v4l2_ctrl_hdl, &wave5_vpu_thumbnail_mode, NULL); > + v4l2_ctrl_new_std(&inst->v4l2_ctrl_hdl, &wave5_vpu_dec_ctrl_ops, > + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 1); > + > + if (inst->v4l2_ctrl_hdl.error) { > + ret = -ENODEV; > + goto cleanup_inst; > + } > + > + inst->v4l2_fh.ctrl_handler = &inst->v4l2_ctrl_hdl; > + v4l2_ctrl_handler_setup(&inst->v4l2_ctrl_hdl); > + > + wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); > + inst->colorspace = V4L2_COLORSPACE_REC709; > + inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; > + inst->hsv_enc = 0; > + inst->quantization = V4L2_QUANTIZATION_DEFAULT; > + inst->xfer_func = V4L2_XFER_FUNC_DEFAULT; > + > + init_completion(&inst->irq_done); > + ret = kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL); > + if (ret) { > + dev_err(inst->dev->dev, "failed to allocate fifo\n"); > + goto cleanup_inst; > + } > + > + inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); > + if (inst->id < 0) { > + dev_warn(inst->dev->dev, "Allocating instance ID, fail: %d\n", inst->id); > + ret = inst->id; > + goto cleanup_inst; > + } > + > + return 0; > + > +cleanup_inst: > + wave5_cleanup_instance(inst); > + return ret; > +} > + > +static int wave5_vpu_dec_release(struct file *filp) > +{ > + return wave5_vpu_release_device(filp, wave5_vpu_dec_close, "decoder"); > +} > + > +static const struct v4l2_file_operations wave5_vpu_dec_fops = { > + .owner = THIS_MODULE, > + .open = wave5_vpu_open_dec, > + .release = wave5_vpu_dec_release, > + .unlocked_ioctl = video_ioctl2, > + .poll = v4l2_m2m_fop_poll, > + .mmap = v4l2_m2m_fop_mmap, > +}; > + > +int wave5_vpu_dec_register_device(struct vpu_device *dev) > +{ > + struct video_device *vdev_dec; > + int ret; > + > + vdev_dec = devm_kzalloc(dev->v4l2_dev.dev, sizeof(*vdev_dec), GFP_KERNEL); > + if (!vdev_dec) > + return -ENOMEM; > + > + dev->video_dev_dec = vdev_dec; > + > + strscpy(vdev_dec->name, VPU_DEC_DEV_NAME, sizeof(vdev_dec->name)); > + vdev_dec->fops = &wave5_vpu_dec_fops; > + vdev_dec->ioctl_ops = &wave5_vpu_dec_ioctl_ops; > + vdev_dec->release = video_device_release_empty; > + vdev_dec->v4l2_dev = &dev->v4l2_dev; > + vdev_dec->vfl_dir = VFL_DIR_M2M; > + vdev_dec->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; > + vdev_dec->lock = &dev->dev_lock; > + > + ret = video_register_device(vdev_dec, VFL_TYPE_VIDEO, -1); > + if (ret) > + return ret; > + > + video_set_drvdata(vdev_dec, dev); > + > + return 0; > +} > + > +void wave5_vpu_dec_unregister_device(struct vpu_device *dev) > +{ > + video_unregister_device(dev->video_dev_dec); > +} > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c Decoder and encoder could certainly be split in two commits here. I'll resume with the encoder later. > new file mode 100644 > index 000000000000..285111c2d9cd > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c > @@ -0,0 +1,1746 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > +/* > + * Wave5 series multi-standard codec IP - encoder interface > + * > + * Copyright (C) 2021 CHIPS&MEDIA INC > + */ > + > +#include "wave5-helper.h" > + > +#define VPU_ENC_DEV_NAME "C&M Wave5 VPU encoder" > +#define VPU_ENC_DRV_NAME "wave5-enc" > + > +static const struct vpu_format enc_fmt_list[FMT_TYPES][MAX_FMTS] = { > + [VPU_FMT_TYPE_CODEC] = { > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_HEVC, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_H264, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + }, > + [VPU_FMT_TYPE_RAW] = { > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV12, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV21, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV12M, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + { > + .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, > + .max_width = W5_MAX_ENC_PIC_WIDTH, > + .min_width = W5_MIN_ENC_PIC_WIDTH, > + .max_height = W5_MAX_ENC_PIC_HEIGHT, > + .min_height = W5_MIN_ENC_PIC_HEIGHT, > + }, > + } > +}; > + > +static enum wave_std wave5_to_vpu_wavestd(unsigned int v4l2_pix_fmt) > +{ > + switch (v4l2_pix_fmt) { > + case V4L2_PIX_FMT_H264: > + return W_AVC_ENC; > + case V4L2_PIX_FMT_HEVC: > + return W_HEVC_ENC; > + default: > + return STD_UNKNOWN; > + } > +} > + > +static struct vb2_v4l2_buffer *wave5_get_valid_src_buf(struct vpu_instance *inst) > +{ > + struct v4l2_m2m_buffer *v4l2_m2m_buf; > + > + v4l2_m2m_for_each_src_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { > + struct vb2_v4l2_buffer *vb2_v4l2_buf; > + struct vpu_buffer *vpu_buf = NULL; > + > + vb2_v4l2_buf = &v4l2_m2m_buf->vb; > + vpu_buf = wave5_to_vpu_buf(vb2_v4l2_buf); > + > + if (!vpu_buf->consumed) { > + dev_dbg(inst->dev->dev, "%s: src buf (index: %u) has not been consumed\n", > + __func__, vb2_v4l2_buf->vb2_buf.index); > + return vb2_v4l2_buf; > + } > + } > + > + return NULL; > +} > + > +static struct vb2_v4l2_buffer *wave5_get_valid_dst_buf(struct vpu_instance *inst) > +{ > + struct v4l2_m2m_buffer *v4l2_m2m_buf; > + > + v4l2_m2m_for_each_dst_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { > + struct vb2_v4l2_buffer *vb2_v4l2_buf; > + struct vpu_buffer *vpu_buf = NULL; > + > + vb2_v4l2_buf = &v4l2_m2m_buf->vb; > + vpu_buf = wave5_to_vpu_buf(vb2_v4l2_buf); > + > + if (!vpu_buf->consumed) { > + dev_dbg(inst->dev->dev, "%s: dst buf (index: %u) has not been consumed\n", > + __func__, vb2_v4l2_buf->vb2_buf.index); > + return vb2_v4l2_buf; > + } > + } > + > + return NULL; > +} > + > +static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width, > + unsigned int height) > +{ > + switch (pix_mp->pixelformat) { > + case V4L2_PIX_FMT_YUV420: > + case V4L2_PIX_FMT_NV12: > + case V4L2_PIX_FMT_NV21: > + pix_mp->width = width; > + pix_mp->height = height; > + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); > + pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height * 3 / 2; > + break; > + case V4L2_PIX_FMT_YUV420M: > + pix_mp->width = width; > + pix_mp->height = height; > + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); > + pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height; > + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; > + pix_mp->plane_fmt[1].sizeimage = round_up(width, 32) * height / 4; > + pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; > + pix_mp->plane_fmt[2].sizeimage = round_up(width, 32) * height / 4; > + break; > + case V4L2_PIX_FMT_NV12M: > + case V4L2_PIX_FMT_NV21M: > + pix_mp->width = width; > + pix_mp->height = height; > + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); > + pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height; > + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); > + pix_mp->plane_fmt[1].sizeimage = round_up(width, 32) * height / 2; > + break; > + default: > + pix_mp->width = width; > + pix_mp->height = height; > + pix_mp->plane_fmt[0].bytesperline = 0; > + pix_mp->plane_fmt[0].sizeimage = width * height; > + break; > + } > +} > + > +static void wave5_vpu_enc_start_encode(struct vpu_instance *inst) > +{ > + u32 max_cmd_q = 0; > + > + max_cmd_q = (inst->src_buf_count < COMMAND_QUEUE_DEPTH) ? > + inst->src_buf_count : COMMAND_QUEUE_DEPTH; > + > + if (inst->state == VPU_INST_STATE_STOP) > + max_cmd_q = 1; > + > + while (max_cmd_q) { > + struct vb2_v4l2_buffer *src_buf; > + struct vb2_v4l2_buffer *dst_buf; > + struct vpu_buffer *src_vbuf; > + struct vpu_buffer *dst_vbuf; > + struct frame_buffer frame_buf; > + struct enc_param pic_param; > + u32 stride = ALIGN(inst->dst_fmt.width, 32); > + u32 luma_size = (stride * inst->dst_fmt.height); > + u32 chroma_size = ((stride / 2) * (inst->dst_fmt.height / 2)); > + u32 fail_res; > + int ret; > + > + memset(&pic_param, 0, sizeof(struct enc_param)); > + memset(&frame_buf, 0, sizeof(struct frame_buffer)); > + > + src_buf = wave5_get_valid_src_buf(inst); > + dst_buf = wave5_get_valid_dst_buf(inst); > + > + if (!dst_buf) { > + dev_dbg(inst->dev->dev, "%s: No valid dst buf\n", __func__); > + break; > + } > + > + dst_vbuf = wave5_to_vpu_buf(dst_buf); > + pic_param.pic_stream_buffer_addr = > + vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); > + pic_param.pic_stream_buffer_size = > + vb2_plane_size(&dst_buf->vb2_buf, 0); > + > + if (!src_buf) { > + dev_dbg(inst->dev->dev, "%s: No valid src buf\n", __func__); > + if (inst->state == VPU_INST_STATE_STOP) > + pic_param.src_end_flag = true; > + else > + break; > + } else { > + src_vbuf = wave5_to_vpu_buf(src_buf); > + if (inst->src_fmt.num_planes == 1) { > + frame_buf.buf_y = > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); > + frame_buf.buf_cb = frame_buf.buf_y + luma_size; > + frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; > + } else if (inst->src_fmt.num_planes == 2) { > + frame_buf.buf_y = > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); > + frame_buf.buf_cb = > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); > + frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; > + } else if (inst->src_fmt.num_planes == 3) { > + frame_buf.buf_y = > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); > + frame_buf.buf_cb = > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); > + frame_buf.buf_cr = > + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 2); > + } > + frame_buf.stride = stride; > + pic_param.src_idx = src_buf->vb2_buf.index; > + } > + > + pic_param.source_frame = &frame_buf; > + pic_param.code_option.implicit_header_encode = 1; > + ret = wave5_vpu_enc_start_one_frame(inst, &pic_param, &fail_res); > + if (ret) { > + if (fail_res == WAVE5_SYSERR_QUEUEING_FAIL) > + break; > + > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame fail: %d\n", > + __func__, ret); > + src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); > + if (!src_buf) { > + dev_dbg(inst->dev->dev, > + "%s: Removing src buf failed, the queue is empty\n", > + __func__); > + continue; > + } > + dst_buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx); > + if (!dst_buf) { > + dev_dbg(inst->dev->dev, > + "%s: Removing dst buf failed, the queue is empty\n", > + __func__); > + continue; > + } > + inst->state = VPU_INST_STATE_STOP; > + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); > + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR); > + } else { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame success\n", > + __func__); > + if (src_buf) > + src_vbuf->consumed = true; > + if (dst_buf) > + dst_vbuf->consumed = true; > + } > + > + max_cmd_q--; > + } > +} > + > +static void wave5_vpu_enc_stop_encode(struct vpu_instance *inst) > +{ > + inst->state = VPU_INST_STATE_STOP; > + > + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); > +} > + > +static void wave5_vpu_enc_finish_encode(struct vpu_instance *inst) > +{ > + int ret; > + struct enc_output_info enc_output_info; > + u32 irq_status; > + struct vb2_v4l2_buffer *dst_buf = NULL; > + struct v4l2_m2m_buffer *v4l2_m2m_buf = NULL; > + > + if (kfifo_out(&inst->irq_status, &irq_status, sizeof(int))) > + wave5_vpu_clear_interrupt_ex(inst, irq_status); > + > + ret = wave5_vpu_enc_get_output_info(inst, &enc_output_info); > + if (ret) { > + dev_dbg(inst->dev->dev, > + "%s: vpu_enc_get_output_info fail: %d reason: %u | info: %u\n", > + __func__, ret, enc_output_info.error_reason, enc_output_info.warn_info); > + return; > + } > + > + v4l2_m2m_for_each_dst_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { > + dst_buf = &v4l2_m2m_buf->vb; > + if (enc_output_info.bitstream_buffer == > + vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0)) > + break; > + } > + > + if (enc_output_info.enc_src_idx >= 0) { > + struct vb2_v4l2_buffer *src_buf = > + v4l2_m2m_src_buf_remove_by_idx(inst->v4l2_fh.m2m_ctx, > + enc_output_info.enc_src_idx); > + > + inst->timestamp = src_buf->vb2_buf.timestamp; > + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); > + } > + > + if (enc_output_info.recon_frame_index == RECON_IDX_FLAG_ENC_END) { > + static const struct v4l2_event vpu_event_eos = { > + .type = V4L2_EVENT_EOS > + }; > + > + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, 0); > + dst_buf->vb2_buf.timestamp = inst->timestamp; > + dst_buf->field = V4L2_FIELD_NONE; > + dst_buf->flags |= V4L2_BUF_FLAG_LAST; > + v4l2_m2m_dst_buf_remove_by_buf(inst->v4l2_fh.m2m_ctx, dst_buf); > + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); > + > + inst->state = VPU_INST_STATE_PIC_RUN; > + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos); > + > + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); > + } else { > + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, enc_output_info.bitstream_size); > + > + dst_buf->vb2_buf.timestamp = inst->timestamp; > + dst_buf->field = V4L2_FIELD_NONE; > + if (enc_output_info.pic_type == PIC_TYPE_I) { > + if (enc_output_info.enc_vcl_nut == 19 || > + enc_output_info.enc_vcl_nut == 20) > + dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME; > + else > + dst_buf->flags |= V4L2_BUF_FLAG_PFRAME; > + } else if (enc_output_info.pic_type == PIC_TYPE_P) { > + dst_buf->flags |= V4L2_BUF_FLAG_PFRAME; > + } else if (enc_output_info.pic_type == PIC_TYPE_B) { > + dst_buf->flags |= V4L2_BUF_FLAG_BFRAME; > + } > + > + v4l2_m2m_dst_buf_remove_by_buf(inst->v4l2_fh.m2m_ctx, dst_buf); > + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); > + > + dev_dbg(inst->dev->dev, "%s: frame_cycle %8u\n", > + __func__, enc_output_info.frame_cycle); > + } > +} > + > +static int wave5_vpu_enc_querycap(struct file *file, void *fh, struct v4l2_capability *cap) > +{ > + strscpy(cap->driver, VPU_ENC_DRV_NAME, sizeof(cap->driver)); > + strscpy(cap->card, VPU_ENC_DRV_NAME, sizeof(cap->card)); > + strscpy(cap->bus_info, "platform:" VPU_ENC_DRV_NAME, sizeof(cap->bus_info)); > + > + return 0; > +} > + > +static int wave5_vpu_enc_enum_framesizes(struct file *f, void *fh, struct v4l2_frmsizeenum *fsize) > +{ > + const struct vpu_format *vpu_fmt; > + > + if (fsize->index) > + return -EINVAL; > + > + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, enc_fmt_list[VPU_FMT_TYPE_CODEC]); > + if (!vpu_fmt) { > + vpu_fmt = wave5_find_vpu_fmt(fsize->pixel_format, enc_fmt_list[VPU_FMT_TYPE_RAW]); > + if (!vpu_fmt) > + return -EINVAL; > + } > + > + fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; > + fsize->stepwise.min_width = vpu_fmt->min_width; > + fsize->stepwise.max_width = vpu_fmt->max_width; > + fsize->stepwise.step_width = 1; > + fsize->stepwise.min_height = vpu_fmt->min_height; > + fsize->stepwise.max_height = vpu_fmt->max_height; > + fsize->stepwise.step_height = 1; > + > + return 0; > +} > + > +static int wave5_vpu_enc_enum_fmt_cap(struct file *file, void *fh, struct v4l2_fmtdesc *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); > + > + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, enc_fmt_list[VPU_FMT_TYPE_CODEC]); > + if (!vpu_fmt) > + return -EINVAL; > + > + f->pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->flags = 0; > + > + return 0; > +} > + > +static int wave5_vpu_enc_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > + > + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) > + return -EINVAL; > + > + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]); > + if (!vpu_fmt) { > + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; > + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; > + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height); > + } else { > + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); > + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); > + > + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->fmt.pix_mp.num_planes = 1; > + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); > + } > + > + f->fmt.pix_mp.flags = 0; > + f->fmt.pix_mp.field = V4L2_FIELD_NONE; > + f->fmt.pix_mp.colorspace = inst->colorspace; > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > + f->fmt.pix_mp.quantization = inst->quantization; > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); > + > + return 0; > +} > + > +static int wave5_vpu_enc_s_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i, ret; > + > + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > + > + ret = wave5_vpu_enc_try_fmt_cap(file, fh, f); > + if (ret) > + return ret; > + > + inst->dst_fmt.width = f->fmt.pix_mp.width; > + inst->dst_fmt.height = f->fmt.pix_mp.height; > + inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat; > + inst->dst_fmt.field = f->fmt.pix_mp.field; > + inst->dst_fmt.flags = f->fmt.pix_mp.flags; > + inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes; > + for (i = 0; i < inst->dst_fmt.num_planes; i++) { > + inst->dst_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; > + inst->dst_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; > + } > + > + return 0; > +} > + > +static int wave5_vpu_enc_g_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i; > + > + f->fmt.pix_mp.width = inst->dst_fmt.width; > + f->fmt.pix_mp.height = inst->dst_fmt.height; > + f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; > + f->fmt.pix_mp.field = inst->dst_fmt.field; > + f->fmt.pix_mp.flags = inst->dst_fmt.flags; > + f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; > + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { > + f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->dst_fmt.plane_fmt[i].bytesperline; > + f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->dst_fmt.plane_fmt[i].sizeimage; > + } > + > + f->fmt.pix_mp.colorspace = inst->colorspace; > + f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; > + f->fmt.pix_mp.hsv_enc = inst->hsv_enc; > + f->fmt.pix_mp.quantization = inst->quantization; > + f->fmt.pix_mp.xfer_func = inst->xfer_func; > + > + return 0; > +} > + > +static int wave5_vpu_enc_enum_fmt_out(struct file *file, void *fh, struct v4l2_fmtdesc *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, "%s: index: %u\n", __func__, f->index); > + > + vpu_fmt = wave5_find_vpu_fmt_by_idx(f->index, enc_fmt_list[VPU_FMT_TYPE_RAW]); > + if (!vpu_fmt) > + return -EINVAL; > + > + f->pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->flags = 0; > + > + return 0; > +} > + > +static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + const struct vpu_format *vpu_fmt; > + > + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > + > + if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + return -EINVAL; > + > + vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_RAW]); > + if (!vpu_fmt) { > + f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; > + f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; > + wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height); > + } else { > + int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); > + int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); > + const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); > + > + f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; > + f->fmt.pix_mp.num_planes = info->mem_planes; > + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); > + } > + > + f->fmt.pix_mp.flags = 0; > + f->fmt.pix_mp.field = V4L2_FIELD_NONE; > + memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); > + > + return 0; > +} > + > +static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int i, ret; > + > + dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", > + __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, > + f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); > + > + ret = wave5_vpu_enc_try_fmt_out(file, fh, f); > + if (ret) > + return ret; > + > + inst->src_fmt.width = f->fmt.pix_mp.width; > + inst->src_fmt.height = f->fmt.pix_mp.height; > + inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat; > + inst->src_fmt.field = f->fmt.pix_mp.field; > + inst->src_fmt.flags = f->fmt.pix_mp.flags; > + inst->src_fmt.num_planes = f->fmt.pix_mp.num_planes; > + for (i = 0; i < inst->src_fmt.num_planes; i++) { > + inst->src_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline; > + inst->src_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage; > + } > + > + if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12 || > + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12M) { > + inst->cbcr_interleave = true; > + inst->nv21 = false; > + } else if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21 || > + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21M) { > + inst->cbcr_interleave = true; > + inst->nv21 = true; > + } else { > + inst->cbcr_interleave = false; > + inst->nv21 = false; > + } > + > + inst->colorspace = f->fmt.pix_mp.colorspace; > + inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; > + inst->hsv_enc = f->fmt.pix_mp.hsv_enc; > + inst->quantization = f->fmt.pix_mp.quantization; > + inst->xfer_func = f->fmt.pix_mp.xfer_func; > + > + wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height); > + > + return 0; > +} > + > +static int wave5_vpu_enc_g_selection(struct file *file, void *fh, struct v4l2_selection *s) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + > + dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target); > + > + if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { > + switch (s->target) { > + case V4L2_SEL_TGT_CROP_DEFAULT: > + case V4L2_SEL_TGT_CROP_BOUNDS: > + s->r.left = 0; > + s->r.top = 0; > + s->r.width = inst->dst_fmt.width; > + s->r.height = inst->dst_fmt.height; > + break; > + case V4L2_SEL_TGT_CROP: > + s->r.left = 0; > + s->r.top = 0; > + s->r.width = inst->dst_fmt.width; > + s->r.height = inst->dst_fmt.height; > + dev_dbg(inst->dev->dev, "%s: V4L2_SEL_TGT_CROP width: %u | height: %u\n", > + __func__, s->r.width, s->r.height); > + break; > + default: > + return -EINVAL; > + } > + } else { > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int wave5_vpu_enc_s_selection(struct file *file, void *fh, struct v4l2_selection *s) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + > + if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) > + return -EINVAL; > + > + if (s->target != V4L2_SEL_TGT_CROP) > + return -EINVAL; > + > + dev_dbg(inst->dev->dev, "%s: V4L2_SEL_TGT_CROP width: %u | height: %u\n", > + __func__, s->r.width, s->r.height); > + > + s->r.left = 0; > + s->r.top = 0; > + s->r.width = inst->src_fmt.width; > + s->r.height = inst->src_fmt.height; > + > + return 0; > +} > + > +static int wave5_vpu_enc_encoder_cmd(struct file *file, void *fh, struct v4l2_encoder_cmd *ec) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + int ret; > + > + ret = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, ec); > + if (ret) > + return ret; > + > + if (!wave5_vpu_both_queues_are_streaming(inst)) > + return 0; > + > + switch (ec->cmd) { > + case V4L2_ENC_CMD_STOP: > + inst->state = VPU_INST_STATE_STOP; > + inst->ops->start_process(inst); > + break; > + case V4L2_ENC_CMD_START: > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static int wave5_vpu_enc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, a->type); > + > + if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + return -EINVAL; > + > + a->parm.output.capability = V4L2_CAP_TIMEPERFRAME; > + a->parm.output.timeperframe.numerator = 1; > + a->parm.output.timeperframe.denominator = inst->frame_rate; > + > + dev_dbg(inst->dev->dev, "%s: numerator: %u | denominator: %u\n", > + __func__, a->parm.output.timeperframe.numerator, > + a->parm.output.timeperframe.denominator); > + > + return 0; > +} > + > +static int wave5_vpu_enc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a) > +{ > + struct vpu_instance *inst = wave5_to_vpu_inst(fh); > + > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, a->type); > + > + if (a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT && a->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + return -EINVAL; > + > + a->parm.output.capability = V4L2_CAP_TIMEPERFRAME; > + if (a->parm.output.timeperframe.denominator && a->parm.output.timeperframe.numerator) { > + inst->frame_rate = a->parm.output.timeperframe.denominator / > + a->parm.output.timeperframe.numerator; > + } else { > + a->parm.output.timeperframe.numerator = 1; > + a->parm.output.timeperframe.denominator = inst->frame_rate; > + } > + > + dev_dbg(inst->dev->dev, "%s: numerator: %u | denominator: %u\n", > + __func__, a->parm.output.timeperframe.numerator, > + a->parm.output.timeperframe.denominator); > + > + return 0; > +} > + > +static const struct v4l2_ioctl_ops wave5_vpu_enc_ioctl_ops = { > + .vidioc_querycap = wave5_vpu_enc_querycap, > + .vidioc_enum_framesizes = wave5_vpu_enc_enum_framesizes, > + > + .vidioc_enum_fmt_vid_cap = wave5_vpu_enc_enum_fmt_cap, > + .vidioc_s_fmt_vid_cap_mplane = wave5_vpu_enc_s_fmt_cap, > + .vidioc_g_fmt_vid_cap_mplane = wave5_vpu_enc_g_fmt_cap, > + .vidioc_try_fmt_vid_cap_mplane = wave5_vpu_enc_try_fmt_cap, > + > + .vidioc_enum_fmt_vid_out = wave5_vpu_enc_enum_fmt_out, > + .vidioc_s_fmt_vid_out_mplane = wave5_vpu_enc_s_fmt_out, > + .vidioc_g_fmt_vid_out_mplane = wave5_vpu_g_fmt_out, > + .vidioc_try_fmt_vid_out_mplane = wave5_vpu_enc_try_fmt_out, > + > + .vidioc_g_selection = wave5_vpu_enc_g_selection, > + .vidioc_s_selection = wave5_vpu_enc_s_selection, > + > + .vidioc_g_parm = wave5_vpu_enc_g_parm, > + .vidioc_s_parm = wave5_vpu_enc_s_parm, > + > + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, > + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, > + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, > + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, > + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, > + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, > + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, > + .vidioc_streamon = v4l2_m2m_ioctl_streamon, > + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, > + > + .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd, > + .vidioc_encoder_cmd = wave5_vpu_enc_encoder_cmd, > + > + .vidioc_subscribe_event = wave5_vpu_subscribe_event, > + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, > +}; > + > +static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl) > +{ > + struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl); > + > + dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n", __func__, ctrl->name, ctrl->val); > + > + switch (ctrl->id) { > + case V4L2_CID_HFLIP: > + inst->mirror_direction |= (ctrl->val << 1); > + break; > + case V4L2_CID_VFLIP: > + inst->mirror_direction |= ctrl->val; > + break; > + case V4L2_CID_ROTATE: > + inst->rot_angle = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_VBV_SIZE: > + inst->vbv_buf_size = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR: > + inst->rc_mode = 0; > + break; > + case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR: > + inst->rc_mode = 1; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_BITRATE: > + inst->bit_rate = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_GOP_SIZE: > + inst->enc_param.avc_idr_period = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE: > + inst->enc_param.independ_slice_mode = ctrl->val; > + inst->enc_param.avc_slice_mode = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB: > + inst->enc_param.independ_slice_mode_arg = ctrl->val; > + inst->enc_param.avc_slice_arg = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: > + inst->rc_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE: > + inst->enc_param.mb_level_rc_enable = ctrl->val; > + inst->enc_param.cu_level_rc_enable = ctrl->val; > + inst->enc_param.hvs_qp_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN: > + inst->enc_param.profile = HEVC_PROFILE_MAIN; > + inst->bit_depth = 8; > + break; > + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE: > + inst->enc_param.profile = HEVC_PROFILE_STILLPICTURE; > + inst->enc_param.en_still_picture = 1; > + inst->bit_depth = 8; > + break; > + case V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10: > + inst->enc_param.profile = HEVC_PROFILE_MAIN10; > + inst->bit_depth = 10; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_1: > + inst->enc_param.level = 10 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2: > + inst->enc_param.level = 20 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1: > + inst->enc_param.level = 21 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3: > + inst->enc_param.level = 30 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1: > + inst->enc_param.level = 31 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4: > + inst->enc_param.level = 40 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1: > + inst->enc_param.level = 41 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5: > + inst->enc_param.level = 50 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1: > + inst->enc_param.level = 51 * 3; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2: > + inst->enc_param.level = 52 * 3; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: > + inst->enc_param.min_qp_i = ctrl->val; > + inst->enc_param.min_qp_p = ctrl->val; > + inst->enc_param.min_qp_b = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: > + inst->enc_param.max_qp_i = ctrl->val; > + inst->enc_param.max_qp_p = ctrl->val; > + inst->enc_param.max_qp_b = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: > + inst->enc_param.intra_qp = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED: > + inst->enc_param.disable_deblk = 1; > + inst->enc_param.sao_enable = 0; > + inst->enc_param.lf_cross_slice_boundary_enable = 0; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED: > + inst->enc_param.disable_deblk = 0; > + inst->enc_param.sao_enable = 1; > + inst->enc_param.lf_cross_slice_boundary_enable = 1; > + break; > + case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY: > + inst->enc_param.disable_deblk = 0; > + inst->enc_param.sao_enable = 1; > + inst->enc_param.lf_cross_slice_boundary_enable = 0; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2: > + inst->enc_param.beta_offset_div2 = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2: > + inst->enc_param.tc_offset_div2 = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE: > + inst->enc_param.decoding_refresh_type = 0; > + break; > + case V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA: > + inst->enc_param.decoding_refresh_type = 1; > + break; > + case V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR: > + inst->enc_param.decoding_refresh_type = 2; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD: > + inst->enc_param.intra_period = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU: > + inst->enc_param.lossless_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED: > + inst->enc_param.const_intra_pred_flag = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT: > + inst->enc_param.wpp_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING: > + inst->enc_param.strong_intra_smooth_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1: > + inst->enc_param.max_num_merge = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION: > + inst->enc_param.tmvp_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_PROFILE: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: > + case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: > + inst->enc_param.profile = H264_PROFILE_BP; > + inst->bit_depth = 8; > + break; > + case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: > + inst->enc_param.profile = H264_PROFILE_MP; > + inst->bit_depth = 8; > + break; > + case V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED: > + inst->enc_param.profile = H264_PROFILE_EXTENDED; > + inst->bit_depth = 8; > + break; > + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: > + inst->enc_param.profile = H264_PROFILE_HP; > + inst->bit_depth = 8; > + break; > + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10: > + inst->enc_param.profile = H264_PROFILE_HIGH10; > + inst->bit_depth = 10; > + break; > + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422: > + inst->enc_param.profile = H264_PROFILE_HIGH422; > + inst->bit_depth = 10; > + break; > + case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE: > + inst->enc_param.profile = H264_PROFILE_HIGH444; > + inst->bit_depth = 10; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_H264_LEVEL: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: > + inst->enc_param.level = 10; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_1B: > + inst->enc_param.level = 9; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: > + inst->enc_param.level = 11; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: > + inst->enc_param.level = 12; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: > + inst->enc_param.level = 13; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: > + inst->enc_param.level = 20; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: > + inst->enc_param.level = 21; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: > + inst->enc_param.level = 22; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: > + inst->enc_param.level = 30; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: > + inst->enc_param.level = 31; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: > + inst->enc_param.level = 32; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: > + inst->enc_param.level = 40; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_4_1: > + inst->enc_param.level = 41; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_4_2: > + inst->enc_param.level = 42; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_5_0: > + inst->enc_param.level = 50; > + break; > + case V4L2_MPEG_VIDEO_H264_LEVEL_5_1: > + inst->enc_param.level = 51; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: > + inst->enc_param.min_qp_i = ctrl->val; > + inst->enc_param.min_qp_p = ctrl->val; > + inst->enc_param.min_qp_b = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: > + inst->enc_param.max_qp_i = ctrl->val; > + inst->enc_param.max_qp_p = ctrl->val; > + inst->enc_param.max_qp_b = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: > + inst->enc_param.intra_qp = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE: > + switch (ctrl->val) { > + case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED: > + inst->enc_param.disable_deblk = 1; > + inst->enc_param.lf_cross_slice_boundary_enable = 1; > + break; > + case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED: > + inst->enc_param.disable_deblk = 0; > + inst->enc_param.lf_cross_slice_boundary_enable = 1; > + break; > + case V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY: > + inst->enc_param.disable_deblk = 0; > + inst->enc_param.lf_cross_slice_boundary_enable = 0; > + break; > + default: > + return -EINVAL; > + } > + break; > + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA: > + inst->enc_param.beta_offset_div2 = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA: > + inst->enc_param.tc_offset_div2 = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM: > + inst->enc_param.transform8x8_enable = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: > + inst->enc_param.const_intra_pred_flag = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET: > + inst->enc_param.chroma_cb_qp_offset = ctrl->val; > + inst->enc_param.chroma_cr_qp_offset = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_I_PERIOD: > + inst->enc_param.intra_period = ctrl->val; > + break; > + case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: > + inst->enc_param.entropy_coding_mode = ctrl->val; > + break; > + case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT: > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +static const struct v4l2_ctrl_ops wave5_vpu_enc_ctrl_ops = { > + .s_ctrl = wave5_vpu_enc_s_ctrl, > +}; > + > +static void wave5_set_enc_openparam(struct enc_open_param *open_param, > + struct vpu_instance *inst) > +{ > + struct enc_wave_param input = inst->enc_param; > + u32 num_ctu_row = ALIGN(inst->dst_fmt.height, 64) / 64; > + u32 num_mb_row = ALIGN(inst->dst_fmt.height, 16) / 16; > + > + open_param->wave_param.gop_preset_idx = PRESET_IDX_IPP_SINGLE; > + open_param->wave_param.hvs_qp_scale = 2; > + open_param->wave_param.hvs_max_delta_qp = 10; > + open_param->wave_param.skip_intra_trans = 1; > + open_param->wave_param.intra_nx_n_enable = 1; > + open_param->wave_param.nr_intra_weight_y = 7; > + open_param->wave_param.nr_intra_weight_cb = 7; > + open_param->wave_param.nr_intra_weight_cr = 7; > + open_param->wave_param.nr_inter_weight_y = 4; > + open_param->wave_param.nr_inter_weight_cb = 4; > + open_param->wave_param.nr_inter_weight_cr = 4; > + open_param->wave_param.rdo_skip = 1; > + open_param->wave_param.lambda_scaling_enable = 1; > + > + open_param->stream_endian = VPU_STREAM_ENDIAN; > + open_param->source_endian = VPU_SOURCE_ENDIAN; > + open_param->line_buf_int_en = true; > + open_param->pic_width = inst->dst_fmt.width; > + open_param->pic_height = inst->dst_fmt.height; > + open_param->frame_rate_info = inst->frame_rate; > + open_param->rc_enable = inst->rc_enable; > + if (inst->rc_enable) { > + open_param->wave_param.initial_rc_qp = -1; > + open_param->wave_param.rc_weight_param = 16; > + open_param->wave_param.rc_weight_buf = 128; > + } > + open_param->wave_param.mb_level_rc_enable = input.mb_level_rc_enable; > + open_param->wave_param.cu_level_rc_enable = input.cu_level_rc_enable; > + open_param->wave_param.hvs_qp_enable = input.hvs_qp_enable; > + open_param->bit_rate = inst->bit_rate; > + open_param->vbv_buffer_size = inst->vbv_buf_size; > + if (inst->rc_mode == 0) > + open_param->vbv_buffer_size = 3000; > + open_param->wave_param.profile = input.profile; > + open_param->wave_param.en_still_picture = input.en_still_picture; > + open_param->wave_param.level = input.level; > + open_param->wave_param.internal_bit_depth = inst->bit_depth; > + open_param->wave_param.intra_qp = input.intra_qp; > + open_param->wave_param.min_qp_i = input.min_qp_i; > + open_param->wave_param.max_qp_i = input.max_qp_i; > + open_param->wave_param.min_qp_p = input.min_qp_p; > + open_param->wave_param.max_qp_p = input.max_qp_p; > + open_param->wave_param.min_qp_b = input.min_qp_b; > + open_param->wave_param.max_qp_b = input.max_qp_b; > + open_param->wave_param.disable_deblk = input.disable_deblk; > + open_param->wave_param.lf_cross_slice_boundary_enable = > + input.lf_cross_slice_boundary_enable; > + open_param->wave_param.tc_offset_div2 = input.tc_offset_div2; > + open_param->wave_param.beta_offset_div2 = input.beta_offset_div2; > + open_param->wave_param.decoding_refresh_type = input.decoding_refresh_type; > + open_param->wave_param.intra_period = input.intra_period; > + if (inst->std == W_HEVC_ENC) { > + if (input.intra_period == 0) { > + open_param->wave_param.decoding_refresh_type = DEC_REFRESH_TYPE_IDR; > + open_param->wave_param.intra_period = input.avc_idr_period; > + } > + } else { > + open_param->wave_param.avc_idr_period = input.avc_idr_period; > + } > + open_param->wave_param.entropy_coding_mode = input.entropy_coding_mode; > + open_param->wave_param.lossless_enable = input.lossless_enable; > + open_param->wave_param.const_intra_pred_flag = input.const_intra_pred_flag; > + open_param->wave_param.wpp_enable = input.wpp_enable; > + open_param->wave_param.strong_intra_smooth_enable = input.strong_intra_smooth_enable; > + open_param->wave_param.max_num_merge = input.max_num_merge; > + open_param->wave_param.tmvp_enable = input.tmvp_enable; > + open_param->wave_param.transform8x8_enable = input.transform8x8_enable; > + open_param->wave_param.chroma_cb_qp_offset = input.chroma_cb_qp_offset; > + open_param->wave_param.chroma_cr_qp_offset = input.chroma_cr_qp_offset; > + open_param->wave_param.independ_slice_mode = input.independ_slice_mode; > + open_param->wave_param.independ_slice_mode_arg = input.independ_slice_mode_arg; > + open_param->wave_param.avc_slice_mode = input.avc_slice_mode; > + open_param->wave_param.avc_slice_arg = input.avc_slice_arg; > + open_param->wave_param.intra_mb_refresh_mode = input.intra_mb_refresh_mode; > + if (input.intra_mb_refresh_mode != REFRESH_MB_MODE_NONE) { > + if (num_mb_row >= input.intra_mb_refresh_arg) > + open_param->wave_param.intra_mb_refresh_arg = > + num_mb_row / input.intra_mb_refresh_arg; > + else > + open_param->wave_param.intra_mb_refresh_arg = num_mb_row; > + } > + open_param->wave_param.intra_refresh_mode = input.intra_refresh_mode; > + if (input.intra_refresh_mode != 0) { > + if (num_ctu_row >= input.intra_refresh_arg) > + open_param->wave_param.intra_refresh_arg = > + num_ctu_row / input.intra_refresh_arg; > + else > + open_param->wave_param.intra_refresh_arg = num_ctu_row; > + } > +} > + > +static int wave5_vpu_enc_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, > + unsigned int *num_planes, unsigned int sizes[], > + struct device *alloc_devs[]) > +{ > + struct vpu_instance *inst = vb2_get_drv_priv(q); > + struct v4l2_pix_format_mplane inst_format = > + (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; > + unsigned int i; > + int ret; > + > + dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, > + *num_buffers, *num_planes, q->type); > + > + if (*num_planes) { > + if (inst_format.num_planes != *num_planes) > + return -EINVAL; > + > + for (i = 0; i < *num_planes; i++) { > + if (sizes[i] < inst_format.plane_fmt[i].sizeimage) > + return -EINVAL; > + } > + } else { > + *num_planes = inst_format.num_planes; > + for (i = 0; i < *num_planes; i++) { > + sizes[i] = inst_format.plane_fmt[i].sizeimage; > + dev_dbg(inst->dev->dev, "%s: size[%u]: %u\n", __func__, i, sizes[i]); > + } > + } > + > + dev_dbg(inst->dev->dev, "%s: size: %u\n", __func__, sizes[0]); > + > + if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > + unsigned int non_linear_num = 0; > + u32 fb_stride = 0; > + u32 fb_height = 0; > + struct enc_open_param open_param; > + struct enc_initial_info initial_info; > + struct v4l2_ctrl *ctrl; > + > + memset(&open_param, 0, sizeof(struct enc_open_param)); > + > + inst->std = wave5_to_vpu_wavestd(inst->dst_fmt.pixelformat); > + if (inst->std == STD_UNKNOWN) { > + dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", > + (char *)&inst->dst_fmt.pixelformat); > + return -EINVAL; > + } > + > + wave5_set_enc_openparam(&open_param, inst); > + > + ret = wave5_vpu_enc_open(inst, &open_param); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_open, fail: %d\n", > + __func__, ret); > + return ret; > + } > + > + inst->state = VPU_INST_STATE_OPEN; > + > + if (inst->mirror_direction) { > + wave5_vpu_enc_give_command(inst, ENABLE_MIRRORING, NULL); > + wave5_vpu_enc_give_command(inst, SET_MIRROR_DIRECTION, > + &inst->mirror_direction); > + } > + if (inst->rot_angle) { > + wave5_vpu_enc_give_command(inst, ENABLE_ROTATION, NULL); > + wave5_vpu_enc_give_command(inst, SET_ROTATION_ANGLE, &inst->rot_angle); > + } > + > + ret = wave5_vpu_enc_issue_seq_init(inst); > + if (ret) { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_issue_seq_init, fail: %d\n", > + __func__, ret); > + return ret; > + } > + > + if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) { > + dev_dbg(inst->dev->dev, "%s: wave5_vpu_wait_interrupt failed\n", __func__); > + return -EINVAL; > + } > + > + ret = wave5_vpu_enc_complete_seq_init(inst, &initial_info); > + if (ret) > + return ret; > + > + dev_dbg(inst->dev->dev, "%s: min_frame_buffer: %u | min_source_buffer: %u\n", > + __func__, initial_info.min_frame_buffer_count, > + initial_info.min_src_frame_count); > + inst->state = VPU_INST_STATE_INIT_SEQ; > + inst->min_src_buf_count = initial_info.min_src_frame_count + > + COMMAND_QUEUE_DEPTH; > + > + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, > + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT); > + if (ctrl) > + v4l2_ctrl_s_ctrl(ctrl, inst->min_src_buf_count); > + > + inst->min_dst_buf_count = initial_info.min_frame_buffer_count; > + inst->src_buf_count = inst->min_src_buf_count; > + > + if (*num_buffers > inst->src_buf_count) > + inst->src_buf_count = *num_buffers; > + > + *num_buffers = inst->src_buf_count; > + non_linear_num = inst->min_dst_buf_count; > + > + fb_stride = ALIGN(inst->dst_fmt.width, 32); > + fb_height = ALIGN(inst->dst_fmt.height, 32); > + > + for (i = 0; i < non_linear_num; i++) { > + u32 luma_size = fb_stride * fb_height; > + u32 chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; > + > + inst->frame_vbuf[i].size = luma_size + chroma_size; > + ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->frame_vbuf[i]); > + if (ret < 0) { > + dev_dbg(inst->dev->dev, "%s: failed to allocate FBC buffer %zu\n", > + __func__, inst->frame_vbuf[i].size); > + goto free_buffers; > + } > + > + inst->frame_buf[i].buf_y = inst->frame_vbuf[i].daddr; > + inst->frame_buf[i].buf_cb = (dma_addr_t)-1; > + inst->frame_buf[i].buf_cr = (dma_addr_t)-1; > + inst->frame_buf[i].update_fb_info = true; > + inst->frame_buf[i].size = inst->frame_vbuf[i].size; > + } > + > + ret = wave5_vpu_enc_register_frame_buffer(inst, non_linear_num, fb_stride, > + fb_height, COMPRESSED_FRAME_MAP); > + if (ret) { > + dev_dbg(inst->dev->dev, > + "%s: wave5_vpu_enc_register_frame_buffer, fail: %d\n", > + __func__, ret); > + goto free_buffers; > + } > + > + inst->state = VPU_INST_STATE_PIC_RUN; > + } > + > + if (inst->state == VPU_INST_STATE_INIT_SEQ && > + q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > + *num_buffers = inst->src_buf_count; > + dev_dbg(inst->dev->dev, "%s: src buf num: %u", __func__, *num_buffers); > + } > + > + return 0; > + > +free_buffers: > + for (i = 0; i < inst->min_dst_buf_count; i++) > + wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[i]); > + return ret; > +} > + > +static void wave5_vpu_enc_buf_queue(struct vb2_buffer *vb) > +{ > + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); > + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); > + struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); > + > + dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n", > + __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), > + vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); > + > + if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) > + vbuf->sequence = inst->queued_src_buf_num++; > + else > + vbuf->sequence = inst->queued_dst_buf_num++; > + > + vpu_buf->consumed = FALSE; > + v4l2_m2m_buf_queue(inst->v4l2_fh.m2m_ctx, vbuf); > + > + if (vb2_start_streaming_called(vb->vb2_queue)) > + inst->ops->start_process(inst); > +} > + > +static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q) > +{ > + struct vpu_instance *inst = vb2_get_drv_priv(q); > + struct vb2_v4l2_buffer *buf; > + bool check_cmd = true; > + > + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); > + > + if (wave5_vpu_both_queues_are_streaming(inst)) > + inst->state = VPU_INST_STATE_STOP; > + > + while (check_cmd) { > + struct queue_status_info q_status; > + struct enc_output_info enc_output_info; > + > + wave5_vpu_enc_give_command(inst, ENC_GET_QUEUE_STATUS, &q_status); > + > + if (q_status.instance_queue_count + q_status.report_queue_count == 0) > + break; > + > + if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) > + break; > + > + if (wave5_vpu_enc_get_output_info(inst, &enc_output_info)) > + dev_dbg(inst->dev->dev, "Getting encoding results from fw, fail\n"); > + } > + > + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { > + while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { > + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); > + } > + } else { > + while ((buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx))) { > + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", > + __func__, buf->vb2_buf.type, buf->vb2_buf.index); > + vb2_set_plane_payload(&buf->vb2_buf, 0, 0); > + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); > + } > + } > +} > + > +static const struct vb2_ops wave5_vpu_enc_vb2_ops = { > + .queue_setup = wave5_vpu_enc_queue_setup, > + .wait_prepare = vb2_ops_wait_prepare, > + .wait_finish = vb2_ops_wait_finish, > + .buf_queue = wave5_vpu_enc_buf_queue, > + .stop_streaming = wave5_vpu_enc_stop_streaming, > +}; > + > +static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, > + struct v4l2_pix_format_mplane *dst_fmt) > +{ > + unsigned int src_pix_fmt = enc_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; > + const struct v4l2_format_info *src_fmt_info = v4l2_format_info(src_pix_fmt); > + > + src_fmt->pixelformat = src_pix_fmt; > + src_fmt->field = V4L2_FIELD_NONE; > + src_fmt->flags = 0; > + src_fmt->num_planes = src_fmt_info->mem_planes; > + wave5_update_pix_fmt(src_fmt, 416, 240); > + > + dst_fmt->pixelformat = enc_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; > + dst_fmt->field = V4L2_FIELD_NONE; > + dst_fmt->flags = 0; > + dst_fmt->num_planes = 1; > + wave5_update_pix_fmt(dst_fmt, 416, 240); > +} > + > +static int wave5_vpu_enc_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) > +{ > + return wave5_vpu_queue_init(priv, src_vq, dst_vq, &wave5_vpu_enc_vb2_ops); > +} > + > +static const struct vpu_instance_ops wave5_vpu_enc_inst_ops = { > + .start_process = wave5_vpu_enc_start_encode, > + .stop_process = wave5_vpu_enc_stop_encode, > + .finish_process = wave5_vpu_enc_finish_encode, > +}; > + > +static void wave5_vpu_enc_device_run(void *priv) > +{ > + struct vpu_instance *inst = priv; > + > + inst->ops->start_process(inst); > +} > + > +static int wave5_vpu_enc_job_ready(void *priv) > +{ > + struct vpu_instance *inst = priv; > + > + if (inst->state == VPU_INST_STATE_STOP) > + return 0; > + > + return 1; > +} > + > +static void wave5_vpu_enc_job_abort(void *priv) > +{ > + struct vpu_instance *inst = priv; > + > + inst->ops->stop_process(inst); > +} > + > +static const struct v4l2_m2m_ops wave5_vpu_enc_m2m_ops = { > + .device_run = wave5_vpu_enc_device_run, > + .job_ready = wave5_vpu_enc_job_ready, > + .job_abort = wave5_vpu_enc_job_abort, > +}; > + > +static int wave5_vpu_open_enc(struct file *filp) > +{ > + struct video_device *vdev = video_devdata(filp); > + struct vpu_device *dev = video_drvdata(filp); > + struct vpu_instance *inst = NULL; > + struct v4l2_ctrl_handler *v4l2_ctrl_hdl; > + int ret = 0; > + > + inst = kzalloc(sizeof(*inst), GFP_KERNEL); > + if (!inst) > + return -ENOMEM; > + v4l2_ctrl_hdl = &inst->v4l2_ctrl_hdl; > + > + inst->dev = dev; > + inst->type = VPU_INST_TYPE_ENC; > + inst->ops = &wave5_vpu_enc_inst_ops; > + > + v4l2_fh_init(&inst->v4l2_fh, vdev); > + filp->private_data = &inst->v4l2_fh; > + v4l2_fh_add(&inst->v4l2_fh); > + > + INIT_LIST_HEAD(&inst->list); > + list_add_tail(&inst->list, &dev->instances); > + > + inst->v4l2_m2m_dev = v4l2_m2m_init(&wave5_vpu_enc_m2m_ops); > + if (IS_ERR(inst->v4l2_m2m_dev)) { > + ret = PTR_ERR(inst->v4l2_m2m_dev); > + dev_err(inst->dev->dev, "v4l2_m2m_init, fail: %d\n", ret); > + goto cleanup_inst; > + } > + > + inst->v4l2_fh.m2m_ctx = > + v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_enc_queue_init); > + if (IS_ERR(inst->v4l2_fh.m2m_ctx)) { > + ret = PTR_ERR(inst->v4l2_fh.m2m_ctx); > + goto cleanup_inst; > + } > + > + v4l2_ctrl_handler_init(v4l2_ctrl_hdl, 50); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, > + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, 0, > + V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, > + V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 0, > + V4L2_MPEG_VIDEO_HEVC_LEVEL_1); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP, > + 0, 63, 1, 8); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP, > + 0, 63, 1, 51); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP, > + 0, 63, 1, 30); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE, > + V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, 0, > + V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2, > + -6, 6, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2, > + -6, 6, 1, 0); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE, > + V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR, 0, > + V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD, > + 0, 2047, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING, > + 0, 1, 1, 1); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1, > + 1, 2, 1, 2); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION, > + 0, 1, 1, 1); > + > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_PROFILE, > + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE, 0, > + V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_LEVEL, > + V4L2_MPEG_VIDEO_H264_LEVEL_5_1, 0, > + V4L2_MPEG_VIDEO_H264_LEVEL_1_0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_MIN_QP, > + 0, 63, 1, 8); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_MAX_QP, > + 0, 63, 1, 51); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, > + 0, 63, 1, 30); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE, > + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY, 0, > + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA, > + -6, 6, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA, > + -6, 6, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM, > + 0, 1, 1, 1); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET, > + -12, 12, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_I_PERIOD, > + 0, 2047, 1, 0); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE, > + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, 0, > + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC); > + > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_HFLIP, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_VFLIP, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_ROTATE, > + 0, 270, 90, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_VBV_SIZE, > + 10, 3000, 1, 3000); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_BITRATE_MODE, > + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0, > + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_BITRATE, > + 0, 700000000, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_GOP_SIZE, > + 0, 2047, 1, 0); > + v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE, > + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB, 0, > + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, > + 0, 0xFFFF, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE, > + 0, 1, 1, 0); > + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, > + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1); > + > + if (v4l2_ctrl_hdl->error) { > + ret = -ENODEV; > + goto cleanup_inst; > + } > + > + inst->v4l2_fh.ctrl_handler = v4l2_ctrl_hdl; > + v4l2_ctrl_handler_setup(v4l2_ctrl_hdl); > + > + wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); > + inst->colorspace = V4L2_COLORSPACE_REC709; > + inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; > + inst->hsv_enc = 0; > + inst->quantization = V4L2_QUANTIZATION_DEFAULT; > + inst->xfer_func = V4L2_XFER_FUNC_DEFAULT; > + inst->frame_rate = 30; > + > + init_completion(&inst->irq_done); > + ret = kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL); > + if (ret) { > + dev_err(inst->dev->dev, "Allocating fifo, fail: %d\n", ret); > + goto cleanup_inst; > + } > + > + inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); > + if (inst->id < 0) { > + dev_warn(inst->dev->dev, "Allocating instance ID, fail: %d\n", inst->id); > + ret = inst->id; > + goto cleanup_inst; > + } > + > + return 0; > + > +cleanup_inst: > + wave5_cleanup_instance(inst); > + return ret; > +} > + > +static int wave5_vpu_enc_release(struct file *filp) > +{ > + return wave5_vpu_release_device(filp, wave5_vpu_enc_close, "encoder"); > +} > + > +static const struct v4l2_file_operations wave5_vpu_enc_fops = { > + .owner = THIS_MODULE, > + .open = wave5_vpu_open_enc, > + .release = wave5_vpu_enc_release, > + .unlocked_ioctl = video_ioctl2, > + .poll = v4l2_m2m_fop_poll, > + .mmap = v4l2_m2m_fop_mmap, > +}; > + > +int wave5_vpu_enc_register_device(struct vpu_device *dev) > +{ > + struct video_device *vdev_enc; > + int ret; > + > + vdev_enc = devm_kzalloc(dev->v4l2_dev.dev, sizeof(*vdev_enc), GFP_KERNEL); > + if (!vdev_enc) > + return -ENOMEM; > + > + dev->video_dev_enc = vdev_enc; > + > + strscpy(vdev_enc->name, VPU_ENC_DEV_NAME, sizeof(vdev_enc->name)); > + vdev_enc->fops = &wave5_vpu_enc_fops; > + vdev_enc->ioctl_ops = &wave5_vpu_enc_ioctl_ops; > + vdev_enc->release = video_device_release_empty; > + vdev_enc->v4l2_dev = &dev->v4l2_dev; > + vdev_enc->vfl_dir = VFL_DIR_M2M; > + vdev_enc->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; > + vdev_enc->lock = &dev->dev_lock; > + > + ret = video_register_device(vdev_enc, VFL_TYPE_VIDEO, -1); > + if (ret) > + return ret; > + > + video_set_drvdata(vdev_enc, dev); > + > + return 0; > +} > + > +void wave5_vpu_enc_unregister_device(struct vpu_device *dev) > +{ > + video_unregister_device(dev->video_dev_enc); > +} > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers/media/platform/chips-media/wave5/wave5-vpu.c > new file mode 100644 > index 000000000000..9c602168cffc > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c > @@ -0,0 +1,362 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) > +/* > + * Wave5 series multi-standard codec IP - platform driver > + * > + * Copyright (C) 2021 CHIPS&MEDIA INC > + */ > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/clk.h> > +#include <linux/of_address.h> > +#include <linux/firmware.h> > +#include <linux/interrupt.h> > +#include "wave5-vpu.h" > +#include "wave5-regdefine.h" > +#include "wave5-vpuconfig.h" > +#include "wave5.h" > + > +#define VPU_PLATFORM_DEVICE_NAME "vdec" > +#define VPU_CLK_NAME "vcodec" > + > +#define WAVE5_IS_ENC BIT(0) > +#define WAVE5_IS_DEC BIT(1) > + > +struct wave5_match_data { > + int flags; > + const char *fw_name; > +}; > + > +int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout) > +{ > + int ret; > + > + ret = wait_for_completion_timeout(&inst->irq_done, > + msecs_to_jiffies(timeout)); > + if (!ret) > + return -ETIMEDOUT; > + > + reinit_completion(&inst->irq_done); > + > + return 0; > +} > + > +static void wave5_vpu_get_interrupt_for_inst(struct vpu_instance *inst, u32 status) > +{ > + struct vpu_device *dev = inst->dev; > + u32 seq_done; > + u32 cmd_done; > + int val; > + > + seq_done = wave5_vdi_readl(dev, W5_RET_SEQ_DONE_INSTANCE_INFO); > + cmd_done = wave5_vdi_readl(dev, W5_RET_QUEUE_CMD_DONE_INST); > + > + if (status & BIT(INT_WAVE5_INIT_SEQ)) { > + if (seq_done & BIT(inst->id)) { > + seq_done &= ~BIT(inst->id); > + wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done); > + val = BIT(INT_WAVE5_INIT_SEQ); > + kfifo_in(&inst->irq_status, &val, sizeof(int)); > + } > + } > + if (status & BIT(INT_WAVE5_ENC_SET_PARAM)) { > + if (seq_done & BIT(inst->id)) { > + seq_done &= ~BIT(inst->id); > + wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done); > + val = BIT(INT_WAVE5_ENC_SET_PARAM); > + kfifo_in(&inst->irq_status, &val, sizeof(int)); > + } > + } > + if (status & BIT(INT_WAVE5_DEC_PIC) || > + status & BIT(INT_WAVE5_ENC_PIC)) { > + if (cmd_done & BIT(inst->id)) { > + cmd_done &= ~BIT(inst->id); > + wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST, cmd_done); > + val = BIT(INT_WAVE5_DEC_PIC); > + kfifo_in(&inst->irq_status, &val, sizeof(int)); > + } > + } > +} > + > +static irqreturn_t wave5_vpu_irq(int irq, void *dev_id) > +{ > + struct vpu_device *dev = dev_id; > + > + if (wave5_vdi_readl(dev, W5_VPU_VPU_INT_STS)) { > + struct vpu_instance *inst; > + u32 irq_status = wave5_vdi_readl(dev, W5_VPU_VINT_REASON); > + > + list_for_each_entry(inst, &dev->instances, list) { > + wave5_vpu_get_interrupt_for_inst(inst, irq_status); > + } > + > + wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_status); > + wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1); > + > + return IRQ_WAKE_THREAD; > + } > + > + return IRQ_HANDLED; > +} > + > +static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id) > +{ > + struct vpu_device *dev = dev_id; > + struct vpu_instance *inst; > + int irq_status, ret; > + u32 val; > + > + list_for_each_entry(inst, &dev->instances, list) { > + while (kfifo_len(&inst->irq_status)) { > + struct vpu_instance *curr; > + > + curr = v4l2_m2m_get_curr_priv(inst->v4l2_m2m_dev); > + if (curr) { > + inst->ops->finish_process(inst); > + } else { > + ret = kfifo_out(&inst->irq_status, &irq_status, sizeof(int)); > + if (!ret) > + break; > + > + val = wave5_vdi_readl(dev, W5_VPU_VINT_REASON_USR); > + val &= ~irq_status; > + wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_USR, val); > + complete(&inst->irq_done); > + } > + } > + } > + > + return IRQ_HANDLED; > +} > + > +static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name) > +{ > + const struct firmware *fw; > + int ret; > + u32 revision; > + unsigned int product_id; > + > + ret = request_firmware(&fw, fw_name, dev); > + if (ret) { > + dev_err(dev, "request_firmware, fail: %d\n", ret); > + return ret; > + } > + > + ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw->data, fw->size); > + if (ret) { > + dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret); > + goto release_fw; > + } > + release_firmware(fw); > + > + ret = wave5_vpu_get_version_info(dev, &revision, &product_id); > + if (ret) { > + dev_err(dev, "vpu_get_version_info fail: %d\n", ret); > + goto err_without_release; > + } > + > + dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n", > + __func__, product_id, revision); > + > + return 0; > + > +release_fw: > + release_firmware(fw); > +err_without_release: > + return ret; > +} > + > +static int wave5_vpu_probe(struct platform_device *pdev) > +{ > + int ret; > + struct vpu_device *dev; > + struct device_node *np; > + const struct wave5_match_data *match_data; > + struct resource sram; > + > + match_data = device_get_match_data(&pdev->dev); > + if (!match_data) { > + dev_err(&pdev->dev, "missing device match data\n"); > + return -EINVAL; > + } > + > + /* physical addresses limited to 32 bits */ > + dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); > + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); > + > + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); > + if (!dev) > + return -ENOMEM; > + > + dev->vdb_register = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(dev->vdb_register)) > + return PTR_ERR(dev->vdb_register); > + ida_init(&dev->inst_ida); > + > + mutex_init(&dev->dev_lock); > + mutex_init(&dev->hw_lock); > + dev_set_drvdata(&pdev->dev, dev); > + dev->dev = &pdev->dev; > + > + ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks); > + > + /* continue without clock, assume externally managed */ > + if (ret < 0) { > + dev_warn(&pdev->dev, "Getting clocks, fail: %d\n", ret); > + ret = 0; > + } > + dev->num_clks = ret; > + > + ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks); > + if (ret) { > + dev_err(&pdev->dev, "Enabling clocks, fail: %d\n", ret); > + return ret; > + } > + > + np = of_parse_phandle(pdev->dev.of_node, "sram", 0); > + if (!np) { > + dev_warn(&pdev->dev, "sram node not found\n"); > + } else { > + ret = of_address_to_resource(np, 0, &sram); > + if (ret) { > + dev_err(&pdev->dev, "sram resource not available\n"); > + goto err_put_node; > + } > + dev->sram_buf.daddr = sram.start; > + dev->sram_buf.size = resource_size(&sram); > + dev_dbg(&pdev->dev, "%s: sram daddr: %pad, size: 0x%lx\n", > + __func__, &dev->sram_buf.daddr, dev->sram_buf.size); > + } > + > + dev->product_code = wave5_vdi_readl(dev, VPU_PRODUCT_CODE_REGISTER); > + ret = wave5_vdi_init(&pdev->dev); > + if (ret < 0) { > + dev_err(&pdev->dev, "wave5_vdi_init, fail: %d\n", ret); > + goto err_clk_dis; > + } > + dev->product = wave5_vpu_get_product_id(dev); > + > + INIT_LIST_HEAD(&dev->instances); > + ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); > + if (ret) { > + dev_err(&pdev->dev, "v4l2_device_register, fail: %d\n", ret); > + goto err_vdi_release; > + } > + > + if (match_data->flags & WAVE5_IS_DEC) { > + ret = wave5_vpu_dec_register_device(dev); > + if (ret) { > + dev_err(&pdev->dev, "wave5_vpu_dec_register_device, fail: %d\n", ret); > + goto err_v4l2_unregister; > + } > + } > + if (match_data->flags & WAVE5_IS_ENC) { > + ret = wave5_vpu_enc_register_device(dev); > + if (ret) { > + dev_err(&pdev->dev, "wave5_vpu_enc_register_device, fail: %d\n", ret); > + goto err_dec_unreg; > + } > + } > + > + dev->irq = platform_get_irq(pdev, 0); > + if (dev->irq < 0) { > + dev_err(&pdev->dev, "failed to get irq resource\n"); > + ret = -ENXIO; > + goto err_enc_unreg; > + } > + > + ret = devm_request_threaded_irq(&pdev->dev, dev->irq, wave5_vpu_irq, > + wave5_vpu_irq_thread, 0, "vpu_irq", dev); > + if (ret) { > + dev_err(&pdev->dev, "Register interrupt handler, fail: %d\n", ret); > + goto err_enc_unreg; > + } > + > + ret = wave5_vpu_load_firmware(&pdev->dev, match_data->fw_name); > + if (ret) { > + dev_err(&pdev->dev, "wave5_vpu_load_firmware, fail: %d\n", ret); > + goto err_enc_unreg; > + } > + > + dev_dbg(&pdev->dev, "Added wave5 driver with caps: %s %s and product code: 0x%x\n", > + (match_data->flags & WAVE5_IS_ENC) ? "'ENCODE'" : "", > + (match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : "", > + dev->product_code); > + return 0; > + > +err_enc_unreg: > + if (match_data->flags & WAVE5_IS_ENC) > + wave5_vpu_enc_unregister_device(dev); > +err_dec_unreg: > + if (match_data->flags & WAVE5_IS_DEC) > + wave5_vpu_dec_unregister_device(dev); > +err_v4l2_unregister: > + v4l2_device_unregister(&dev->v4l2_dev); > +err_vdi_release: > + wave5_vdi_release(&pdev->dev); > +err_clk_dis: > + clk_bulk_disable_unprepare(dev->num_clks, dev->clks); > +err_put_node: > + of_node_put(np); > + > + return ret; > +} > + > +static int wave5_vpu_remove(struct platform_device *pdev) > +{ > + struct vpu_device *dev = dev_get_drvdata(&pdev->dev); > + > + clk_bulk_disable_unprepare(dev->num_clks, dev->clks); > + wave5_vpu_enc_unregister_device(dev); > + wave5_vpu_dec_unregister_device(dev); > + v4l2_device_unregister(&dev->v4l2_dev); > + wave5_vdi_release(&pdev->dev); > + ida_destroy(&dev->inst_ida); > + > + return 0; > +} > + > +static const struct wave5_match_data wave511_data = { > + .flags = WAVE5_IS_DEC, > + .fw_name = "wave511_dec_fw.bin", > +}; > + > +static const struct wave5_match_data wave521_data = { > + .flags = WAVE5_IS_ENC, > + .fw_name = "wave521_enc_fw.bin", > +}; > + > +static const struct wave5_match_data wave521c_data = { > + .flags = WAVE5_IS_ENC | WAVE5_IS_DEC, > + .fw_name = "wave521c_codec_fw.bin", > +}; > + > +static const struct wave5_match_data default_match_data = { > + .flags = WAVE5_IS_ENC | WAVE5_IS_DEC, > + .fw_name = "chagall.bin", > +}; > + > +static const struct of_device_id wave5_dt_ids[] = { > + { .compatible = "cnm,cm511-vpu", .data = &wave511_data }, > + { .compatible = "cnm,cm517-vpu", .data = &default_match_data }, > + { .compatible = "cnm,cm521-vpu", .data = &wave521_data }, > + { .compatible = "cnm,cm521c-vpu", .data = &wave521c_data }, > + { .compatible = "cnm,cm521c-dual-vpu", .data = &wave521c_data }, > + { .compatible = "cnm,cm521e1-vpu", .data = &default_match_data }, > + { .compatible = "cnm,cm537-vpu", .data = &default_match_data }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, wave5_dt_ids); > + > +static struct platform_driver wave5_vpu_driver = { > + .driver = { > + .name = VPU_PLATFORM_DEVICE_NAME, > + .of_match_table = of_match_ptr(wave5_dt_ids), > + }, > + .probe = wave5_vpu_probe, > + .remove = wave5_vpu_remove, > +}; > + > +module_platform_driver(wave5_vpu_driver); > +MODULE_DESCRIPTION("chips&media VPU V4L2 driver"); > +MODULE_LICENSE("Dual BSD/GPL"); > diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.h b/drivers/media/platform/chips-media/wave5/wave5-vpu.h > new file mode 100644 > index 000000000000..7156d8c3fee4 > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.h > @@ -0,0 +1,72 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ > +/* > + * Wave5 series multi-standard codec IP - basic types > + * > + * Copyright (C) 2021 CHIPS&MEDIA INC > + */ > +#ifndef __VPU_DRV_H__ > +#define __VPU_DRV_H__ > + > +#include <media/v4l2-ctrls.h> > +#include <media/v4l2-ioctl.h> > +#include <media/v4l2-event.h> > +#include <media/v4l2-fh.h> > +#include <media/videobuf2-v4l2.h> > +#include <media/videobuf2-dma-contig.h> > +#include <media/videobuf2-vmalloc.h> > +#include "wave5-vpuconfig.h" > +#include "wave5-vpuapi.h" > + > +#define VPU_BUF_SYNC_TO_DEVICE 0 > +#define VPU_BUF_SYNC_FROM_DEVICE 1 > + > +struct vpu_buffer { > + struct v4l2_m2m_buffer v4l2_m2m_buf; > + bool consumed; > +}; > + > +enum vpu_fmt_type { > + VPU_FMT_TYPE_CODEC = 0, > + VPU_FMT_TYPE_RAW = 1 > +}; > + > +struct vpu_format { > + unsigned int v4l2_pix_fmt; > + unsigned int max_width; > + unsigned int min_width; > + unsigned int max_height; > + unsigned int min_height; > +}; > + > +static inline struct vpu_instance *wave5_to_vpu_inst(struct v4l2_fh *vfh) > +{ > + return container_of(vfh, struct vpu_instance, v4l2_fh); > +} > + > +static inline struct vpu_instance *wave5_ctrl_to_vpu_inst(struct v4l2_ctrl *vctrl) > +{ > + return container_of(vctrl->handler, struct vpu_instance, v4l2_ctrl_hdl); > +} > + > +static inline struct vpu_buffer *wave5_to_vpu_buf(struct vb2_v4l2_buffer *vbuf) > +{ > + return container_of(vbuf, struct vpu_buffer, v4l2_m2m_buf.vb); > +} > + > +int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout); > + > +int wave5_vpu_dec_register_device(struct vpu_device *dev); > +void wave5_vpu_dec_unregister_device(struct vpu_device *dev); > +int wave5_vpu_enc_register_device(struct vpu_device *dev); > +void wave5_vpu_enc_unregister_device(struct vpu_device *dev); > +static inline bool wave5_vpu_both_queues_are_streaming(struct vpu_instance *inst) > +{ > + struct vb2_queue *vq_cap = > + v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); > + struct vb2_queue *vq_out = > + v4l2_m2m_get_vq(inst->v4l2_fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); > + > + return vb2_is_streaming(vq_cap) && vb2_is_streaming(vq_out); > +} > + > +#endif ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v11 4/6] media: chips-media: wave5: Add TODO file [not found] <20221207121350.66217-1-sebastian.fricke@collabora.com> ` (2 preceding siblings ...) 2022-12-07 12:13 ` [PATCH v11 3/6] media: chips-media: wave5: Add the v4l2 layer Sebastian Fricke @ 2022-12-07 12:13 ` Sebastian Fricke 2022-12-12 14:30 ` Hans Verkuil 2022-12-07 12:13 ` [PATCH v11 5/6] dt-bindings: media: wave5: add yaml devicetree bindings Sebastian Fricke 2022-12-07 12:13 ` [PATCH v11 6/6] media: chips-media: wave5: Add wave5 driver to maintainers file Sebastian Fricke 5 siblings, 1 reply; 22+ messages in thread From: Sebastian Fricke @ 2022-12-07 12:13 UTC (permalink / raw) To: linux-media, Nas Chung, Robert Beckett, Sebastian Fricke, Mauro Carvalho Chehab Cc: kernel, hverkuil-cisco, nicolas.dufresne, linux-kernel From: Nas Chung <nas.chung@chipsnmedia.com> Add a TODO file with remaining elements to be improved/added. Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com> --- drivers/media/platform/chips-media/wave5/TODO | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 drivers/media/platform/chips-media/wave5/TODO diff --git a/drivers/media/platform/chips-media/wave5/TODO b/drivers/media/platform/chips-media/wave5/TODO new file mode 100644 index 000000000000..2164fd071a56 --- /dev/null +++ b/drivers/media/platform/chips-media/wave5/TODO @@ -0,0 +1,18 @@ +* Handle interrupts better + +Currently the interrupt handling uses an unusual design employing a kfifo to +transfer irq status to irq thread. This was done as a work around for dropped +interrupts seen with IRQF_ONESHOT based handling. + +This needs further investigation and fixing properly, with the aid of +C&M. + +* power management handling - add (runtime_)suspen/resume cb where the clock is enabled + +* revise logic of wave5_vpu_(dec/enc)_register_framebuffer + +* check if the normal kernel endianness/__swab32 routines are sufficient. (instead of the ones + implemented in the driver) + +* Adjust STREAMON routine for the stateful decoder to adhere to the API, which + declares that STREAMON can be called before source buffers have been queued. -- 2.25.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v11 4/6] media: chips-media: wave5: Add TODO file 2022-12-07 12:13 ` [PATCH v11 4/6] media: chips-media: wave5: Add TODO file Sebastian Fricke @ 2022-12-12 14:30 ` Hans Verkuil 0 siblings, 0 replies; 22+ messages in thread From: Hans Verkuil @ 2022-12-12 14:30 UTC (permalink / raw) To: Sebastian Fricke, linux-media, Nas Chung, Robert Beckett, Mauro Carvalho Chehab Cc: kernel, nicolas.dufresne, linux-kernel On 07/12/2022 13:13, Sebastian Fricke wrote: > From: Nas Chung <nas.chung@chipsnmedia.com> > > Add a TODO file with remaining elements to be improved/added. > > Signed-off-by: Robert Beckett <bob.beckett@collabora.com> > Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> > Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> > Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com> > --- > drivers/media/platform/chips-media/wave5/TODO | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > create mode 100644 drivers/media/platform/chips-media/wave5/TODO > > diff --git a/drivers/media/platform/chips-media/wave5/TODO b/drivers/media/platform/chips-media/wave5/TODO > new file mode 100644 > index 000000000000..2164fd071a56 > --- /dev/null > +++ b/drivers/media/platform/chips-media/wave5/TODO > @@ -0,0 +1,18 @@ > +* Handle interrupts better > + > +Currently the interrupt handling uses an unusual design employing a kfifo to > +transfer irq status to irq thread. This was done as a work around for dropped > +interrupts seen with IRQF_ONESHOT based handling. > + > +This needs further investigation and fixing properly, with the aid of > +C&M. > + > +* power management handling - add (runtime_)suspen/resume cb where the clock is enabled > + > +* revise logic of wave5_vpu_(dec/enc)_register_framebuffer > + > +* check if the normal kernel endianness/__swab32 routines are sufficient. (instead of the ones > + implemented in the driver) > + > +* Adjust STREAMON routine for the stateful decoder to adhere to the API, which > + declares that STREAMON can be called before source buffers have been queued. A TODO file doesn't belong in a non-staging driver. So either it should remain in staging if this is serious enough (and I'm a bit worried about the last item here!), or it should be documented in comments in the driver in the appropriate places. Note that the "revise logic" item doesn't explain the reason why that should be done. Regards, Hans ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v11 5/6] dt-bindings: media: wave5: add yaml devicetree bindings [not found] <20221207121350.66217-1-sebastian.fricke@collabora.com> ` (3 preceding siblings ...) 2022-12-07 12:13 ` [PATCH v11 4/6] media: chips-media: wave5: Add TODO file Sebastian Fricke @ 2022-12-07 12:13 ` Sebastian Fricke 2022-12-07 12:31 ` Krzysztof Kozlowski 2022-12-07 12:13 ` [PATCH v11 6/6] media: chips-media: wave5: Add wave5 driver to maintainers file Sebastian Fricke 5 siblings, 1 reply; 22+ messages in thread From: Sebastian Fricke @ 2022-12-07 12:13 UTC (permalink / raw) To: linux-media, Rob Herring, Krzysztof Kozlowski Cc: kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, Sebastian Fricke, devicetree, linux-kernel From: Robert Beckett <bob.beckett@collabora.com> Add bindings for the wave5 chips&media codec driver Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> --- .../devicetree/bindings/cnm,wave5.yml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/cnm,wave5.yml diff --git a/Documentation/devicetree/bindings/cnm,wave5.yml b/Documentation/devicetree/bindings/cnm,wave5.yml new file mode 100644 index 000000000000..01dddebb162e --- /dev/null +++ b/Documentation/devicetree/bindings/cnm,wave5.yml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/wave5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Chips&Media Wave 5 Series multi-standard codec IP + +maintainers: + - Nas Chung <nas.chung@chipsnmedia.com> + - Robert Beckett <bob.beckett@collabora.com> + - Sebastian Fricke <sebastian.fricke@collabora.com> + +description: |- + The Chips&Media WAVE codec IP is a multi format video encoder/decoder + +properties: + compatible: + anyOf: + - items: + - enum: + - cnm,cm511-vpu + - cnm,cm517-vpu + - cnm,cm521-vpu + - cnm,cm521c-vpu + - cnm,cm521c-dual-vpu + - cnm,cm521e1-vpu + - cnm,cm537-vpu + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle pointing to the SRAM device node + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + vpu: video-codec@12345678 { + compatible = "cnm,cm521-vpu"; + reg = <0x12345678 0x1000>; + interrupts = <42>; + clocks = <&clks 42>; + clock-names = "vcodec"; + sram = <&sram>; + }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v11 5/6] dt-bindings: media: wave5: add yaml devicetree bindings 2022-12-07 12:13 ` [PATCH v11 5/6] dt-bindings: media: wave5: add yaml devicetree bindings Sebastian Fricke @ 2022-12-07 12:31 ` Krzysztof Kozlowski 2022-12-07 13:17 ` Krzysztof Kozlowski ` (2 more replies) 0 siblings, 3 replies; 22+ messages in thread From: Krzysztof Kozlowski @ 2022-12-07 12:31 UTC (permalink / raw) To: Sebastian Fricke, linux-media, Rob Herring, Krzysztof Kozlowski Cc: kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, devicetree, linux-kernel On 07/12/2022 13:13, Sebastian Fricke wrote: > From: Robert Beckett <bob.beckett@collabora.com> > > Add bindings for the wave5 chips&media codec driver > > Signed-off-by: Robert Beckett <bob.beckett@collabora.com> > Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> > Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> What's happening with this patch? Where is the changelog? Why it is v11 and first time I see it? And why it is v11 with basic mistakes and lack of testing?!? I would assume that v11 was already seen and tested... > --- > .../devicetree/bindings/cnm,wave5.yml | 72 +++++++++++++++++++ > 1 file changed, 72 insertions(+) > create mode 100644 Documentation/devicetree/bindings/cnm,wave5.yml Wrong directory. It wasn't here at all before, so I am really confused how this could happen. Subject: drop redundant pieces: yaml, devicetree and bindings. > > diff --git a/Documentation/devicetree/bindings/cnm,wave5.yml b/Documentation/devicetree/bindings/cnm,wave5.yml > new file mode 100644 > index 000000000000..01dddebb162e > --- /dev/null > +++ b/Documentation/devicetree/bindings/cnm,wave5.yml > @@ -0,0 +1,72 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/wave5.yaml# You clearly did not test them before sending. > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Chips&Media Wave 5 Series multi-standard codec IP > + > +maintainers: > + - Nas Chung <nas.chung@chipsnmedia.com> > + - Robert Beckett <bob.beckett@collabora.com> > + - Sebastian Fricke <sebastian.fricke@collabora.com> > + > +description: |- > + The Chips&Media WAVE codec IP is a multi format video encoder/decoder > + > +properties: > + compatible: > + anyOf: Please start from example-schema or other recently approved bindings. No anyOf. > + - items: No items... > + - enum: > + - cnm,cm511-vpu > + - cnm,cm517-vpu > + - cnm,cm521-vpu > + - cnm,cm521c-vpu > + - cnm,cm521c-dual-vpu What's the difference between this and one above? > + - cnm,cm521e1-vpu > + - cnm,cm537-vpu > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + maxItems: 4 This has to be specific. > + > + clock-names: > + minItems: 1 > + maxItems: 4 You need to list the names. > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > + sram: Missing vendor prefix. > + $ref: /schemas/types.yaml#/definitions/phandle > + description: phandle pointing to the SRAM device node And what is it for? Why do you need SRAM? > + maxItems: 1 Drop > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + vpu: video-codec@12345678 { > + compatible = "cnm,cm521-vpu"; > + reg = <0x12345678 0x1000>; > + interrupts = <42>; > + clocks = <&clks 42>; > + clock-names = "vcodec"; > + sram = <&sram>; > + }; Best regards, Krzysztof ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v11 5/6] dt-bindings: media: wave5: add yaml devicetree bindings 2022-12-07 12:31 ` Krzysztof Kozlowski @ 2022-12-07 13:17 ` Krzysztof Kozlowski 2022-12-07 15:09 ` Sebastian Fricke 2023-09-04 6:25 ` Sebastian Fricke 2 siblings, 0 replies; 22+ messages in thread From: Krzysztof Kozlowski @ 2022-12-07 13:17 UTC (permalink / raw) To: Sebastian Fricke, linux-media, Rob Herring, Krzysztof Kozlowski Cc: kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, devicetree, linux-kernel On 07/12/2022 13:31, Krzysztof Kozlowski wrote: > On 07/12/2022 13:13, Sebastian Fricke wrote: >> From: Robert Beckett <bob.beckett@collabora.com> >> >> Add bindings for the wave5 chips&media codec driver >> >> Signed-off-by: Robert Beckett <bob.beckett@collabora.com> >> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> >> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> > > What's happening with this patch? Where is the changelog? Why it is v11 > and first time I see it? And why it is v11 with basic mistakes and lack > of testing?!? I would assume that v11 was already seen and tested... > > >> --- >> .../devicetree/bindings/cnm,wave5.yml | 72 +++++++++++++++++++ >> 1 file changed, 72 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/cnm,wave5.yml > > Wrong directory. It wasn't here at all before, so I am really confused > how this could happen. > > Subject: drop redundant pieces: yaml, devicetree and bindings. > > >> >> diff --git a/Documentation/devicetree/bindings/cnm,wave5.yml b/Documentation/devicetree/bindings/cnm,wave5.yml >> new file mode 100644 >> index 000000000000..01dddebb162e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/cnm,wave5.yml >> @@ -0,0 +1,72 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/media/wave5.yaml# > > You clearly did not test them before sending. > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Chips&Media Wave 5 Series multi-standard codec IP >> + >> +maintainers: >> + - Nas Chung <nas.chung@chipsnmedia.com> >> + - Robert Beckett <bob.beckett@collabora.com> >> + - Sebastian Fricke <sebastian.fricke@collabora.com> >> + >> +description: |- >> + The Chips&Media WAVE codec IP is a multi format video encoder/decoder >> + >> +properties: >> + compatible: >> + anyOf: > > Please start from example-schema or other recently approved bindings. No > anyOf. > >> + - items: > > No items... > >> + - enum: >> + - cnm,cm511-vpu >> + - cnm,cm517-vpu >> + - cnm,cm521-vpu >> + - cnm,cm521c-vpu >> + - cnm,cm521c-dual-vpu > > What's the difference between this and one above? > >> + - cnm,cm521e1-vpu >> + - cnm,cm537-vpu One more question - why "vpu" suffixes? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v11 5/6] dt-bindings: media: wave5: add yaml devicetree bindings 2022-12-07 12:31 ` Krzysztof Kozlowski 2022-12-07 13:17 ` Krzysztof Kozlowski @ 2022-12-07 15:09 ` Sebastian Fricke 2022-12-07 15:27 ` Krzysztof Kozlowski 2023-09-04 6:25 ` Sebastian Fricke 2 siblings, 1 reply; 22+ messages in thread From: Sebastian Fricke @ 2022-12-07 15:09 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: linux-media, Rob Herring, Krzysztof Kozlowski, kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, devicetree, linux-kernel Hello Krzysztof, On 07.12.2022 13:31, Krzysztof Kozlowski wrote: >On 07/12/2022 13:13, Sebastian Fricke wrote: >> From: Robert Beckett <bob.beckett@collabora.com> >> >> Add bindings for the wave5 chips&media codec driver >> >> Signed-off-by: Robert Beckett <bob.beckett@collabora.com> >> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> >> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> > >What's happening with this patch? Where is the changelog? The changelog is located in the cover letter. https://lore.kernel.org/linux-media/20221207121350.66217-1-sebastian.fricke@collabora.com/ >Why it is v11 and first time I see it? You actually replied to V10: https://lore.kernel.org/linux-media/20221023085341.s23qinjuw4qls3dn@basti-XPS-13-9310/ >And why it is v11 with basic mistakes and lack of testing?!? >I would assume that v11 was already seen and tested... Sorry I don't have a lot of experience with dt-bindings, thank you for highlighting the issues, I will correct them. And I forgot to build the documentation during my testing runs. I took over the patch set from another contributor and as no one complained about the dt-bindings for the last 10 versions, I concentrated my energy on other problems. > > >> --- >> .../devicetree/bindings/cnm,wave5.yml | 72 +++++++++++++++++++ >> 1 file changed, 72 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/cnm,wave5.yml > >Wrong directory. It wasn't here at all before, so I am really confused >how this could happen. Thanks for the highlight. I will move it to: Documentation/devicetree/bindings/media/cnm,wave5.yml > >Subject: drop redundant pieces: yaml, devicetree and bindings. I call it: dt-bindings: media: chips-media: add wave5 bindings in V12 Sincerely, Sebastian Fricke > > >> >> diff --git a/Documentation/devicetree/bindings/cnm,wave5.yml b/Documentation/devicetree/bindings/cnm,wave5.yml >> new file mode 100644 >> index 000000000000..01dddebb162e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/cnm,wave5.yml >> @@ -0,0 +1,72 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/media/wave5.yaml# > >You clearly did not test them before sending. > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Chips&Media Wave 5 Series multi-standard codec IP >> + >> +maintainers: >> + - Nas Chung <nas.chung@chipsnmedia.com> >> + - Robert Beckett <bob.beckett@collabora.com> >> + - Sebastian Fricke <sebastian.fricke@collabora.com> >> + >> +description: |- >> + The Chips&Media WAVE codec IP is a multi format video encoder/decoder >> + >> +properties: >> + compatible: >> + anyOf: > >Please start from example-schema or other recently approved bindings. No >anyOf. > >> + - items: > >No items... > >> + - enum: >> + - cnm,cm511-vpu >> + - cnm,cm517-vpu >> + - cnm,cm521-vpu >> + - cnm,cm521c-vpu >> + - cnm,cm521c-dual-vpu > >What's the difference between this and one above? > >> + - cnm,cm521e1-vpu >> + - cnm,cm537-vpu >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + minItems: 1 >> + maxItems: 4 > >This has to be specific. > >> + >> + clock-names: >> + minItems: 1 >> + maxItems: 4 > >You need to list the names. > >> + >> + interrupts: >> + maxItems: 1 >> + >> + power-domains: >> + maxItems: 1 >> + >> + resets: >> + maxItems: 1 >> + >> + sram: > >Missing vendor prefix. > >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: phandle pointing to the SRAM device node > >And what is it for? Why do you need SRAM? > >> + maxItems: 1 > >Drop > >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - clocks >> + - clock-names >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + vpu: video-codec@12345678 { >> + compatible = "cnm,cm521-vpu"; >> + reg = <0x12345678 0x1000>; >> + interrupts = <42>; >> + clocks = <&clks 42>; >> + clock-names = "vcodec"; >> + sram = <&sram>; >> + }; > >Best regards, >Krzysztof > ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v11 5/6] dt-bindings: media: wave5: add yaml devicetree bindings 2022-12-07 15:09 ` Sebastian Fricke @ 2022-12-07 15:27 ` Krzysztof Kozlowski 2022-12-12 11:32 ` Sebastian Fricke 0 siblings, 1 reply; 22+ messages in thread From: Krzysztof Kozlowski @ 2022-12-07 15:27 UTC (permalink / raw) To: Sebastian Fricke Cc: linux-media, Rob Herring, Krzysztof Kozlowski, kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, devicetree, linux-kernel On 07/12/2022 16:09, Sebastian Fricke wrote: > Hello Krzysztof, > > On 07.12.2022 13:31, Krzysztof Kozlowski wrote: >> On 07/12/2022 13:13, Sebastian Fricke wrote: >>> From: Robert Beckett <bob.beckett@collabora.com> >>> >>> Add bindings for the wave5 chips&media codec driver >>> >>> Signed-off-by: Robert Beckett <bob.beckett@collabora.com> >>> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> >>> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> >> >> What's happening with this patch? Where is the changelog? > > The changelog is located in the cover letter. > https://lore.kernel.org/linux-media/20221207121350.66217-1-sebastian.fricke@collabora.com/ Which you did not sent to us... so? How does it help us? > >> Why it is v11 and first time I see it? > > You actually replied to V10: > https://lore.kernel.org/linux-media/20221023085341.s23qinjuw4qls3dn@basti-XPS-13-9310/ > >> And why it is v11 with basic mistakes and lack of testing?!? >> I would assume that v11 was already seen and tested... > > Sorry I don't have a lot of experience with dt-bindings, thank you for > highlighting the issues, I will correct them. And I forgot to build the > documentation during my testing runs. > I took over the patch set from another contributor and as no one > complained about the dt-bindings for the last 10 versions, I concentrated > my energy on other problems. Because they were never sent to maintainers... > >> >> >>> --- >>> .../devicetree/bindings/cnm,wave5.yml | 72 +++++++++++++++++++ >>> 1 file changed, 72 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/cnm,wave5.yml >> >> Wrong directory. It wasn't here at all before, so I am really confused >> how this could happen. > > Thanks for the highlight. > > I will move it to: > Documentation/devicetree/bindings/media/cnm,wave5.yml > >> >> Subject: drop redundant pieces: yaml, devicetree and bindings. > > I call it: > > dt-bindings: media: chips-media: add wave5 bindings > > in V12 > > Sincerely, > Sebastian Fricke And the rest questions? Lack of response means agreement, which is fine, so in v12 questionable parts will be removed? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v11 5/6] dt-bindings: media: wave5: add yaml devicetree bindings 2022-12-07 15:27 ` Krzysztof Kozlowski @ 2022-12-12 11:32 ` Sebastian Fricke 0 siblings, 0 replies; 22+ messages in thread From: Sebastian Fricke @ 2022-12-12 11:32 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: linux-media, Rob Herring, Krzysztof Kozlowski, kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, devicetree, linux-kernel Hey Krzysztof, On 07.12.2022 16:27, Krzysztof Kozlowski wrote: >On 07/12/2022 16:09, Sebastian Fricke wrote: >> Hello Krzysztof, >> >> On 07.12.2022 13:31, Krzysztof Kozlowski wrote: >>> On 07/12/2022 13:13, Sebastian Fricke wrote: >>>> From: Robert Beckett <bob.beckett@collabora.com> >>>> >>>> Add bindings for the wave5 chips&media codec driver >>>> >>>> Signed-off-by: Robert Beckett <bob.beckett@collabora.com> >>>> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> >>>> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> >>> >>> What's happening with this patch? Where is the changelog? >> >> The changelog is located in the cover letter. >> https://lore.kernel.org/linux-media/20221207121350.66217-1-sebastian.fricke@collabora.com/ > > >Which you did not sent to us... so? How does it help us? I completely agree, I simply forgot to add the devicetree@vger.kernel.org mail to the list of receivers. > >> >>> Why it is v11 and first time I see it? >> >> You actually replied to V10: >> https://lore.kernel.org/linux-media/20221023085341.s23qinjuw4qls3dn@basti-XPS-13-9310/ >> >>> And why it is v11 with basic mistakes and lack of testing?!? >>> I would assume that v11 was already seen and tested... >> >> Sorry I don't have a lot of experience with dt-bindings, thank you for >> highlighting the issues, I will correct them. And I forgot to build the >> documentation during my testing runs. >> I took over the patch set from another contributor and as no one >> complained about the dt-bindings for the last 10 versions, I concentrated >> my energy on other problems. > >Because they were never sent to maintainers... > >> >>> >>> >>>> --- >>>> .../devicetree/bindings/cnm,wave5.yml | 72 +++++++++++++++++++ >>>> 1 file changed, 72 insertions(+) >>>> create mode 100644 Documentation/devicetree/bindings/cnm,wave5.yml >>> >>> Wrong directory. It wasn't here at all before, so I am really confused >>> how this could happen. >> >> Thanks for the highlight. >> >> I will move it to: >> Documentation/devicetree/bindings/media/cnm,wave5.yml >> >>> >>> Subject: drop redundant pieces: yaml, devicetree and bindings. >> >> I call it: >> >> dt-bindings: media: chips-media: add wave5 bindings >> >> in V12 >> >And the rest questions? Lack of response means agreement, which is fine, >so in v12 questionable parts will be removed? Yes, I will completely rework this part, thus I try to take all of your highlights into consideration. > >Best regards, >Krzysztof Sincerely, Sebastian Fricke ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v11 5/6] dt-bindings: media: wave5: add yaml devicetree bindings 2022-12-07 12:31 ` Krzysztof Kozlowski 2022-12-07 13:17 ` Krzysztof Kozlowski 2022-12-07 15:09 ` Sebastian Fricke @ 2023-09-04 6:25 ` Sebastian Fricke 2023-09-04 7:53 ` Krzysztof Kozlowski 2 siblings, 1 reply; 22+ messages in thread From: Sebastian Fricke @ 2023-09-04 6:25 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: linux-media, Rob Herring, kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, devicetree, linux-kernel Hey Krzysztof, sorry for digging this mail out of the tombs. We have worked for quite a while on a new version of the driver and we are currently finishing it up. I have a few questions before I can finish the patchset. Please see below... On 07.12.2022 13:31, Krzysztof Kozlowski wrote: >On 07/12/2022 13:13, Sebastian Fricke wrote: >> From: Robert Beckett <bob.beckett@collabora.com> >> >> Add bindings for the wave5 chips&media codec driver >> >> Signed-off-by: Robert Beckett <bob.beckett@collabora.com> >> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> >> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> > >What's happening with this patch? Where is the changelog? Why it is v11 >and first time I see it? And why it is v11 with basic mistakes and lack >of testing?!? I would assume that v11 was already seen and tested... > > >> --- >> .../devicetree/bindings/cnm,wave5.yml | 72 +++++++++++++++++++ >> 1 file changed, 72 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/cnm,wave5.yml > >Wrong directory. It wasn't here at all before, so I am really confused >how this could happen. > >Subject: drop redundant pieces: yaml, devicetree and bindings. > > >> >> diff --git a/Documentation/devicetree/bindings/cnm,wave5.yml b/Documentation/devicetree/bindings/cnm,wave5.yml >> new file mode 100644 >> index 000000000000..01dddebb162e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/cnm,wave5.yml >> @@ -0,0 +1,72 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/media/wave5.yaml# > >You clearly did not test them before sending. > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Chips&Media Wave 5 Series multi-standard codec IP >> + >> +maintainers: >> + - Nas Chung <nas.chung@chipsnmedia.com> >> + - Robert Beckett <bob.beckett@collabora.com> >> + - Sebastian Fricke <sebastian.fricke@collabora.com> >> + >> +description: |- >> + The Chips&Media WAVE codec IP is a multi format video encoder/decoder >> + >> +properties: >> + compatible: >> + anyOf: > >Please start from example-schema or other recently approved bindings. No >anyOf. > >> + - items: > >No items... > >> + - enum: >> + - cnm,cm511-vpu >> + - cnm,cm517-vpu >> + - cnm,cm521-vpu >> + - cnm,cm521c-vpu >> + - cnm,cm521c-dual-vpu > >What's the difference between this and one above? > >> + - cnm,cm521e1-vpu >> + - cnm,cm537-vpu >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + minItems: 1 >> + maxItems: 4 > >This has to be specific. > >> + >> + clock-names: >> + minItems: 1 >> + maxItems: 4 > >You need to list the names. > >> + >> + interrupts: >> + maxItems: 1 >> + >> + power-domains: >> + maxItems: 1 >> + >> + resets: >> + maxItems: 1 >> + >> + sram: > >Missing vendor prefix. After some discussion with the the manufacturer of this CODEC chip, the SRAM is not fixed to the CODEC chip but instead part of the SoC, thus the vendor can vary. It sounds like the policy is to use the vendor prefix of the SoC, that was used for upstreaming. But that policy sounds a bit like a potential for future confusion to me, so I wanted to ask what you would like to see. The SoC we develop on is from TI and the CODEC chip is from C&M, so I could either call it: `ti,sram` or `cnm,sram` > >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: phandle pointing to the SRAM device node > >And what is it for? Why do you need SRAM? I would write the following here: The VPU uses the SRAM to store some of the reference data instead of storing it on DMA memory. It is mainly used for the purpose of reducing bandwidth. Sincerely, Sebastian > >> + maxItems: 1 > >Drop > >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - clocks >> + - clock-names >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + vpu: video-codec@12345678 { >> + compatible = "cnm,cm521-vpu"; >> + reg = <0x12345678 0x1000>; >> + interrupts = <42>; >> + clocks = <&clks 42>; >> + clock-names = "vcodec"; >> + sram = <&sram>; >> + }; > >Best regards, >Krzysztof > ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v11 5/6] dt-bindings: media: wave5: add yaml devicetree bindings 2023-09-04 6:25 ` Sebastian Fricke @ 2023-09-04 7:53 ` Krzysztof Kozlowski 0 siblings, 0 replies; 22+ messages in thread From: Krzysztof Kozlowski @ 2023-09-04 7:53 UTC (permalink / raw) To: Sebastian Fricke Cc: linux-media, Rob Herring, kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, devicetree, linux-kernel On 04/09/2023 08:25, Sebastian Fricke wrote: >>> + sram: >> >> Missing vendor prefix. > > After some discussion with the the manufacturer of this CODEC chip, the SRAM > is not fixed to the CODEC chip but instead part of the SoC, thus the > vendor can vary. It sounds like the policy is to use the vendor prefix > of the SoC, that was used for upstreaming. But that policy sounds a bit > like a potential for future confusion to me, so I wanted to ask what you > would like to see. The SoC we develop on is from TI and the CODEC chip is from > C&M, so I could either call it: `ti,sram` or `cnm,sram` I meant vendor prefix of this device. It does not matter what SoC is that, however it turns out it is already a generic property, so no vendor prefix is needed if you use the same property - phandle points to a node which is a sram.yaml. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v11 6/6] media: chips-media: wave5: Add wave5 driver to maintainers file [not found] <20221207121350.66217-1-sebastian.fricke@collabora.com> ` (4 preceding siblings ...) 2022-12-07 12:13 ` [PATCH v11 5/6] dt-bindings: media: wave5: add yaml devicetree bindings Sebastian Fricke @ 2022-12-07 12:13 ` Sebastian Fricke 2022-12-08 5:29 ` kernel test robot 5 siblings, 1 reply; 22+ messages in thread From: Sebastian Fricke @ 2022-12-07 12:13 UTC (permalink / raw) To: linux-media Cc: kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, Sebastian Fricke, linux-kernel From: Robert Beckett <bob.beckett@collabora.com> Add the Chips&Media wave5 encoder/decoder driver to the maintainers file Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 83801ff3507d..ddb61ee10c59 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22155,6 +22155,15 @@ F: include/linux/watchdog.h F: include/uapi/linux/watchdog.h F: include/trace/events/watchdog.h +WAVE5 VPU CODEC DRIVER +M: Nas Chung <nas.chung@chipsnmedia.com> +M: Robert Beckett <bob.beckett@collabora.com> +M: Sebastian Fricke <sebastian.fricke@collabora.com> +L: linux-media@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/media/cnm,wave5.yaml +F: drivers/media/platform/chips-media/wave5/ + WHISKEYCOVE PMIC GPIO DRIVER M: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> L: linux-gpio@vger.kernel.org -- 2.25.1 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v11 6/6] media: chips-media: wave5: Add wave5 driver to maintainers file 2022-12-07 12:13 ` [PATCH v11 6/6] media: chips-media: wave5: Add wave5 driver to maintainers file Sebastian Fricke @ 2022-12-08 5:29 ` kernel test robot 0 siblings, 0 replies; 22+ messages in thread From: kernel test robot @ 2022-12-08 5:29 UTC (permalink / raw) To: Sebastian Fricke, linux-media Cc: oe-kbuild-all, kernel, bob.beckett, hverkuil-cisco, nicolas.dufresne, nas.chung, Sebastian Fricke, linux-kernel [-- Attachment #1: Type: text/plain, Size: 1576 bytes --] Hi Sebastian, I love your patch! Perhaps something to improve: [auto build test WARNING on media-tree/master] [also build test WARNING on robh/for-next linus/master sailus-media-tree/streams v6.1-rc8 next-20221207] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Sebastian-Fricke/Wave5-codec-driver/20221207-201618 base: git://linuxtv.org/media_tree.git master patch link: https://lore.kernel.org/r/20221207121350.66217-7-sebastian.fricke%40collabora.com patch subject: [PATCH v11 6/6] media: chips-media: wave5: Add wave5 driver to maintainers file reproduce: # https://github.com/intel-lab-lkp/linux/commit/ecd9a1264703561791ef1c77a76880b95b55eda9 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Sebastian-Fricke/Wave5-codec-driver/20221207-201618 git checkout ecd9a1264703561791ef1c77a76880b95b55eda9 make menuconfig # enable CONFIG_COMPILE_TEST, CONFIG_WARN_MISSING_DOCUMENTS, CONFIG_WARN_ABI_ERRORS make htmldocs If you fix the issue, kindly add following tag where applicable | Reported-by: kernel test robot <lkp@intel.com> All warnings (new ones prefixed by >>): >> Warning: MAINTAINERS references a file that doesn't exist: Documentation/devicetree/bindings/media/cnm,wave5.yaml -- 0-DAY CI Kernel Test Service https://01.org/lkp [-- Attachment #2: config --] [-- Type: text/plain, Size: 38869 bytes --] # # Automatically generated file; DO NOT EDIT. # Linux/x86_64 6.1.0-rc4 Kernel Configuration # CONFIG_CC_VERSION_TEXT="gcc-11 (Debian 11.3.0-8) 11.3.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=110300 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=23900 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=123 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_COMPILE_TEST=y # CONFIG_WERROR is not set CONFIG_LOCALVERSION="" CONFIG_BUILD_SALT="" CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_BZIP2=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y CONFIG_HAVE_KERNEL_ZSTD=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set # CONFIG_KERNEL_ZSTD is not set CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" # CONFIG_SYSVIPC is not set # CONFIG_WATCH_QUEUE is not set # CONFIG_CROSS_MEMORY_ATTACH is not set # CONFIG_USELIB is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y # # IRQ subsystem # CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y CONFIG_GENERIC_IRQ_RESERVATION_MODE=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y # end of IRQ subsystem CONFIG_CLOCKSOURCE_WATCHDOG=y CONFIG_ARCH_CLOCKSOURCE_INIT=y CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y # # Timers subsystem # CONFIG_HZ_PERIODIC=y # CONFIG_NO_HZ_IDLE is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 # end of Timers subsystem CONFIG_HAVE_EBPF_JIT=y CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y # # BPF subsystem # # CONFIG_BPF_SYSCALL is not set # end of BPF subsystem CONFIG_PREEMPT_NONE_BUILD=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_PREEMPT_DYNAMIC is not set # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y # CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set # CONFIG_IRQ_TIME_ACCOUNTING is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_PSI is not set # end of CPU/Task time and stats accounting CONFIG_CPU_ISOLATION=y # # RCU Subsystem # CONFIG_TINY_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TINY_SRCU=y # end of RCU Subsystem # CONFIG_IKCONFIG is not set # CONFIG_IKHEADERS is not set CONFIG_LOG_BUF_SHIFT=17 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y # # Scheduler features # # end of Scheduler features CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y CONFIG_CC_HAS_INT128=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_ARCH_SUPPORTS_INT128=y # CONFIG_CGROUPS is not set CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set # CONFIG_TIME_NS is not set # CONFIG_USER_NS is not set # CONFIG_PID_NS is not set # CONFIG_CHECKPOINT_RESTORE is not set # CONFIG_SCHED_AUTOGROUP is not set # CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set # CONFIG_BLK_DEV_INITRD is not set # CONFIG_BOOT_CONFIG is not set # CONFIG_INITRAMFS_PRESERVE_MTIME is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_HAVE_PCSPKR_PLATFORM=y # CONFIG_EXPERT is not set CONFIG_MULTIUSER=y CONFIG_SGETMASK_SYSCALL=y CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_PCSPKR_PLATFORM=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_RSEQ=y # CONFIG_EMBEDDED is not set CONFIG_HAVE_PERF_EVENTS=y # # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y # end of Kernel Performance Events And Counters # CONFIG_PROFILING is not set # end of General setup CONFIG_64BIT=y CONFIG_X86_64=y CONFIG_X86=y CONFIG_INSTRUCTION_DECODER=y CONFIG_OUTPUT_FORMAT="elf64-x86-64" CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=28 CONFIG_ARCH_MMAP_RND_BITS_MAX=32 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 CONFIG_GENERIC_ISA_DMA=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_HAS_CPU_RELAX=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_NR_GPIO=1024 CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_AUDIT_ARCH=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_PGTABLE_LEVELS=4 CONFIG_CC_HAS_SANE_STACKPROTECTOR=y # # Processor type and features # # CONFIG_SMP is not set CONFIG_X86_FEATURE_NAMES=y CONFIG_X86_MPPARSE=y # CONFIG_GOLDFISH is not set # CONFIG_X86_CPU_RESCTRL is not set # CONFIG_X86_EXTENDED_PLATFORM is not set # CONFIG_SCHED_OMIT_FRAME_POINTER is not set # CONFIG_HYPERVISOR_GUEST is not set # CONFIG_MK8 is not set # CONFIG_MPSC is not set # CONFIG_MCORE2 is not set # CONFIG_MATOM is not set CONFIG_GENERIC_CPU=y CONFIG_X86_INTERNODE_CACHE_SHIFT=6 CONFIG_X86_L1_CACHE_SHIFT=6 CONFIG_X86_TSC=y CONFIG_X86_CMPXCHG64=y CONFIG_X86_CMOV=y CONFIG_X86_MINIMUM_CPU_FAMILY=64 CONFIG_X86_DEBUGCTLMSR=y CONFIG_IA32_FEAT_CTL=y CONFIG_X86_VMX_FEATURE_NAMES=y CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_AMD=y CONFIG_CPU_SUP_HYGON=y CONFIG_CPU_SUP_CENTAUR=y CONFIG_CPU_SUP_ZHAOXIN=y CONFIG_HPET_TIMER=y CONFIG_DMI=y CONFIG_NR_CPUS_RANGE_BEGIN=1 CONFIG_NR_CPUS_RANGE_END=1 CONFIG_NR_CPUS_DEFAULT=1 CONFIG_NR_CPUS=1 CONFIG_UP_LATE_INIT=y CONFIG_X86_LOCAL_APIC=y CONFIG_X86_IO_APIC=y # CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set # CONFIG_X86_MCE is not set # # Performance monitoring # # CONFIG_PERF_EVENTS_AMD_POWER is not set # CONFIG_PERF_EVENTS_AMD_UNCORE is not set # CONFIG_PERF_EVENTS_AMD_BRS is not set # end of Performance monitoring CONFIG_X86_16BIT=y CONFIG_X86_ESPFIX64=y CONFIG_X86_VSYSCALL_EMULATION=y # CONFIG_X86_IOPL_IOPERM is not set # CONFIG_MICROCODE is not set # CONFIG_X86_MSR is not set # CONFIG_X86_CPUID is not set # CONFIG_X86_5LEVEL is not set CONFIG_X86_DIRECT_GBPAGES=y # CONFIG_AMD_MEM_ENCRYPT is not set CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 # CONFIG_X86_CHECK_BIOS_CORRUPTION is not set CONFIG_MTRR=y # CONFIG_MTRR_SANITIZER is not set CONFIG_X86_PAT=y CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_X86_UMIP=y CONFIG_CC_HAS_IBT=y # CONFIG_X86_KERNEL_IBT is not set # CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set CONFIG_X86_INTEL_TSX_MODE_OFF=y # CONFIG_X86_INTEL_TSX_MODE_ON is not set # CONFIG_X86_INTEL_TSX_MODE_AUTO is not set # CONFIG_HZ_100 is not set CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 # CONFIG_KEXEC is not set # CONFIG_CRASH_DUMP is not set CONFIG_PHYSICAL_START=0x1000000 # CONFIG_RELOCATABLE is not set CONFIG_PHYSICAL_ALIGN=0x200000 CONFIG_LEGACY_VSYSCALL_XONLY=y # CONFIG_LEGACY_VSYSCALL_NONE is not set # CONFIG_CMDLINE_BOOL is not set CONFIG_MODIFY_LDT_SYSCALL=y # CONFIG_STRICT_SIGALTSTACK_SIZE is not set CONFIG_HAVE_LIVEPATCH=y # end of Processor type and features CONFIG_CC_HAS_SLS=y CONFIG_CC_HAS_RETURN_THUNK=y # CONFIG_SPECULATION_MITIGATIONS is not set CONFIG_ARCH_HAS_ADD_PAGES=y CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y # # Power management and ACPI options # # CONFIG_SUSPEND is not set # CONFIG_PM is not set CONFIG_ARCH_SUPPORTS_ACPI=y # CONFIG_ACPI is not set # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set # end of CPU Frequency scaling # # CPU Idle # # CONFIG_CPU_IDLE is not set # end of CPU Idle # end of Power management and ACPI options # # Bus options (PCI etc.) # CONFIG_ISA_DMA_API=y # end of Bus options (PCI etc.) # # Binary Emulations # # CONFIG_IA32_EMULATION is not set # CONFIG_X86_X32_ABI is not set # end of Binary Emulations CONFIG_HAVE_KVM=y # CONFIG_VIRTUALIZATION is not set CONFIG_AS_AVX512=y CONFIG_AS_SHA1_NI=y CONFIG_AS_SHA256_NI=y CONFIG_AS_TPAUSE=y # # General architecture-dependent options # CONFIG_GENERIC_ENTRY=y # CONFIG_JUMP_LABEL is not set # CONFIG_STATIC_CALL_SELFTEST is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_ARCH_USE_BUILTIN_BSWAP=y CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_OPTPROBES=y CONFIG_HAVE_KPROBES_ON_FTRACE=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y CONFIG_HAVE_NMI=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y CONFIG_HAVE_ARCH_TRACEHOOK=y CONFIG_HAVE_DMA_CONTIGUOUS=y CONFIG_GENERIC_SMP_IDLE_THREAD=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_RUST=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y CONFIG_HAVE_USER_RETURN_NOTIFIER=y CONFIG_HAVE_PERF_EVENTS_NMI=y CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y CONFIG_MMU_GATHER_MERGE_VMAS=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CMPXCHG_DOUBLE=y CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y # CONFIG_SECCOMP is not set CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y # CONFIG_STACKPROTECTOR is not set CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y CONFIG_ARCH_SUPPORTS_CFI_CLANG=y CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_CONTEXT_TRACKING_USER_OFFSTACK=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y CONFIG_HAVE_ARCH_HUGE_VMAP=y CONFIG_HAVE_ARCH_HUGE_VMALLOC=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_ARCH_SOFT_DIRTY=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=28 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_HAVE_OBJTOOL=y CONFIG_HAVE_JUMP_LABEL_HACK=y CONFIG_HAVE_NOINSTR_HACK=y CONFIG_HAVE_NOINSTR_VALIDATION=y CONFIG_HAVE_UACCESS_VALIDATION=y CONFIG_HAVE_STACK_VALIDATION=y CONFIG_HAVE_RELIABLE_STACKTRACE=y # CONFIG_COMPAT_32BIT_TIME is not set CONFIG_HAVE_ARCH_VMAP_STACK=y # CONFIG_VMAP_STACK is not set CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y # CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_HAS_MEM_ENCRYPT=y CONFIG_HAVE_STATIC_CALL=y CONFIG_HAVE_STATIC_CALL_INLINE=y CONFIG_HAVE_PREEMPT_DYNAMIC=y CONFIG_HAVE_PREEMPT_DYNAMIC_CALL=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y CONFIG_ARCH_HAS_ELFCORE_COMPAT=y CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y CONFIG_DYNAMIC_SIGFRAME=y CONFIG_ARCH_HAS_NONLEAF_PMD_YOUNG=y # # GCOV-based kernel profiling # CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling CONFIG_HAVE_GCC_PLUGINS=y # CONFIG_GCC_PLUGINS is not set # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 # CONFIG_MODULES is not set CONFIG_BLOCK=y # CONFIG_BLOCK_LEGACY_AUTOLOAD is not set # CONFIG_BLK_DEV_BSGLIB is not set # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_SED_OPAL is not set # CONFIG_BLK_INLINE_ENCRYPTION is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y CONFIG_EFI_PARTITION=y # end of Partition Types # # IO Schedulers # # CONFIG_MQ_IOSCHED_DEADLINE is not set # CONFIG_MQ_IOSCHED_KYBER is not set # CONFIG_IOSCHED_BFQ is not set # end of IO Schedulers CONFIG_INLINE_SPIN_UNLOCK_IRQ=y CONFIG_INLINE_READ_UNLOCK=y CONFIG_INLINE_READ_UNLOCK_IRQ=y CONFIG_INLINE_WRITE_UNLOCK=y CONFIG_INLINE_WRITE_UNLOCK_IRQ=y CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y # # Executable file formats # # CONFIG_BINFMT_ELF is not set # CONFIG_BINFMT_SCRIPT is not set # CONFIG_BINFMT_MISC is not set CONFIG_COREDUMP=y # end of Executable file formats # # Memory Management options # # CONFIG_SWAP is not set # # SLAB allocator options # # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLAB_MERGE_DEFAULT is not set # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set # CONFIG_SLUB_STATS is not set # end of SLAB allocator options # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set # CONFIG_COMPAT_BRK is not set CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y # CONFIG_SPARSEMEM_VMEMMAP is not set CONFIG_HAVE_FAST_GUP=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y # CONFIG_MEMORY_HOTPLUG is not set CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y # CONFIG_COMPACTION is not set # CONFIG_PAGE_REPORTING is not set CONFIG_PHYS_ADDR_T_64BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ARCH_WANTS_THP_SWAP=y # CONFIG_TRANSPARENT_HUGEPAGE is not set CONFIG_NEED_PER_CPU_KM=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y # CONFIG_CMA is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y CONFIG_VM_EVENT_COUNTERS=y # CONFIG_PERCPU_STATS is not set # # GUP_TEST needs to have DEBUG_FS enabled # CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_SECRETMEM=y # CONFIG_ANON_VMA_NAME is not set # CONFIG_USERFAULTFD is not set # CONFIG_LRU_GEN is not set # # Data Access Monitoring # # CONFIG_DAMON is not set # end of Data Access Monitoring # end of Memory Management options # CONFIG_NET is not set # # Device Drivers # CONFIG_HAVE_EISA=y # CONFIG_EISA is not set CONFIG_HAVE_PCI=y # CONFIG_PCI is not set # CONFIG_PCCARD is not set # # Generic Driver Options # # CONFIG_UEVENT_HELPER is not set # CONFIG_DEVTMPFS is not set # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set # # Firmware loader # CONFIG_FW_LOADER=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set # CONFIG_FW_LOADER_COMPRESS is not set # CONFIG_FW_UPLOAD is not set # end of Firmware loader CONFIG_ALLOW_DEV_COREDUMP=y CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y # end of Generic Driver Options # # Bus devices # # CONFIG_ARM_INTEGRATOR_LM is not set # CONFIG_BT1_APB is not set # CONFIG_BT1_AXI is not set # CONFIG_HISILICON_LPC is not set # CONFIG_INTEL_IXP4XX_EB is not set # CONFIG_QCOM_EBI2 is not set # CONFIG_MHI_BUS is not set # CONFIG_MHI_BUS_EP is not set # end of Bus devices # # Firmware Drivers # # # ARM System Control and Management Interface Protocol # # CONFIG_ARM_SCMI_PROTOCOL is not set # end of ARM System Control and Management Interface Protocol # CONFIG_EDD is not set CONFIG_FIRMWARE_MEMMAP=y # CONFIG_DMIID is not set # CONFIG_DMI_SYSFS is not set CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y # CONFIG_FW_CFG_SYSFS is not set # CONFIG_SYSFB_SIMPLEFB is not set # CONFIG_BCM47XX_NVRAM is not set # CONFIG_GOOGLE_FIRMWARE is not set # # Tegra firmware driver # # end of Tegra firmware driver # end of Firmware Drivers # CONFIG_GNSS is not set # CONFIG_MTD is not set # CONFIG_OF is not set CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y # CONFIG_PARPORT is not set # CONFIG_BLK_DEV is not set # # NVME Support # # CONFIG_NVME_FC is not set # end of NVME Support # # Misc devices # # CONFIG_DUMMY_IRQ is not set # CONFIG_ATMEL_SSC is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_QCOM_COINCELL is not set # CONFIG_SRAM is not set # CONFIG_XILINX_SDFEC is not set # CONFIG_C2PORT is not set # # EEPROM support # # CONFIG_EEPROM_93CX6 is not set # end of EEPROM support # # Texas Instruments shared transport line discipline # # end of Texas Instruments shared transport line discipline # # Altera FPGA firmware download module (requires I2C) # # CONFIG_ECHO is not set # CONFIG_PVPANIC is not set # end of Misc devices # # SCSI device support # CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # end of SCSI device support # CONFIG_ATA is not set # CONFIG_MD is not set # CONFIG_TARGET_CORE is not set # # IEEE 1394 (FireWire) support # # CONFIG_FIREWIRE is not set # end of IEEE 1394 (FireWire) support # CONFIG_MACINTOSH_DRIVERS is not set # # Input device support # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_SPARSEKMAP is not set # CONFIG_INPUT_MATRIXKMAP is not set # # Userland interfaces # # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set # CONFIG_RMI4_CORE is not set # # Hardware I/O ports # # CONFIG_SERIO is not set CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y # CONFIG_GAMEPORT is not set # end of Hardware I/O ports # end of Input device support # # Character devices # CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set # CONFIG_LDISC_AUTOLOAD is not set # # Serial drivers # # CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # # CONFIG_SERIAL_AMBA_PL010 is not set # CONFIG_SERIAL_MESON is not set # CONFIG_SERIAL_CLPS711X is not set # CONFIG_SERIAL_SAMSUNG is not set # CONFIG_SERIAL_TEGRA is not set # CONFIG_SERIAL_IMX is not set # CONFIG_SERIAL_UARTLITE is not set # CONFIG_SERIAL_SH_SCI is not set # CONFIG_SERIAL_MSM is not set # CONFIG_SERIAL_VT8500 is not set # CONFIG_SERIAL_OMAP is not set # CONFIG_SERIAL_LANTIQ is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_TIMBERDALE is not set # CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_MXS_AUART is not set # CONFIG_SERIAL_MPS2_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_FSL_LPUART is not set # CONFIG_SERIAL_FSL_LINFLEXUART is not set # CONFIG_SERIAL_ST_ASC is not set # CONFIG_SERIAL_STM32 is not set # CONFIG_SERIAL_OWL is not set # CONFIG_SERIAL_RDA is not set # CONFIG_SERIAL_LITEUART is not set # CONFIG_SERIAL_SUNPLUS is not set # end of Serial drivers # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_NULL_TTY is not set # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_VIRTIO_CONSOLE is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_ASPEED_KCS_IPMI_BMC is not set # CONFIG_NPCM7XX_KCS_IPMI_BMC is not set # CONFIG_HW_RANDOM is not set # CONFIG_MWAVE is not set # CONFIG_DEVMEM is not set # CONFIG_NVRAM is not set # CONFIG_HANGCHECK_TIMER is not set # CONFIG_TCG_TPM is not set # CONFIG_TELCLOCK is not set # CONFIG_RANDOM_TRUST_CPU is not set # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices # # I2C support # # CONFIG_I2C is not set # end of I2C support # CONFIG_I3C is not set # CONFIG_SPI is not set # CONFIG_SPMI is not set # CONFIG_HSI is not set # CONFIG_PPS is not set # # PTP clock support # CONFIG_PTP_1588_CLOCK_OPTIONAL=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # # end of PTP clock support # CONFIG_PINCTRL is not set # CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_RESET is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set CONFIG_BCMA_POSSIBLE=y # CONFIG_BCMA is not set # # Multifunction device drivers # # CONFIG_MFD_SUN4I_GPADC is not set # CONFIG_MFD_AT91_USART is not set # CONFIG_MFD_MADERA is not set # CONFIG_MFD_EXYNOS_LPASS is not set # CONFIG_MFD_MXS_LRADC is not set # CONFIG_MFD_MX25_TSADC is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_PM8XXX is not set # CONFIG_MFD_SM501 is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_SUN6I_PRCM is not set # CONFIG_MFD_SYSCON is not set # CONFIG_MFD_TI_AM335X_TSCADC is not set # CONFIG_MFD_TQMX86 is not set # CONFIG_MFD_STM32_LPTIMER is not set # CONFIG_MFD_STM32_TIMERS is not set # end of Multifunction device drivers # CONFIG_REGULATOR is not set # CONFIG_RC_CORE is not set # # CEC support # # CONFIG_MEDIA_CEC_SUPPORT is not set # end of CEC support # CONFIG_MEDIA_SUPPORT is not set # # Graphics support # # CONFIG_IMX_IPUV3_CORE is not set # CONFIG_DRM is not set # # ARM devices # # end of ARM devices # # Frame buffer Devices # # CONFIG_FB is not set # CONFIG_MMP_DISP is not set # end of Frame buffer Devices # # Backlight & LCD device support # # CONFIG_LCD_CLASS_DEVICE is not set # CONFIG_BACKLIGHT_CLASS_DEVICE is not set # end of Backlight & LCD device support # # Console display driver support # CONFIG_VGA_CONSOLE=y CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 # end of Console display driver support # end of Graphics support # CONFIG_SOUND is not set # # HID support # # CONFIG_HID is not set # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y CONFIG_RTC_LIB=y CONFIG_RTC_MC146818_LIB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # # DMABUF options # # CONFIG_SYNC_FILE is not set # CONFIG_DMABUF_HEAPS is not set # end of DMABUF options # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # CONFIG_VFIO is not set # CONFIG_VIRT_DRIVERS is not set # CONFIG_VIRTIO_MENU is not set # CONFIG_VHOST_MENU is not set # # Microsoft Hyper-V guest support # # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set # CONFIG_COMEDI is not set # CONFIG_STAGING is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set # CONFIG_OLPC_XO175 is not set # CONFIG_SURFACE_PLATFORMS is not set # CONFIG_X86_PLATFORM_DEVICES is not set # CONFIG_COMMON_CLK is not set # CONFIG_HWSPINLOCK is not set # # Clock Source drivers # CONFIG_CLKEVT_I8253=y CONFIG_I8253_LOCK=y CONFIG_CLKBLD_I8253=y # CONFIG_BCM2835_TIMER is not set # CONFIG_BCM_KONA_TIMER is not set # CONFIG_DAVINCI_TIMER is not set # CONFIG_DIGICOLOR_TIMER is not set # CONFIG_OMAP_DM_TIMER is not set # CONFIG_DW_APB_TIMER is not set # CONFIG_FTTMR010_TIMER is not set # CONFIG_IXP4XX_TIMER is not set # CONFIG_MESON6_TIMER is not set # CONFIG_OWL_TIMER is not set # CONFIG_RDA_TIMER is not set # CONFIG_SUN4I_TIMER is not set # CONFIG_TEGRA_TIMER is not set # CONFIG_VT8500_TIMER is not set # CONFIG_NPCM7XX_TIMER is not set # CONFIG_ASM9260_TIMER is not set # CONFIG_CLKSRC_DBX500_PRCMU is not set # CONFIG_CLPS711X_TIMER is not set # CONFIG_MXS_TIMER is not set # CONFIG_NSPIRE_TIMER is not set # CONFIG_INTEGRATOR_AP_TIMER is not set # CONFIG_CLKSRC_PISTACHIO is not set # CONFIG_CLKSRC_STM32_LP is not set # CONFIG_ARMV7M_SYSTICK is not set # CONFIG_ATMEL_PIT is not set # CONFIG_ATMEL_ST is not set # CONFIG_CLKSRC_SAMSUNG_PWM is not set # CONFIG_FSL_FTM_TIMER is not set # CONFIG_OXNAS_RPS_TIMER is not set # CONFIG_MTK_TIMER is not set # CONFIG_SH_TIMER_CMT is not set # CONFIG_SH_TIMER_MTU2 is not set # CONFIG_RENESAS_OSTM is not set # CONFIG_SH_TIMER_TMU is not set # CONFIG_EM_TIMER_STI is not set # CONFIG_CLKSRC_PXA is not set # CONFIG_TIMER_IMX_SYS_CTR is not set # CONFIG_CLKSRC_ST_LPC is not set # CONFIG_GXP_TIMER is not set # CONFIG_MSC313E_TIMER is not set # CONFIG_MICROCHIP_PIT64B is not set # end of Clock Source drivers # CONFIG_MAILBOX is not set # CONFIG_IOMMU_SUPPORT is not set # # Remoteproc drivers # # CONFIG_REMOTEPROC is not set # end of Remoteproc drivers # # Rpmsg drivers # # CONFIG_RPMSG_VIRTIO is not set # end of Rpmsg drivers # # SOC (System On Chip) specific Drivers # # # Amlogic SoC drivers # # CONFIG_MESON_CANVAS is not set # CONFIG_MESON_CLK_MEASURE is not set # CONFIG_MESON_GX_SOCINFO is not set # CONFIG_MESON_MX_SOCINFO is not set # end of Amlogic SoC drivers # # Apple SoC drivers # # CONFIG_APPLE_SART is not set # end of Apple SoC drivers # # ASPEED SoC drivers # # CONFIG_ASPEED_LPC_CTRL is not set # CONFIG_ASPEED_LPC_SNOOP is not set # CONFIG_ASPEED_UART_ROUTING is not set # CONFIG_ASPEED_P2A_CTRL is not set # CONFIG_ASPEED_SOCINFO is not set # end of ASPEED SoC drivers # CONFIG_AT91_SOC_ID is not set # CONFIG_AT91_SOC_SFR is not set # # Broadcom SoC drivers # # CONFIG_SOC_BCM63XX is not set # CONFIG_SOC_BRCMSTB is not set # end of Broadcom SoC drivers # # NXP/Freescale QorIQ SoC drivers # # end of NXP/Freescale QorIQ SoC drivers # # fujitsu SoC drivers # # end of fujitsu SoC drivers # # i.MX SoC drivers # # CONFIG_SOC_IMX8M is not set # CONFIG_SOC_IMX9 is not set # end of i.MX SoC drivers # # IXP4xx SoC drivers # # CONFIG_IXP4XX_QMGR is not set # CONFIG_IXP4XX_NPE is not set # end of IXP4xx SoC drivers # # Enable LiteX SoC Builder specific drivers # # CONFIG_LITEX_SOC_CONTROLLER is not set # end of Enable LiteX SoC Builder specific drivers # # MediaTek SoC drivers # # CONFIG_MTK_CMDQ is not set # CONFIG_MTK_DEVAPC is not set # CONFIG_MTK_INFRACFG is not set # CONFIG_MTK_MMSYS is not set # end of MediaTek SoC drivers # # Qualcomm SoC drivers # # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GSBI is not set # CONFIG_QCOM_LLCC is not set # CONFIG_QCOM_RPMH is not set # CONFIG_QCOM_SPM is not set # CONFIG_QCOM_ICC_BWMON is not set # end of Qualcomm SoC drivers # CONFIG_SOC_RENESAS is not set # CONFIG_ROCKCHIP_GRF is not set # CONFIG_SOC_SAMSUNG is not set # CONFIG_SOC_TI is not set # CONFIG_UX500_SOC_ID is not set # # Xilinx SoC drivers # # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers # CONFIG_PM_DEVFREQ is not set # CONFIG_EXTCON is not set # CONFIG_MEMORY is not set # CONFIG_IIO is not set # CONFIG_PWM is not set # # IRQ chip support # # CONFIG_AL_FIC is not set # CONFIG_RENESAS_INTC_IRQPIN is not set # CONFIG_RENESAS_IRQC is not set # CONFIG_RENESAS_RZA1_IRQC is not set # CONFIG_RENESAS_RZG2L_IRQC is not set # CONFIG_SL28CPLD_INTC is not set # CONFIG_TS4800_IRQ is not set # CONFIG_INGENIC_TCU_IRQ is not set # CONFIG_IRQ_UNIPHIER_AIDET is not set # CONFIG_MESON_IRQ_GPIO is not set # CONFIG_IMX_IRQSTEER is not set # CONFIG_IMX_INTMUX is not set # CONFIG_EXYNOS_IRQ_COMBINER is not set # CONFIG_MST_IRQ is not set # CONFIG_MCHP_EIC is not set # CONFIG_SUNPLUS_SP7021_INTC is not set # end of IRQ chip support # CONFIG_IPACK_BUS is not set # CONFIG_RESET_CONTROLLER is not set # # PHY Subsystem # # CONFIG_GENERIC_PHY is not set # CONFIG_PHY_PISTACHIO_USB is not set # CONFIG_PHY_CAN_TRANSCEIVER is not set # # PHY drivers for Broadcom platforms # # CONFIG_PHY_BCM63XX_USBH is not set # CONFIG_BCM_KONA_USB2_PHY is not set # end of PHY drivers for Broadcom platforms # CONFIG_PHY_HI6220_USB is not set # CONFIG_PHY_HI3660_USB is not set # CONFIG_PHY_HI3670_USB is not set # CONFIG_PHY_HI3670_PCIE is not set # CONFIG_PHY_HISTB_COMBPHY is not set # CONFIG_PHY_HISI_INNO_USB2 is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_PXA_USB is not set # CONFIG_PHY_MMP3_USB is not set # CONFIG_PHY_MMP3_HSIC is not set # CONFIG_PHY_MT7621_PCI is not set # CONFIG_PHY_RALINK_USB is not set # CONFIG_PHY_RCAR_GEN3_USB3 is not set # CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set # CONFIG_PHY_ROCKCHIP_PCIE is not set # CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set # CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set # CONFIG_PHY_SAMSUNG_USB2 is not set # CONFIG_PHY_ST_SPEAR1310_MIPHY is not set # CONFIG_PHY_ST_SPEAR1340_MIPHY is not set # CONFIG_PHY_TEGRA194_P2U is not set # CONFIG_PHY_DA8XX_USB is not set # CONFIG_OMAP_CONTROL_PHY is not set # CONFIG_TI_PIPE3 is not set # CONFIG_PHY_INTEL_KEEMBAY_EMMC is not set # CONFIG_PHY_INTEL_KEEMBAY_USB is not set # CONFIG_PHY_INTEL_LGM_EMMC is not set # CONFIG_PHY_XILINX_ZYNQMP is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set # CONFIG_MCB is not set # # Performance monitor support # # CONFIG_ARM_CCN is not set # CONFIG_ARM_CMN is not set # CONFIG_FSL_IMX8_DDR_PMU is not set # CONFIG_XGENE_PMU is not set # CONFIG_ARM_DMC620_PMU is not set # CONFIG_MARVELL_CN10K_TAD_PMU is not set # CONFIG_ALIBABA_UNCORE_DRW_PMU is not set # CONFIG_MARVELL_CN10K_DDR_PMU is not set # end of Performance monitor support # CONFIG_RAS is not set # # Android # # CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_DAX is not set # CONFIG_NVMEM is not set # # HW tracing support # # CONFIG_STM is not set # CONFIG_INTEL_TH is not set # end of HW tracing support # CONFIG_FPGA is not set # CONFIG_TEE is not set # CONFIG_SIOX is not set # CONFIG_SLIMBUS is not set # CONFIG_INTERCONNECT is not set # CONFIG_COUNTER is not set # CONFIG_PECI is not set # CONFIG_HTE is not set # end of Device Drivers # # File systems # CONFIG_DCACHE_WORD_ACCESS=y # CONFIG_VALIDATE_FS_PARSER is not set # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set # CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set # CONFIG_F2FS_FS is not set CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set CONFIG_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set # CONFIG_FS_VERITY is not set # CONFIG_DNOTIFY is not set # CONFIG_INOTIFY_USER is not set # CONFIG_FANOTIFY is not set # CONFIG_QUOTA is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_AUTOFS_FS is not set # CONFIG_FUSE_FS is not set # CONFIG_OVERLAY_FS is not set # # Caches # # CONFIG_FSCACHE is not set # end of Caches # # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set # CONFIG_UDF_FS is not set # end of CD-ROM/DVD Filesystems # # DOS/FAT/EXFAT/NT Filesystems # # CONFIG_MSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_EXFAT_FS is not set # CONFIG_NTFS_FS is not set # CONFIG_NTFS3_FS is not set # end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems # CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y # CONFIG_PROC_CHILDREN is not set CONFIG_PROC_PID_ARCH_STATUS=y CONFIG_KERNFS=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLBFS is not set CONFIG_ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y CONFIG_ARCH_HAS_GIGANTIC_PAGE=y # CONFIG_CONFIGFS_FS is not set # end of Pseudo filesystems # CONFIG_MISC_FILESYSTEMS is not set # CONFIG_NLS is not set # CONFIG_UNICODE is not set CONFIG_IO_WQ=y # end of File systems # # Security options # # CONFIG_KEYS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_HARDENED_USERCOPY is not set # CONFIG_FORTIFY_SOURCE is not set # CONFIG_STATIC_USERMODEHELPER is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf" # # Kernel hardening options # # # Memory initialization # CONFIG_INIT_STACK_NONE=y # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y # CONFIG_ZERO_CALL_USED_REGS is not set # end of Memory initialization CONFIG_RANDSTRUCT_NONE=y # end of Kernel hardening options # end of Security options # CONFIG_CRYPTO is not set # # Library routines # # CONFIG_PACKING is not set CONFIG_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y # CONFIG_CORDIC is not set # CONFIG_PRIME_NUMBERS is not set CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y # # Crypto library routines # CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y # CONFIG_CRYPTO_LIB_CHACHA is not set # CONFIG_CRYPTO_LIB_CURVE25519 is not set CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 # CONFIG_CRYPTO_LIB_POLY1305 is not set # end of Crypto library routines # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set # CONFIG_CRC64_ROCKSOFT is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC32_SELFTEST is not set CONFIG_CRC32_SLICEBY8=y # CONFIG_CRC32_SLICEBY4 is not set # CONFIG_CRC32_SARWATE is not set # CONFIG_CRC32_BIT is not set # CONFIG_CRC64 is not set # CONFIG_CRC4 is not set # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set # CONFIG_CRC8 is not set # CONFIG_RANDOM32_SELFTEST is not set # CONFIG_XZ_DEC is not set CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_SWIOTLB=y # CONFIG_DMA_API_DEBUG is not set # CONFIG_IRQ_POLL is not set CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_ARCH_HAS_PMEM_API=y CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y CONFIG_ARCH_HAS_COPY_MC=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y CONFIG_SBITMAP=y # CONFIG_PARMAN is not set # CONFIG_OBJAGG is not set # end of Library routines # # Kernel hacking # # # printk and dmesg options # # CONFIG_PRINTK_TIME is not set # CONFIG_PRINTK_CALLER is not set # CONFIG_STACKTRACE_BUILD_ID is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_DYNAMIC_DEBUG_CORE is not set # CONFIG_SYMBOLIC_ERRNAME is not set CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options # CONFIG_DEBUG_KERNEL is not set # # Compile-time checks and compiler options # CONFIG_AS_HAS_NON_CONST_LEB128=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_HEADERS_INSTALL is not set CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_SECTION_MISMATCH_WARN_ONLY=y CONFIG_OBJTOOL=y # end of Compile-time checks and compiler options # # Generic Kernel Debugging Instruments # # CONFIG_MAGIC_SYSRQ is not set # CONFIG_DEBUG_FS is not set CONFIG_HAVE_ARCH_KGDB=y CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y # CONFIG_UBSAN is not set CONFIG_HAVE_ARCH_KCSAN=y CONFIG_HAVE_KCSAN_COMPILER=y # end of Generic Kernel Debugging Instruments # # Networking Debugging # # end of Networking Debugging # # Memory Debugging # # CONFIG_PAGE_EXTENSION is not set CONFIG_SLUB_DEBUG=y # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_PAGE_TABLE_CHECK is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_RODATA_TEST is not set CONFIG_ARCH_HAS_DEBUG_WX=y # CONFIG_DEBUG_WX is not set CONFIG_GENERIC_PTDUMP=y CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y # CONFIG_DEBUG_VM_PGTABLE is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y CONFIG_DEBUG_MEMORY_INIT=y CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set CONFIG_HAVE_ARCH_KFENCE=y # CONFIG_KFENCE is not set CONFIG_HAVE_ARCH_KMSAN=y # end of Memory Debugging # # Debug Oops, Lockups and Hangs # # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # # end of Scheduler Debugging # CONFIG_DEBUG_TIMEKEEPING is not set # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_WW_MUTEX_SELFTEST is not set # end of Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # # Debug kernel data structures # # CONFIG_BUG_ON_DATA_CORRUPTION is not set # end of Debug kernel data structures # # RCU Debugging # # end of RCU Debugging CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_HAVE_RETHOOK=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_DYNAMIC_FTRACE_NO_PATCHABLE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y CONFIG_HAVE_OBJTOOL_MCOUNT=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y CONFIG_HAVE_SAMPLE_FTRACE_DIRECT_MULTI=y CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # # x86 Debugging # # CONFIG_X86_VERBOSE_BOOTUP is not set CONFIG_EARLY_PRINTK=y CONFIG_HAVE_MMIOTRACE_SUPPORT=y CONFIG_IO_DELAY_0X80=y # CONFIG_IO_DELAY_0XED is not set # CONFIG_IO_DELAY_UDELAY is not set # CONFIG_IO_DELAY_NONE is not set CONFIG_UNWINDER_ORC=y # CONFIG_UNWINDER_FRAME_POINTER is not set # end of x86 Debugging # # Kernel Testing and Coverage # # CONFIG_KUNIT is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage # # Rust hacking # # end of Rust hacking CONFIG_WARN_MISSING_DOCUMENTS=y CONFIG_WARN_ABI_ERRORS=y # end of Kernel hacking ^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2023-09-04 7:53 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
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[not found] <20221207121350.66217-1-sebastian.fricke@collabora.com>
2022-12-07 12:13 ` [PATCH v11 1/6] media: platform: chips-media: Move Coda to separate folder Sebastian Fricke
2022-12-07 12:54 ` Philipp Zabel
2022-12-07 20:44 ` kernel test robot
2022-12-07 12:13 ` [PATCH v11 2/6] media: chips-media: wave5: Add vpuapi layer Sebastian Fricke
2022-12-07 13:05 ` AngeloGioacchino Del Regno
2022-12-15 13:31 ` Sebastian Fricke
2022-12-07 12:13 ` [PATCH v11 3/6] media: chips-media: wave5: Add the v4l2 layer Sebastian Fricke
2022-12-12 14:19 ` Hans Verkuil
2023-04-26 13:22 ` Nicolas Dufresne
2023-04-26 14:44 ` Nicolas Dufresne
2022-12-07 12:13 ` [PATCH v11 4/6] media: chips-media: wave5: Add TODO file Sebastian Fricke
2022-12-12 14:30 ` Hans Verkuil
2022-12-07 12:13 ` [PATCH v11 5/6] dt-bindings: media: wave5: add yaml devicetree bindings Sebastian Fricke
2022-12-07 12:31 ` Krzysztof Kozlowski
2022-12-07 13:17 ` Krzysztof Kozlowski
2022-12-07 15:09 ` Sebastian Fricke
2022-12-07 15:27 ` Krzysztof Kozlowski
2022-12-12 11:32 ` Sebastian Fricke
2023-09-04 6:25 ` Sebastian Fricke
2023-09-04 7:53 ` Krzysztof Kozlowski
2022-12-07 12:13 ` [PATCH v11 6/6] media: chips-media: wave5: Add wave5 driver to maintainers file Sebastian Fricke
2022-12-08 5:29 ` kernel test robot
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