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From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>,
	Andy Shevchenko <andy@kernel.org>,
	Linus Walleij <linus.walleij@linaro.org>
Subject: [PATCH v1 1/1] pinctrl: intel: Use same order of bit fields for PADCFG2
Date: Mon, 19 Dec 2022 14:32:29 +0200	[thread overview]
Message-ID: <20221219123229.5564-1-andriy.shevchenko@linux.intel.com> (raw)

PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same
for PADCFG2 bit fields.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/pinctrl/intel/pinctrl-intel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 5e21b0a96efe..9d2791a81ffa 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -88,9 +88,9 @@
 #define PADCFG1_TERM_800		(BIT(2) | BIT(1) | BIT(0))
 
 #define PADCFG2				0x008
-#define PADCFG2_DEBEN			BIT(0)
 #define PADCFG2_DEBOUNCE_SHIFT		1
 #define PADCFG2_DEBOUNCE_MASK		GENMASK(4, 1)
+#define PADCFG2_DEBEN			BIT(0)
 
 #define DEBOUNCE_PERIOD_NSEC		31250
 
-- 
2.35.1


             reply	other threads:[~2022-12-19 12:33 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-19 12:32 Andy Shevchenko [this message]
2022-12-19 14:34 ` [PATCH v1 1/1] pinctrl: intel: Use same order of bit fields for PADCFG2 Mika Westerberg
2022-12-19 14:39   ` Andy Shevchenko
2022-12-27 19:25   ` Andy Shevchenko

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