From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CABCC4332F for ; Thu, 22 Dec 2022 12:40:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235466AbiLVMkU (ORCPT ); Thu, 22 Dec 2022 07:40:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230301AbiLVMkR (ORCPT ); Thu, 22 Dec 2022 07:40:17 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1EA8E15; Thu, 22 Dec 2022 04:40:15 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 6032BB81D11; Thu, 22 Dec 2022 12:40:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C135CC433EF; Thu, 22 Dec 2022 12:40:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1671712813; bh=A8z1NSCUeJ0GDD5qSEMg8VBjXL+asOLb0k3hOA+DVns=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=j9DdAio452LSzQ2g8EiTrC8AiQD6o74vWIlB1P/cAxLYb9BdPYcMXO31mwYcHIDuE 4TVjl8HaK44hgK+ojucmH0VlXkPlWZ5QVRCx5sE6kOVu9eSyCIRDYgnwVL1SRMQXwK vU7AzH5Jlggs5JEIst3Vj0wcBNkTinhPdmeH2STzP7POf3KthXksIZtYsvN4Rv7KJm X/hntErPycQnSvedDI9JjWA7cbQOhbpOLAB3kqnzc825OPEEPm6eHY3ubOGDnLdyVa B9BvjqLObQ2Y9SkO3h10D25hAKnZHNyOSmIv2rH1x1U1ZX/vEtJ7ixR2VNl4MJcgiq 7m1VpPi4KrQSg== Date: Thu, 22 Dec 2022 13:40:10 +0100 From: Frederic Weisbecker To: Mathieu Desnoyers Cc: Joel Fernandes , linux-kernel@vger.kernel.org, Josh Triplett , Lai Jiangshan , "Paul E. McKenney" , rcu@vger.kernel.org, Steven Rostedt Subject: Re: [RFC 0/2] srcu: Remove pre-flip memory barrier Message-ID: <20221222124010.GC44777@lothringen> References: <6438d903-ab97-48c7-c338-9f0bc2686f94@efficios.com> <7A9876BA-C375-42A7-A5C9-FD940D2898D7@joelfernandes.org> <5bd5ee4a-710a-96bc-abe8-772b2e60f478@efficios.com> <20221220225756.GB26563@lothringen> <20221221115924.GA34934@lothringen> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 21, 2022 at 12:11:42PM -0500, Mathieu Desnoyers wrote: > On 2022-12-21 06:59, Frederic Weisbecker wrote: > > On Tue, Dec 20, 2022 at 10:34:19PM -0500, Mathieu Desnoyers wrote: > [...] > > > > > > The memory ordering constraint I am concerned about here is: > > > > > > * [...] In addition, > > > * each CPU having an SRCU read-side critical section that extends beyond > > > * the return from synchronize_srcu() is guaranteed to have executed a > > > * full memory barrier after the beginning of synchronize_srcu() and before > > > * the beginning of that SRCU read-side critical section. [...] > > > > > > So if we have a SRCU read-side critical section that begins after the beginning > > > of synchronize_srcu, but before its first memory barrier, it would miss the > > > guarantee that the full memory barrier is issued before the beginning of that > > > SRCU read-side critical section. IOW, that memory barrier needs to be at the > > > very beginning of the grace period. > > > > I'm confused, what's wrong with this ? > > > > UPDATER READER > > ------- ------ > > STORE X = 1 STORE srcu_read_lock++ > > // rcu_seq_snap() smp_mb() > > smp_mb() READ X > > // scans > > READ srcu_read_lock > > What you refer to here is only memory ordering of the store to X and load > from X wrt loading/increment of srcu_read_lock, which is internal to the > srcu implementation. If we really want to model the provided high-level > memory ordering guarantees, we should consider a scenario where SRCU is used > for its memory ordering properties to synchronize other variables. > > I'm concerned about the following Dekker scenario, where synchronize_srcu() > and srcu_read_lock/unlock would be used instead of memory barriers: > > Initial state: X = 0, Y = 0 > > Thread A Thread B > --------------------------------------------- > STORE X = 1 STORE Y = 1 > synchronize_srcu() > srcu_read_lock() > r1 = LOAD X > srcu_read_unlock() > r0 = LOAD Y > > BUG_ON(!r0 && !r1) > > So in the synchronize_srcu implementation, there appears to be two > major scenarios: either srcu_gp_start_if_needed starts a gp or expedited gp, > or it uses an already started gp/expedited gp. When snapshotting with > rcu_seq_snap, the fact that the memory barrier is after the ssp->srcu_gp_seq > load means that it does not order prior memory accesses before that load. > This sequence value is then used to identify which gp_seq to wait for when > piggy-backing on another already-started gp. I worry about reordering > between STORE X = 1 and load of ssp->srcu_gp_seq, which is then used to > piggy-back on an already-started gp. > > I suspect that the implicit barrier in srcu_read_lock() invoked at the > beginning of srcu_gp_start_if_needed() is really the barrier that makes > all this behave as expected. But without documentation it's rather hard to > follow. Oh ok I see now. It might be working that way by accident or on forgotten purpose. In any case, we really want to add a comment above that __srcu_read_lock_nmisafe() call.