From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0154C38142 for ; Fri, 20 Jan 2023 00:46:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229749AbjATAqq (ORCPT ); Thu, 19 Jan 2023 19:46:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229513AbjATAql (ORCPT ); Thu, 19 Jan 2023 19:46:41 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0CFE93730 for ; Thu, 19 Jan 2023 16:46:26 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id dw9so4126717pjb.5 for ; Thu, 19 Jan 2023 16:46:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=P1wnVSZdra+euEs7ZvKDTGyvbT6g6viojgbgmEshJwE=; b=mrcA3bRAfRsxg962kSM9tEKDUYTUg47gO03Fl0Kq0/nsxlmmWfudI9OPr3V0fBBN0q SOzp5bOcdDI4N4u4dxAv+c+bS+x2EUsiZbZAmFpmxaL/enWKLIir3E2hUYb3nH5vK5M+ 226Z4Y5MF/vfMm5VHfAHPVavGegauof4l6Q7A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=P1wnVSZdra+euEs7ZvKDTGyvbT6g6viojgbgmEshJwE=; b=hCQoYi0dDZoDj1PkBl0p6q94WPLx0BT485sXD+s0Jf86Ubg7rPgqhWg1syGEdSLfhO KbQgPvFARsqH33vNNsJGEjfeqAENCeXGIPEZX3hhtKr4irrUK7UH51afj8kynLSt2Zop 1+bPcLCt7O6zz2EdPs7i7ffvZ2+RShPuuCfFEDf+zSrGSSl7A5PTQD0Bx8PvpR8TLg1V VI2fXalRsqx2VlEQxCIFb/atwa/AQUJOQHlZVItsNrMH+X6O2/yF5X1eksyYkHmTyHqN i4b7K1Yift2e2DGnVJybVBLejouXcaKBsV6+xULh+na7p8HmEq1ktZShqIh0QyYnzLTl BjRQ== X-Gm-Message-State: AFqh2krXTbDGIZVxXbV+/pbxG+xTMagKTc+vsbYus4u+icl0HBAqcv3p 3fYvBN26qx6ceHdjONV1iZNY1Q== X-Google-Smtp-Source: AMrXdXvz4LrAbyOlE6ugjAl0CAgWr/m2tS2CGoI+FfZesn3j5vlMIGe5u5ya9NwlUhOtYRWYqiuS0g== X-Received: by 2002:a17:902:b60e:b0:192:8b0e:98e1 with SMTP id b14-20020a170902b60e00b001928b0e98e1mr12059970pls.54.1674175586170; Thu, 19 Jan 2023 16:46:26 -0800 (PST) Received: from www.outflux.net (smtp.outflux.net. [198.145.64.163]) by smtp.gmail.com with ESMTPSA id w9-20020a1709026f0900b00194b3a7853esm4528706plk.181.2023.01.19.16.46.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 16:46:25 -0800 (PST) Date: Thu, 19 Jan 2023 16:46:24 -0800 From: Kees Cook To: Rick Edgecombe Cc: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , Weijiang Yang , "Kirill A . Shutemov" , John Allen , kcc@google.com, eranian@google.com, rppt@kernel.org, jamorris@linux.microsoft.com, dethoma@microsoft.com, akpm@linux-foundation.org, Andrew.Cooper3@citrix.com, christina.schimpe@intel.com, Yu-cheng Yu Subject: Re: [PATCH v5 04/39] x86/cpufeatures: Enable CET CR4 bit for shadow stack Message-ID: <202301191646.E739868F@keescook> References: <20230119212317.8324-1-rick.p.edgecombe@intel.com> <20230119212317.8324-5-rick.p.edgecombe@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230119212317.8324-5-rick.p.edgecombe@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 19, 2023 at 01:22:42PM -0800, Rick Edgecombe wrote: > From: Yu-cheng Yu > > Setting CR4.CET is a prerequisite for utilizing any CET features, most of > which also require setting MSRs. > > Kernel IBT already enables the CET CR4 bit when it detects IBT HW support > and is configured with kernel IBT. However, future patches that enable > userspace shadow stack support will need the bit set as well. So change > the logic to enable it in either case. > > Clear MSR_IA32_U_CET in cet_disable() so that it can't live to see > userspace in a new kexec-ed kernel that has CR4.CET set from kernel IBT. > > Tested-by: Pengfei Xu > Tested-by: John Allen > Signed-off-by: Yu-cheng Yu Reviewed-by: Kees Cook -- Kees Cook