From: Anup Patel <apatel@ventanamicro.com>
To: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atishp@atishpatra.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v2 3/7] RISC-V: KVM: Drop the _MASK suffix from hgatp.VMID mask defines
Date: Sat, 28 Jan 2023 12:57:33 +0530 [thread overview]
Message-ID: <20230128072737.2995881-4-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230128072737.2995881-1-apatel@ventanamicro.com>
The hgatp.VMID mask defines are used before shifting when extracting
VMID value from hgatp CSR value so based on the convention followed
in the other parts of asm/csr.h, the hgatp.VMID mask defines should
not have a _MASK suffix.
While we are here, let's use GENMASK() for hgatp.VMID and hgatp.PPN.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/include/asm/csr.h | 12 ++++++------
arch/riscv/kvm/mmu.c | 3 +--
arch/riscv/kvm/vmid.c | 4 ++--
3 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 3c8d68152bce..3176355cf4e9 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -131,25 +131,25 @@
#define HGATP32_MODE_SHIFT 31
#define HGATP32_VMID_SHIFT 22
-#define HGATP32_VMID_MASK _AC(0x1FC00000, UL)
-#define HGATP32_PPN _AC(0x003FFFFF, UL)
+#define HGATP32_VMID GENMASK(28, 22)
+#define HGATP32_PPN GENMASK(21, 0)
#define HGATP64_MODE_SHIFT 60
#define HGATP64_VMID_SHIFT 44
-#define HGATP64_VMID_MASK _AC(0x03FFF00000000000, UL)
-#define HGATP64_PPN _AC(0x00000FFFFFFFFFFF, UL)
+#define HGATP64_VMID GENMASK(57, 44)
+#define HGATP64_PPN GENMASK(43, 0)
#define HGATP_PAGE_SHIFT 12
#ifdef CONFIG_64BIT
#define HGATP_PPN HGATP64_PPN
#define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT
-#define HGATP_VMID_MASK HGATP64_VMID_MASK
+#define HGATP_VMID HGATP64_VMID
#define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT
#else
#define HGATP_PPN HGATP32_PPN
#define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT
-#define HGATP_VMID_MASK HGATP32_VMID_MASK
+#define HGATP_VMID HGATP32_VMID
#define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT
#endif
diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
index dbc4ca060174..829a7065ae01 100644
--- a/arch/riscv/kvm/mmu.c
+++ b/arch/riscv/kvm/mmu.c
@@ -748,8 +748,7 @@ void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu)
unsigned long hgatp = gstage_mode;
struct kvm_arch *k = &vcpu->kvm->arch;
- hgatp |= (READ_ONCE(k->vmid.vmid) << HGATP_VMID_SHIFT) &
- HGATP_VMID_MASK;
+ hgatp |= (READ_ONCE(k->vmid.vmid) << HGATP_VMID_SHIFT) & HGATP_VMID;
hgatp |= (k->pgd_phys >> PAGE_SHIFT) & HGATP_PPN;
csr_write(CSR_HGATP, hgatp);
diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c
index 6cd93995fb65..6f4d4979a759 100644
--- a/arch/riscv/kvm/vmid.c
+++ b/arch/riscv/kvm/vmid.c
@@ -26,9 +26,9 @@ void kvm_riscv_gstage_vmid_detect(void)
/* Figure-out number of VMID bits in HW */
old = csr_read(CSR_HGATP);
- csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
+ csr_write(CSR_HGATP, old | HGATP_VMID);
vmid_bits = csr_read(CSR_HGATP);
- vmid_bits = (vmid_bits & HGATP_VMID_MASK) >> HGATP_VMID_SHIFT;
+ vmid_bits = (vmid_bits & HGATP_VMID) >> HGATP_VMID_SHIFT;
vmid_bits = fls_long(vmid_bits);
csr_write(CSR_HGATP, old);
--
2.34.1
next prev parent reply other threads:[~2023-01-28 7:28 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-28 7:27 [PATCH v2 0/7] RISC-V KVM virtualize AIA CSRs Anup Patel
2023-01-28 7:27 ` [PATCH v2 1/7] RISC-V: Add AIA related CSR defines Anup Patel
2023-01-31 9:22 ` Atish Patra
2023-02-03 0:24 ` Palmer Dabbelt
2023-01-28 7:27 ` [PATCH v2 2/7] RISC-V: Detect AIA CSRs from ISA string Anup Patel
2023-01-31 9:25 ` Atish Patra
2023-02-03 0:24 ` Palmer Dabbelt
2023-02-03 12:01 ` Anup Patel
2023-02-07 18:05 ` Conor Dooley
2023-02-07 18:09 ` Conor Dooley
2023-02-07 18:15 ` Atish Patra
2023-02-07 20:39 ` Conor Dooley
2023-02-08 3:54 ` Anup Patel
2023-02-08 12:57 ` Conor Dooley
2023-02-08 14:57 ` Anup Patel
2023-02-09 23:31 ` Conor Dooley
2023-02-08 3:06 ` Anup Patel
2023-02-15 15:41 ` Christoph Müllner
2023-02-21 7:12 ` Christoph Müllner
2023-02-21 10:40 ` Conor Dooley
2023-02-21 10:51 ` Jessica Clarke
2023-02-21 10:59 ` Conor Dooley
2023-02-21 11:03 ` Christoph Müllner
2023-02-21 11:22 ` Conor Dooley
2023-03-31 12:53 ` Anup Patel
2023-01-28 7:27 ` Anup Patel [this message]
2023-01-31 9:27 ` [PATCH v2 3/7] RISC-V: KVM: Drop the _MASK suffix from hgatp.VMID mask defines Atish Patra
2023-01-28 7:27 ` [PATCH v2 4/7] RISC-V: KVM: Initial skeletal support for AIA Anup Patel
2023-01-31 9:51 ` Atish Patra
2023-01-28 7:27 ` [PATCH v2 5/7] RISC-V: KVM: Add ONE_REG interface for AIA CSRs Anup Patel
2023-02-08 0:04 ` Atish Patra
2023-03-31 17:15 ` Anup Patel
2023-01-28 7:27 ` [PATCH v2 6/7] RISC-V: KVM: Virtualize per-HART " Anup Patel
2023-01-28 7:27 ` [PATCH v2 7/7] RISC-V: KVM: Implement guest external interrupt line management Anup Patel
2023-02-08 0:15 ` Atish Patra
2023-03-31 17:15 ` Anup Patel
2023-01-31 6:01 ` [PATCH v2 0/7] RISC-V KVM virtualize AIA CSRs Anup Patel
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