Re: [PATCH net-next v3 3/3] net: dsa: rzn1-a5psw: add vlan support

Clément Léger
2023-02-09T08:45:13Z

Le Thu, 9 Feb 2023 00:03:09 +0200,
Vladimir Oltean <olteanv@gmail.com> a écrit :

> On Wed, Feb 08, 2023 at 05:17:49PM +0100, Clément Léger wrote:
> > +static void a5psw_port_vlan_tagged_cfg(struct a5psw *a5psw, int vlan_res_id,
> > + int port, bool set)
> > +{
> > + u32 mask = A5PSW_VLAN_RES_WR_PORTMASK | A5PSW_VLAN_RES_RD_TAGMASK |
> > + BIT(port);
> > + u32 vlan_res_off = A5PSW_VLAN_RES(vlan_res_id);
> > + u32 val = A5PSW_VLAN_RES_WR_TAGMASK, reg;
> > +
> > + if (set)
> > + val |= BIT(port);
> > +
> > + /* Toggle tag mask read */
> > + a5psw_reg_writel(a5psw, vlan_res_off, A5PSW_VLAN_RES_RD_TAGMASK);
> > + reg = a5psw_reg_readl(a5psw, vlan_res_off);
> > + a5psw_reg_writel(a5psw, vlan_res_off, A5PSW_VLAN_RES_RD_TAGMASK);
>
> Is it intentional that this register is written twice?

Yes, the A5PSW_VLAN_RES_RD_TAGMASK bit is a toggle-bit (toggled
by writing a 1 in it) and it allows to read the tagmask (for
vlan tagging) instead of the portmask (for vlan membership):

"""
b28 read_tagmask:

Select contents of mask bits (4:0) when reading the
register. If this bit is set during a write into the register, all
other bits of the write are ignored (i.e. 30,29,16:0) and the bit 28 of
the register toggles (1-> 0; 0-> 1). This is used only to allow
changing the bit 28 without changing any table contents.
"""

>
> > +
> > + reg &= ~mask;
> > + reg |= val;
> > + a5psw_reg_writel(a5psw, vlan_res_off, reg);
> > +}

--
Clément Léger,
Embedded Linux and Kernel engineer at Bootlin