Re: [PATCH v2 07/13] ARM: dts: qcom: sdx55: Add support for PCIe RC controller

Konrad Dybcio
2023-02-27T09:10:02Z

On 24.02.2023 11:59, Manivannan Sadhasivam wrote:
> The PCIe controller in SDX55 can act as the RC controller also. Let's
> add support for it.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
> arch/arm/boot/dts/qcom-sdx55.dtsi | 82 +++++++++++++++++++++++++++++++
> 1 file changed, 82 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
> index a1f4a7b0904a..b411c4ae34c3 100644
> --- a/arch/arm/boot/dts/qcom-sdx55.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
> @@ -303,6 +303,88 @@ qpic_nand: nand-controller@1b30000 {
> status = "disabled";
> };
>
> + pcie_rc: pcie@1c00000 {
> + compatible = "qcom,pcie-sdx55";
> + reg = <0x01c00000 0x3000>,
> + <0x40000000 0xf1d>,
> + <0x40000f20 0xc8>,
> + <0x40001000 0x1000>,
> + <0x40100000 0x100000>;
> + reg-names = "parf",
> + "dbi",
> + "elbi",
> + "atu",
> + "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
> + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
> +
> + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi",
> + "msi2",
> + "msi3",
> + "msi4",
> + "msi5",
> + "msi6",
> + "msi7",
> + "msi8";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> + clocks = <&gcc GCC_PCIE_PIPE_CLK>,
> + <&gcc GCC_PCIE_AUX_CLK>,
> + <&gcc GCC_PCIE_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_PCIE_SLEEP_CLK>;
> + clock-names = "pipe",
> + "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "sleep";
> +
> + assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + iommus = <&apps_smmu 0x0200 0x0f>;
> + iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
> + <0x100 &apps_smmu 0x0201 0x1>,
> + <0x200 &apps_smmu 0x0202 0x1>,
> + <0x300 &apps_smmu 0x0203 0x1>,
> + <0x400 &apps_smmu 0x0204 0x1>;
> +
> + resets = <&gcc GCC_PCIE_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc PCIE_GDSC>;
> +
> + phys = <&pcie_lane>;
> + phy-names = "pciephy";
> +
> + status = "disabled";
> + };
> +
> pcie_ep: pcie-ep@1c00000 {
> compatible = "qcom,sdx55-pcie-ep";
> reg = <0x01c00000 0x3000>,