[PATCH 0/6] Add PCIe EP support for SDX65

[PATCH 0/6] Add PCIe EP support for SDX65

[Rohit Agarwal]

Hi,

This series adds the devicetree support for PCIe PHY and PCIe EP on SDX65.
The PCIe EP is enabled on SDX65 MTP board.

Thanks,
Rohit.

Rohit Agarwal (6):
  dt-bindings: mfd: qcom,tcsr: Add compatible for sdx65
  dt-bindings: PCI: qcom: Add SDX65 SoC
  ARM: dts: qcom: sdx65: Add support for PCIe PHY
  ARM: dts: qcom: sdx65: Add support for PCIe EP
  ARM: dts: qcom: sdx65-mtp: Enable PCIE0 PHY
  ARM: dts: qcom: sdx65-mtp: Enable PCIe EP

 .../devicetree/bindings/mfd/qcom,tcsr.yaml         |  1 +
 .../devicetree/bindings/pci/qcom,pcie-ep.yaml      |  2 +
 arch/arm/boot/dts/qcom-sdx65-mtp.dts               | 53 +++++++++++++++
 arch/arm/boot/dts/qcom-sdx65.dtsi                  | 76 ++++++++++++++++++++++
 4 files changed, 132 insertions(+)

-- 
2.7.4

[PATCH 1/6] dt-bindings: mfd: qcom,tcsr: Add compatible for sdx65

[Rohit Agarwal]

Add the qcom,sdx65-tcsr compatible.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
index adcae6c..01f2f2f 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
@@ -25,6 +25,7 @@ properties:
           - qcom,sc8280xp-tcsr
           - qcom,sdm630-tcsr
           - qcom,sdm845-tcsr
+          - qcom,sdx65-tcsr
           - qcom,sm8150-tcsr
           - qcom,tcsr-apq8064
           - qcom,tcsr-apq8084
-- 
2.7.4

[PATCH 2/6] dt-bindings: PCI: qcom: Add SDX65 SoC

[Rohit Agarwal]

Add PCIe EP compatible string for SDX65 SoC.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index 8d7eb51..6c864e2 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -13,6 +13,7 @@ properties:
   compatible:
     enum:
       - qcom,sdx55-pcie-ep
+      - qcom,sdx65-pcie-ep
       - qcom,sm8450-pcie-ep
 
   reg:
@@ -107,6 +108,7 @@ allOf:
           contains:
             enum:
               - qcom,sdx55-pcie-ep
+              - qcom,sdx65-pcie-ep
     then:
       properties:
         clocks:
-- 
2.7.4

[PATCH 3/6] ARM: dts: qcom: sdx65: Add support for PCIe PHY

[Rohit Agarwal]

Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
used by the PCIe EP controller.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm/boot/dts/qcom-sdx65.dtsi | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index b073e0c..246290d 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -292,6 +292,38 @@
 			status = "disabled";
 		};
 
+		pcie0_phy: phy@1c07000 {
+			compatible = "qcom,sdx65-qmp-pcie-phy";
+			reg = <0x01c07000 0x1e4>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
+				 <&gcc GCC_PCIE_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_0_CLKREF_EN>,
+				 <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+			clock-names = "aux", "cfg_ahb", "ref", "refgen";
+
+			resets = <&gcc GCC_PCIE_PHY_BCR>;
+			reset-names = "phy";
+			assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+
+			pcie0_lane: lanes@1c06000 {
+				reg = <0x01c06000 0xf0>, /* tx0 */
+				      <0x01c06200 0x2f0>, /* rx0 */
+				      <0x01c07200 0x1e8>, /* pcs */
+				      <0x01c06800 0xf0>, /* tx1 */
+				      <0x01c06a00 0x2f0>, /* rx1 */
+				      <0x01c07400 0xc00>; /* pcs_misc */
+				clocks = <&gcc GCC_PCIE_PIPE_CLK>;
+				clock-names = "pipe0";
+				#phy-cells = <0>;
+				clock-output-names = "pcie_pipe_clk";
+			};
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex";
 			reg = <0x01f40000 0x40000>;
-- 
2.7.4

[PATCH 4/6] ARM: dts: qcom: sdx65: Add support for PCIe EP

[Rohit Agarwal]

Add support for PCIe Endpoint controller on the Qualcomm SDX65 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm/boot/dts/qcom-sdx65.dtsi | 44 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 246290d..93ea94e 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	#address-cells = <1>;
@@ -292,6 +293,44 @@
 			status = "disabled";
 		};
 
+		pcie_ep: pcie-ep@1c00000 {
+			compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
+			reg = <0x01c00000 0x3000>,
+				  <0x40000000 0xf1d>,
+				  <0x40000f20 0xa8>,
+				  <0x40001000 0x1000>,
+				  <0x40200000 0x100000>,
+				  <0x01c03000 0x3000>;
+			reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
+						"mmio";
+
+			qcom,perst-regs = <&tcsr 0xb258 0xb270>;
+
+			clocks = <&gcc GCC_PCIE_AUX_CLK>,
+					 <&gcc GCC_PCIE_CFG_AHB_CLK>,
+					 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+					 <&gcc GCC_PCIE_SLV_AXI_CLK>,
+					 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+					 <&gcc GCC_PCIE_SLEEP_CLK>,
+					 <&gcc GCC_PCIE_0_CLKREF_EN>;
+			clock-names = "aux", "cfg", "bus_master", "bus_slave",
+							"slave_q2a", "sleep", "ref";
+
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+						 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "global", "doorbell";
+			reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+			wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
+			resets = <&gcc GCC_PCIE_BCR>;
+			reset-names = "core";
+			power-domains = <&gcc PCIE_GDSC>;
+			phys = <&pcie0_lane>;
+			phy-names = "pciephy";
+			max-link-speed = <3>;
+			num-lanes = <2>;
+			status = "disabled";
+		};
+
 		pcie0_phy: phy@1c07000 {
 			compatible = "qcom,sdx65-qmp-pcie-phy";
 			reg = <0x01c07000 0x1e4>;
@@ -330,6 +369,11 @@
 			#hwlock-cells = <1>;
 		};
 
+		tcsr: syscon@1fcb000 {
+			compatible = "qcom,sdx65-tcsr", "syscon";
+			reg = <0x01fc0000 0x1000>;
+		};
+
 		remoteproc_mpss: remoteproc@4080000 {
 			compatible = "qcom,sdx55-mpss-pas";
 			reg = <0x04080000 0x4040>;
-- 
2.7.4

[PATCH 5/6] ARM: dts: qcom: sdx65-mtp: Enable PCIE0 PHY

[Rohit Agarwal]

Enable PCIE0 PHY on SDX65 MTP for PCIE EP.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm/boot/dts/qcom-sdx65-mtp.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index 85ea02d..86bb853 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -245,6 +245,13 @@
 	status = "okay";
 };
 
+&pcie0_phy {
+	status = "okay";
+
+	vdda-phy-supply = <&vreg_l1b_1p2>;
+	vdda-pll-supply = <&vreg_l4b_0p88>;
+};
+
 &qpic_bam {
 	status = "okay";
 };
-- 
2.7.4

[PATCH 6/6] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP

[Rohit Agarwal]

Enable PCIe Endpoint controller on the SDX65 MTP board based
on Qualcomm SDX65 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm/boot/dts/qcom-sdx65-mtp.dts | 46 ++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index 86bb853..952de105 100644
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -252,6 +252,14 @@
 	vdda-pll-supply = <&vreg_l4b_0p88>;
 };
 
+&pcie_ep {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
+			&pcie_ep_wake_default>;
+};
+
 &qpic_bam {
 	status = "okay";
 };
@@ -276,6 +284,44 @@
 	memory-region = <&mpss_adsp_mem>;
 };
 
++&tlmm {
+	pcie_ep_clkreq_default: pcie_ep_clkreq_default {
+		mux {
+			pins = "gpio56";
+			function = "pcie_clkreq";
+		};
+		config {
+			pins = "gpio56";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+
+	pcie_ep_perst_default: pcie_ep_perst_default {
+		mux {
+			pins = "gpio57";
+			function = "gpio";
+		};
+		config {
+			pins = "gpio57";
+			drive-strength = <2>;
+			bias-pull-down;
+		};
+	};
+
+	pcie_ep_wake_default: pcie_ep_wake_default {
+		mux {
+			pins = "gpio53";
+			function = "gpio";
+		};
+		config {
+			pins = "gpio53";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+};
+
 &usb {
 	status = "okay";
 };
-- 
2.7.4

Re: [PATCH 1/6] dt-bindings: mfd: qcom,tcsr: Add compatible for sdx65

[Krzysztof Kozlowski]

On 06/03/2023 06:24, Rohit Agarwal wrote:
> Add the qcom,sdx65-tcsr compatible.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
>  Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 2/6] dt-bindings: PCI: qcom: Add SDX65 SoC

[Krzysztof Kozlowski]

On 06/03/2023 06:24, Rohit Agarwal wrote:
> Add PCIe EP compatible string for SDX65 SoC.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 3/6] ARM: dts: qcom: sdx65: Add support for PCIe PHY

[Dmitry Baryshkov]

On 06/03/2023 07:24, Rohit Agarwal wrote:
> Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
> used by the PCIe EP controller.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
>   arch/arm/boot/dts/qcom-sdx65.dtsi | 32 ++++++++++++++++++++++++++++++++
>   1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index b073e0c..246290d 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -292,6 +292,38 @@
>   			status = "disabled";
>   		};
>   
> +		pcie0_phy: phy@1c07000 {
> +			compatible = "qcom,sdx65-qmp-pcie-phy";
> +			reg = <0x01c07000 0x1e4>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
> +				 <&gcc GCC_PCIE_CFG_AHB_CLK>,
> +				 <&gcc GCC_PCIE_0_CLKREF_EN>,
> +				 <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
> +			clock-names = "aux", "cfg_ahb", "ref", "refgen";
> +
> +			resets = <&gcc GCC_PCIE_PHY_BCR>;
> +			reset-names = "phy";
> +			assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +
> +			pcie0_lane: lanes@1c06000 {

Please use new style bindings found in qcom,sc8280xp-qmp-pcie-phy.yaml

> +				reg = <0x01c06000 0xf0>, /* tx0 */
> +				      <0x01c06200 0x2f0>, /* rx0 */
> +				      <0x01c07200 0x1e8>, /* pcs */
> +				      <0x01c06800 0xf0>, /* tx1 */
> +				      <0x01c06a00 0x2f0>, /* rx1 */
> +				      <0x01c07400 0xc00>; /* pcs_misc */
> +				clocks = <&gcc GCC_PCIE_PIPE_CLK>;
> +				clock-names = "pipe0";
> +				#phy-cells = <0>;
> +				clock-output-names = "pcie_pipe_clk";
> +			};
> +		};
> +
>   		tcsr_mutex: hwlock@1f40000 {
>   			compatible = "qcom,tcsr-mutex";
>   			reg = <0x01f40000 0x40000>;

-- 
With best wishes
Dmitry

Re: [PATCH 5/6] ARM: dts: qcom: sdx65-mtp: Enable PCIE0 PHY

[Konrad Dybcio]

On 6.03.2023 06:25, Rohit Agarwal wrote:
> Enable PCIE0 PHY on SDX65 MTP for PCIE EP.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
Status should go last. It would be nice if you could update
that for the other nodes in this dt while at it.

Konrad
>  arch/arm/boot/dts/qcom-sdx65-mtp.dts | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> index 85ea02d..86bb853 100644
> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> @@ -245,6 +245,13 @@
>  	status = "okay";
>  };
>  
> +&pcie0_phy {
> +	status = "okay";
> +
> +	vdda-phy-supply = <&vreg_l1b_1p2>;
> +	vdda-pll-supply = <&vreg_l4b_0p88>;
> +};
> +
>  &qpic_bam {
>  	status = "okay";
>  };

Re: [PATCH 6/6] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP

[Konrad Dybcio]

On 6.03.2023 06:25, Rohit Agarwal wrote:
> Enable PCIe Endpoint controller on the SDX65 MTP board based
> on Qualcomm SDX65 platform.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
>  arch/arm/boot/dts/qcom-sdx65-mtp.dts | 46 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> index 86bb853..952de105 100644
> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
> @@ -252,6 +252,14 @@
>  	vdda-pll-supply = <&vreg_l4b_0p88>;
>  };
>  
> +&pcie_ep {
> +	status = "okay";
> +
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
> +			&pcie_ep_wake_default>;
status last

pinctrl-n goes before pinctrl-names
> +};
> +
>  &qpic_bam {
>  	status = "okay";
>  };
> @@ -276,6 +284,44 @@
>  	memory-region = <&mpss_adsp_mem>;
>  };
>  
> ++&tlmm {
> +	pcie_ep_clkreq_default: pcie_ep_clkreq_default {
No underscores in node names, pinctrl children node names
must end in -state. Please check your patches against
"make dtbs_check"
> +		mux {
> +			pins = "gpio56";
> +			function = "pcie_clkreq";
> +		};
> +		config {
> +			pins = "gpio56";
> +			drive-strength = <2>;
> +			bias-disable;
> +		};
mux {} / config {} is unnecessary. You can simply do:

{
    pins = "gpio56";
    function = "pcie_clkreq";
    drive-strength = <2>;
    bias-disable;
};

Konrad
> +	};
> +
> +	pcie_ep_perst_default: pcie_ep_perst_default {
> +		mux {
> +			pins = "gpio57";
> +			function = "gpio";
> +		};
> +		config {
> +			pins = "gpio57";
> +			drive-strength = <2>;
> +			bias-pull-down;
> +		};
> +	};
> +
> +	pcie_ep_wake_default: pcie_ep_wake_default {
> +		mux {
> +			pins = "gpio53";
> +			function = "gpio";
> +		};
> +		config {
> +			pins = "gpio53";
> +			drive-strength = <2>;
> +			bias-disable;
> +		};
> +	};
> +};
> +
>  &usb {
>  	status = "okay";
>  };

Re: [PATCH 4/6] ARM: dts: qcom: sdx65: Add support for PCIe EP

[Konrad Dybcio]

On 6.03.2023 06:25, Rohit Agarwal wrote:
> Add support for PCIe Endpoint controller on the Qualcomm SDX65 platform.
> 
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
> ---
>  arch/arm/boot/dts/qcom-sdx65.dtsi | 44 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 246290d..93ea94e 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -11,6 +11,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/power/qcom-rpmpd.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/gpio/gpio.h>
>  
>  / {
>  	#address-cells = <1>;
> @@ -292,6 +293,44 @@
>  			status = "disabled";
>  		};
>  
> +		pcie_ep: pcie-ep@1c00000 {
> +			compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
> +			reg = <0x01c00000 0x3000>,
> +				  <0x40000000 0xf1d>,
> +				  <0x40000f20 0xa8>,
> +				  <0x40001000 0x1000>,
> +				  <0x40200000 0x100000>,
> +				  <0x01c03000 0x3000>;
The indentation here seems incorrect. The kernel uses 8-wide tabs.

> +			reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
> +						"mmio";
Please turn this into a vertical list, like this:

"parf",
"dbi",
...

> +
> +			qcom,perst-regs = <&tcsr 0xb258 0xb270>;
> +
> +			clocks = <&gcc GCC_PCIE_AUX_CLK>,
> +					 <&gcc GCC_PCIE_CFG_AHB_CLK>,
> +					 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
> +					 <&gcc GCC_PCIE_SLV_AXI_CLK>,
> +					 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
> +					 <&gcc GCC_PCIE_SLEEP_CLK>,
> +					 <&gcc GCC_PCIE_0_CLKREF_EN>;
The indentation here seems incorrect.

> +			clock-names = "aux", "cfg", "bus_master", "bus_slave",
> +							"slave_q2a", "sleep", "ref";
Please turn this into a vertical list too.

> +
> +			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> +						 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
The indentation seems off here.

Konrad
> +			interrupt-names = "global", "doorbell";
> +			reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
> +			wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
> +			resets = <&gcc GCC_PCIE_BCR>;
> +			reset-names = "core";
> +			power-domains = <&gcc PCIE_GDSC>;
> +			phys = <&pcie0_lane>;
> +			phy-names = "pciephy";
> +			max-link-speed = <3>;
> +			num-lanes = <2>;
> +			status = "disabled";
> +		};
> +
>  		pcie0_phy: phy@1c07000 {
>  			compatible = "qcom,sdx65-qmp-pcie-phy";
>  			reg = <0x01c07000 0x1e4>;
> @@ -330,6 +369,11 @@
>  			#hwlock-cells = <1>;
>  		};
>  
> +		tcsr: syscon@1fcb000 {
> +			compatible = "qcom,sdx65-tcsr", "syscon";
> +			reg = <0x01fc0000 0x1000>;
> +		};
> +
>  		remoteproc_mpss: remoteproc@4080000 {
>  			compatible = "qcom,sdx55-mpss-pas";
>  			reg = <0x04080000 0x4040>;

Re: [PATCH 3/6] ARM: dts: qcom: sdx65: Add support for PCIe PHY

[Rohit Agarwal]

On 3/6/2023 2:11 PM, Dmitry Baryshkov wrote:
> On 06/03/2023 07:24, Rohit Agarwal wrote:
>> Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
>> used by the PCIe EP controller.
>>
>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
>> ---
>>   arch/arm/boot/dts/qcom-sdx65.dtsi | 32 
>> ++++++++++++++++++++++++++++++++
>>   1 file changed, 32 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi 
>> b/arch/arm/boot/dts/qcom-sdx65.dtsi
>> index b073e0c..246290d 100644
>> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
>> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
>> @@ -292,6 +292,38 @@
>>               status = "disabled";
>>           };
>>   +        pcie0_phy: phy@1c07000 {
>> +            compatible = "qcom,sdx65-qmp-pcie-phy";
>> +            reg = <0x01c07000 0x1e4>;
>> +            #address-cells = <1>;
>> +            #size-cells = <1>;
>> +            ranges;
>> +            clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
>> +                 <&gcc GCC_PCIE_CFG_AHB_CLK>,
>> +                 <&gcc GCC_PCIE_0_CLKREF_EN>,
>> +                 <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
>> +            clock-names = "aux", "cfg_ahb", "ref", "refgen";
>> +
>> +            resets = <&gcc GCC_PCIE_PHY_BCR>;
>> +            reset-names = "phy";
>> +            assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
>> +            assigned-clock-rates = <100000000>;
>> +            status = "disabled";
>> +
>> +            pcie0_lane: lanes@1c06000 {
>
> Please use new style bindings found in qcom,sc8280xp-qmp-pcie-phy.yaml

Sure, Will update it the bindings and this.

Thanks,
Rohit.
>
>> +                reg = <0x01c06000 0xf0>, /* tx0 */
>> +                      <0x01c06200 0x2f0>, /* rx0 */
>> +                      <0x01c07200 0x1e8>, /* pcs */
>> +                      <0x01c06800 0xf0>, /* tx1 */
>> +                      <0x01c06a00 0x2f0>, /* rx1 */
>> +                      <0x01c07400 0xc00>; /* pcs_misc */
>> +                clocks = <&gcc GCC_PCIE_PIPE_CLK>;
>> +                clock-names = "pipe0";
>> +                #phy-cells = <0>;
>> +                clock-output-names = "pcie_pipe_clk";
>> +            };
>> +        };
>> +
>>           tcsr_mutex: hwlock@1f40000 {
>>               compatible = "qcom,tcsr-mutex";
>>               reg = <0x01f40000 0x40000>;
>

Re: [PATCH 5/6] ARM: dts: qcom: sdx65-mtp: Enable PCIE0 PHY

[Rohit Agarwal]

On 3/6/2023 4:00 PM, Konrad Dybcio wrote:
>
> On 6.03.2023 06:25, Rohit Agarwal wrote:
>> Enable PCIE0 PHY on SDX65 MTP for PCIE EP.
>>
>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
>> ---
> Status should go last. It would be nice if you could update
> that for the other nodes in this dt while at it.

Yes, Surely will do.

Thanks,
Rohit.
>
> Konrad
>>   arch/arm/boot/dts/qcom-sdx65-mtp.dts | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> index 85ea02d..86bb853 100644
>> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> @@ -245,6 +245,13 @@
>>   	status = "okay";
>>   };
>>   
>> +&pcie0_phy {
>> +	status = "okay";
>> +
>> +	vdda-phy-supply = <&vreg_l1b_1p2>;
>> +	vdda-pll-supply = <&vreg_l4b_0p88>;
>> +};
>> +
>>   &qpic_bam {
>>   	status = "okay";
>>   };

Re: [PATCH 6/6] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP

[Rohit Agarwal]

On 3/6/2023 4:02 PM, Konrad Dybcio wrote:
>
> On 6.03.2023 06:25, Rohit Agarwal wrote:
>> Enable PCIe Endpoint controller on the SDX65 MTP board based
>> on Qualcomm SDX65 platform.
>>
>> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
>> ---
>>   arch/arm/boot/dts/qcom-sdx65-mtp.dts | 46 ++++++++++++++++++++++++++++++++++++
>>   1 file changed, 46 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> index 86bb853..952de105 100644
>> --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
>> @@ -252,6 +252,14 @@
>>   	vdda-pll-supply = <&vreg_l4b_0p88>;
>>   };
>>   
>> +&pcie_ep {
>> +	status = "okay";
>> +
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
>> +			&pcie_ep_wake_default>;
> status last
>
> pinctrl-n goes before pinctrl-names
>> +};
>> +
>>   &qpic_bam {
>>   	status = "okay";
>>   };
>> @@ -276,6 +284,44 @@
>>   	memory-region = <&mpss_adsp_mem>;
>>   };
>>   
>> ++&tlmm {
>> +	pcie_ep_clkreq_default: pcie_ep_clkreq_default {
> No underscores in node names, pinctrl children node names
> must end in -state. Please check your patches against
> "make dtbs_check"
>> +		mux {
>> +			pins = "gpio56";
>> +			function = "pcie_clkreq";
>> +		};
>> +		config {
>> +			pins = "gpio56";
>> +			drive-strength = <2>;
>> +			bias-disable;
>> +		};
> mux {} / config {} is unnecessary. You can simply do:
>
> {
>      pins = "gpio56";
>      function = "pcie_clkreq";
>      drive-strength = <2>;
>      bias-disable;
> };
Thanks for detailed explanation. Will rectify all in the next version.

Thanks,
Rohit.
> Konrad
>> +	};
>> +
>> +	pcie_ep_perst_default: pcie_ep_perst_default {
>> +		mux {
>> +			pins = "gpio57";
>> +			function = "gpio";
>> +		};
>> +		config {
>> +			pins = "gpio57";
>> +			drive-strength = <2>;
>> +			bias-pull-down;
>> +		};
>> +	};
>> +
>> +	pcie_ep_wake_default: pcie_ep_wake_default {
>> +		mux {
>> +			pins = "gpio53";
>> +			function = "gpio";
>> +		};
>> +		config {
>> +			pins = "gpio53";
>> +			drive-strength = <2>;
>> +			bias-disable;
>> +		};
>> +	};
>> +};
>> +
>>   &usb {
>>   	status = "okay";
>>   };

Re: [PATCH 6/6] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP

[kernel test robot]

Hi Rohit,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on lee-mfd/for-mfd-next lee-mfd/for-mfd-fixes pci/next pci/for-linus linus/master v6.3-rc1 next-20230306]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Rohit-Agarwal/dt-bindings-mfd-qcom-tcsr-Add-compatible-for-sdx65/20230306-132618
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/1678080302-29691-7-git-send-email-quic_rohiagar%40quicinc.com
patch subject: [PATCH 6/6] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP
config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20230307/202303071612.HZ9bDCp7-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/51b8272710554bf9cbee6604f73951179e85ffa7
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Rohit-Agarwal/dt-bindings-mfd-qcom-tcsr-Add-compatible-for-sdx65/20230306-132618
        git checkout 51b8272710554bf9cbee6604f73951179e85ffa7
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm olddefconfig
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202303071612.HZ9bDCp7-lkp@intel.com/

All errors (new ones prefixed by >>):

>> Error: arch/arm/boot/dts/qcom-sdx65-mtp.dts:287.1-2 syntax error
   FATAL ERROR: Unable to parse input tree

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests