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Wed, 08 Mar 2023 00:32:50 -0800 (PST) Received: from thinkpad ([59.97.52.140]) by smtp.gmail.com with ESMTPSA id q15-20020a170902f78f00b001948ff5cc32sm9414443pln.215.2023.03.08.00.32.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 00:32:50 -0800 (PST) Date: Wed, 8 Mar 2023 14:02:44 +0530 From: Manivannan Sadhasivam To: Johan Hovold Cc: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com Subject: Re: [PATCH 15/19] dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs Message-ID: <20230308083244.GE134293@thinkpad> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> <20230306153222.157667-16-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 06, 2023 at 05:49:44PM +0100, Johan Hovold wrote: > On Mon, Mar 06, 2023 at 09:02:18PM +0530, Manivannan Sadhasivam wrote: > > "mhi" register region contains the MHI registers that could be used by > > the PCIe controller drivers to get debug information like PCIe link > > transition counts on newer SoCs. > > > > Signed-off-by: Manivannan Sadhasivam > > --- > > Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 12 ++++++++---- > > 1 file changed, 8 insertions(+), 4 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > index fb32c43dd12d..2de6e7154025 100644 > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > @@ -44,11 +44,11 @@ properties: > > > > reg: > > minItems: 4 > > - maxItems: 5 > > + maxItems: 6 > > > > reg-names: > > minItems: 4 > > - maxItems: 5 > > + maxItems: 6 > > > > interrupts: > > minItems: 1 > > @@ -185,10 +185,12 @@ allOf: > > properties: > > reg: > > minItems: 4 > > - maxItems: 4 > > + maxItems: 5 > > reg-names: > > + minItems: 4 > > items: > > - const: parf # Qualcomm specific registers > > + - const: mhi # MHI registers > > You need to add the new (optional) registers at the end. > Will do it in next revision. Thanks, Mani > > - const: dbi # DesignWare PCIe registers > > - const: elbi # External local bus interface registers > > - const: config # PCIe configuration space > > Johan -- மணிவண்ணன் சதாசிவம்