[PATCH v3 17/19] arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes

Manivannan Sadhasivam
2023-03-10T04:12:10Z

The "mhi" region contains the debug registers that could be used to monitor
the PCIe link transitions.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 +++++++++++++++----------
1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 0d02599d8867..eb87c3e5d2bc 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1653,8 +1653,9 @@ pcie4: pcie@1c00000 {
<0x0 0x30000000 0x0 0xf1d>,
<0x0 0x30000f20 0x0 0xa8>,
<0x0 0x30001000 0x0 0x1000>,
- <0x0 0x30100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x30100000 0x0 0x100000>,
+ <0x0 0x01c03000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
@@ -1752,8 +1753,9 @@ pcie3b: pcie@1c08000 {
<0x0 0x32000000 0x0 0xf1d>,
<0x0 0x32000f20 0x0 0xa8>,
<0x0 0x32001000 0x0 0x1000>,
- <0x0 0x32100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x32100000 0x0 0x100000>,
+ <0x0 0x01c0b000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
@@ -1849,8 +1851,9 @@ pcie3a: pcie@1c10000 {
<0x0 0x34000000 0x0 0xf1d>,
<0x0 0x34000f20 0x0 0xa8>,
<0x0 0x34001000 0x0 0x1000>,
- <0x0 0x34100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x34100000 0x0 0x100000>,
+ <0x0 0x01c13000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
@@ -1949,8 +1952,9 @@ pcie2b: pcie@1c18000 {
<0x0 0x38000000 0x0 0xf1d>,
<0x0 0x38000f20 0x0 0xa8>,
<0x0 0x38001000 0x0 0x1000>,
- <0x0 0x38100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x38100000 0x0 0x100000>,
+ <0x0 0x01c1b000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
@@ -2046,8 +2050,9 @@ pcie2a: pcie@1c20000 {
<0x0 0x3c000000 0x0 0xf1d>,
<0x0 0x3c000f20 0x0 0xa8>,
<0x0 0x3c001000 0x0 0x1000>,
- <0x0 0x3c100000 0x0 0x100000>;
- reg-names = "parf", "dbi", "elbi", "atu", "config";
+ <0x0 0x3c100000 0x0 0x100000>,
+ <0x0 0x01c23000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
--
2.25.1