[RFC PATCH 08/14] arm64: Make the PHYS_MASK_SHIFT dynamic

Steven Price
2023-01-27T11:30:35Z

Make the PHYS_MASK_SHIFT dynamic for Realms. This is only is required
for masking the PFN from a pte entry. Elsewhere, we could still use the
PA bits configured by the kernel. So, this patch:

-> renames PHYS_MASK_SHIFT -> MAX_PHYS_SHIFT as supported by the kernel
-> Makes PHYS_MASK_SHIFT -> Dynamic value of the (I)PA bit width
-> For a realm: reduces phys_mask_shift if the RMM reports a smaller
configured size for the guest.

Co-developed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
---
arch/arm64/include/asm/kvm_arm.h | 2 +-
arch/arm64/include/asm/pgtable-hwdef.h | 4 ++--
arch/arm64/include/asm/pgtable.h | 5 +++++
arch/arm64/kernel/head.S | 2 +-
arch/arm64/kernel/rsi.c | 5 +++++
5 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 0df3fc3a0173..924f84024009 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -346,7 +346,7 @@
* bits in PAR are res0.
*/
#define PAR_TO_HPFAR(par) \
- (((par) & GENMASK_ULL(52 - 1, 12)) >> 8)
+ (((par) & GENMASK_ULL(MAX_PHYS_MASK_SHIFT - 1, 12)) >> 8)

#define ECN(x) { ESR_ELx_EC_##x, #x }

diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index f658aafc47df..677bf7a91616 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -178,8 +178,8 @@
/*
* Highest possible physical address supported.
*/
-#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)
-#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
+#define MAX_PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)
+#define MAX_PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)

#define TTBR_CNP_BIT (UL(1) << 0)

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index b4bbeed80fb6..a1319a743b38 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -35,6 +35,11 @@
#include <linux/sched.h>
#include <linux/page_table_check.h>

+extern unsigned int phys_mask_shift;
+
+#define PHYS_MASK_SHIFT (phys_mask_shift)
+#define PHYS_MASK ((1UL << PHYS_MASK_SHIFT) - 1)
+
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE

diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 952e17bd1c0b..a05504667b69 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -321,7 +321,7 @@ SYM_FUNC_START_LOCAL(create_idmap)
#error "Mismatch between VA_BITS and page size/number of translation levels"
#endif
#else
-#define IDMAP_PGD_ORDER (PHYS_MASK_SHIFT - PGDIR_SHIFT)
+#define IDMAP_PGD_ORDER (MAX_PHYS_MASK_SHIFT - PGDIR_SHIFT)
#define EXTRA_SHIFT
/*
* If VA_BITS == 48, we don't have to configure an additional
diff --git a/arch/arm64/kernel/rsi.c b/arch/arm64/kernel/rsi.c
index 9c63ee1c6979..49d36dfe0064 100644
--- a/arch/arm64/kernel/rsi.c
+++ b/arch/arm64/kernel/rsi.c
@@ -12,6 +12,8 @@ struct realm_config __attribute((aligned(PAGE_SIZE))) config;
unsigned long prot_ns_shared;
EXPORT_SYMBOL(prot_ns_shared);

+unsigned int phys_mask_shift = CONFIG_ARM64_PA_BITS;
+
DEFINE_STATIC_KEY_FALSE_RO(rsi_present);

static bool rsi_version_matches(void)
@@ -54,5 +56,8 @@ void __init arm64_rsi_init(void)
return;
prot_ns_shared = BIT(config.ipa_bits - 1);

+ if (config.ipa_bits - 1 < phys_mask_shift)
+ phys_mask_shift = config.ipa_bits - 1;
+
static_branch_enable(&rsi_present);
}
--
2.34.1