Re: [PATCH v6 4/4] riscv: dts: starfive: add dma controller node

Conor Dooley
2023-07-01T23:03:20Z

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On Sun, Jul 02, 2023 at 12:01:29AM +0200, Aurelien Jarno wrote:
> On 2023-03-22 17:48, Walker Chen wrote:
> > Add the dma controller node for the Starfive JH7110 SoC.
> >
> > Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
> > ---
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > index 17220576b21c..b503b6137743 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -510,6 +510,24 @@
> > #gpio-cells = <2>;
> > };
> >
> > + dma: dma-controller@16050000 {
> > + compatible = "starfive,jh7110-axi-dma";
> > + reg = <0x0 0x16050000 0x0 0x10000>;
> > + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
> > + <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
> > + clock-names = "core-clk", "cfgr-clk";
> > + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
> > + <&stgcrg JH7110_STGRST_DMA1P_AHB>;
> > + interrupts = <73>;
> > + #dma-cells = <1>;
> > + dma-channels = <4>;
> > + snps,dma-masters = <1>;
> > + snps,data-width = <3>;
> > + snps,block-size = <65536 65536 65536 65536>;
> > + snps,priority = <0 1 2 3>;
> > + snps,axi-max-burst-len = <16>;
> > + };
> > +
> > aoncrg: clock-controller@17000000 {
> > compatible = "starfive,jh7110-aoncrg";
> > reg = <0x0 0x17000000 0x0 0x10000>;
>
> It appears that this patch has never been applied, although the rest of
> the series has already been merged.

Correct. I can't apply it because the stgcrg it depends on is still
pending.

> Unfortunately it doesn't apply
> anymore due to other changes to that file.
>
> Could you please rebase and repost it?

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