From: Hal Feng <hal.feng@starfivetech.com>
To: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-riscv@lists.infradead.org>
Cc: Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
"Rob Herring" <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Ben Dooks <ben.dooks@sifive.com>,
"Daniel Lezcano" <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>,
Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Hal Feng <hal.feng@starfivetech.com>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v7 02/22] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
Date: Sat, 1 Apr 2023 19:19:14 +0800 [thread overview]
Message-ID: <20230401111934.130844-3-hal.feng@starfivetech.com> (raw)
In-Reply-To: <20230401111934.130844-1-hal.feng@starfivetech.com>
From: Emil Renner Berthing <kernel@esmil.dk>
Add bindings for the always-on clock and reset generator (AONCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../clock/starfive,jh7110-aoncrg.yaml | 107 ++++++++++++++++++
.../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++
.../dt-bindings/reset/starfive,jh7110-crg.h | 12 ++
3 files changed, 137 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
new file mode 100644
index 000000000000..923680a44aef
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Always-On Clock and Reset Generator
+
+maintainers:
+ - Emil Renner Berthing <kernel@esmil.dk>
+
+properties:
+ compatible:
+ const: starfive,jh7110-aoncrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ oneOf:
+ - items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC0 RMII reference or GMAC0 RGMII RX
+ - description: STG AXI/AHB
+ - description: APB Bus
+ - description: GMAC0 GTX
+
+ - items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC0 RMII reference or GMAC0 RGMII RX
+ - description: STG AXI/AHB or GMAC0 RGMII RX
+ - description: APB Bus or STG AXI/AHB
+ - description: GMAC0 GTX or APB Bus
+ - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
+
+ - items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC0 RMII reference
+ - description: GMAC0 RGMII RX
+ - description: STG AXI/AHB
+ - description: APB Bus
+ - description: GMAC0 GTX
+ - description: RTC Oscillator (32.768 kHz)
+
+ clock-names:
+ oneOf:
+ - minItems: 5
+ items:
+ - const: osc
+ - enum:
+ - gmac0_rmii_refin
+ - gmac0_rgmii_rxin
+ - const: stg_axiahb
+ - const: apb_bus
+ - const: gmac0_gtxclk
+ - const: rtc_osc
+
+ - minItems: 6
+ items:
+ - const: osc
+ - const: gmac0_rmii_refin
+ - const: gmac0_rgmii_rxin
+ - const: stg_axiahb
+ - const: apb_bus
+ - const: gmac0_gtxclk
+ - const: rtc_osc
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+ clock-controller@17000000 {
+ compatible = "starfive,jh7110-aoncrg";
+ reg = <0x17000000 0x10000>;
+ clocks = <&osc>, <&gmac0_rmii_refin>,
+ <&gmac0_rgmii_rxin>,
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg JH7110_SYSCLK_APB_BUS>,
+ <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
+ <&rtc_osc>;
+ clock-names = "osc", "gmac0_rmii_refin",
+ "gmac0_rgmii_rxin", "stg_axiahb",
+ "apb_bus", "gmac0_gtxclk",
+ "rtc_osc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index fdd1852e34cc..06257bfd9ac1 100644
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -200,4 +200,22 @@
#define JH7110_SYSCLK_END 190
+/* AONCRG clocks */
+#define JH7110_AONCLK_OSC_DIV4 0
+#define JH7110_AONCLK_APB_FUNC 1
+#define JH7110_AONCLK_GMAC0_AHB 2
+#define JH7110_AONCLK_GMAC0_AXI 3
+#define JH7110_AONCLK_GMAC0_RMII_RTX 4
+#define JH7110_AONCLK_GMAC0_TX 5
+#define JH7110_AONCLK_GMAC0_TX_INV 6
+#define JH7110_AONCLK_GMAC0_RX 7
+#define JH7110_AONCLK_GMAC0_RX_INV 8
+#define JH7110_AONCLK_OTPC_APB 9
+#define JH7110_AONCLK_RTC_APB 10
+#define JH7110_AONCLK_RTC_INTERNAL 11
+#define JH7110_AONCLK_RTC_32K 12
+#define JH7110_AONCLK_RTC_CAL 13
+
+#define JH7110_AONCLK_END 14
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
index b88216a4fe40..d78e38690ceb 100644
--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
@@ -139,4 +139,16 @@
#define JH7110_SYSRST_END 126
+/* AONCRG resets */
+#define JH7110_AONRST_GMAC0_AXI 0
+#define JH7110_AONRST_GMAC0_AHB 1
+#define JH7110_AONRST_IOMUX 2
+#define JH7110_AONRST_PMU_APB 3
+#define JH7110_AONRST_PMU_WKUP 4
+#define JH7110_AONRST_RTC_APB 5
+#define JH7110_AONRST_RTC_CAL 6
+#define JH7110_AONRST_RTC_32K 7
+
+#define JH7110_AONRST_END 8
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
--
2.38.1
next prev parent reply other threads:[~2023-04-01 11:19 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-01 11:19 [PATCH v7 00/22] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2023-04-01 11:19 ` [PATCH v7 01/22] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2023-04-01 11:19 ` Hal Feng [this message]
2023-04-01 11:19 ` [PATCH v7 03/22] clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng
2023-04-05 11:48 ` Heiko Stübner
2023-04-01 11:19 ` [PATCH v7 04/22] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2023-04-01 11:19 ` [PATCH v7 05/22] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng
2023-04-01 11:19 ` [PATCH v7 06/22] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-04-01 11:19 ` [PATCH v7 07/22] reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng
2023-04-01 11:19 ` [PATCH v7 08/22] reset: Create subdirectory for StarFive drivers Hal Feng
2023-04-01 11:19 ` [PATCH v7 09/22] reset: starfive: Factor out common JH71X0 reset code Hal Feng
2023-04-01 11:19 ` [PATCH v7 10/22] reset: starfive: Extract the " Hal Feng
2023-04-01 11:19 ` [PATCH v7 11/22] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-04-01 11:19 ` [PATCH v7 12/22] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
2023-04-01 11:19 ` [PATCH v7 13/22] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2023-04-01 11:19 ` [PATCH v7 14/22] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
2023-04-01 11:19 ` [PATCH v7 15/22] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
2023-04-01 11:19 ` [PATCH v7 16/22] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2023-04-01 11:19 ` [PATCH v7 17/22] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2023-04-01 11:19 ` [PATCH v7 18/22] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
2023-04-01 11:19 ` [PATCH v7 19/22] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2023-05-07 10:03 ` Shengyu Qu
2023-06-01 3:39 ` Hal Feng
2023-04-01 11:19 ` [PATCH v7 20/22] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng
2023-04-01 11:19 ` [PATCH v7 21/22] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
2023-04-04 18:38 ` Shengyu Qu
2023-04-05 1:40 ` Hal Feng
2023-04-01 11:19 ` [PATCH v7 22/22] riscv: dts: starfive: jh7110: Correct the properties of S7 core Hal Feng
2023-04-02 19:19 ` [PATCH v7 00/22] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Conor Dooley
2023-04-03 7:30 ` Hal Feng
2023-04-03 7:47 ` Conor Dooley
2023-04-05 14:40 ` Emil Renner Berthing
2023-04-05 21:30 ` Conor Dooley
2023-04-06 7:03 ` Hal Feng
2023-04-11 21:35 ` Conor Dooley
2023-04-12 2:12 ` Hal Feng
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