Re: [PATCH v3 1/6] cxl/pci: Add RCH downstream port AER and RAS register discovery

Jonathan Cameron
2023-04-14T11:47:12Z

> >> + endpoint = devm_cxl_add_port(host, &cxlmd->dev, cxlds->component_reg_phys,
> >> parent_dport);
> > As above, I'd prefer to see this refactor done in a precursor patch before the new
> > stuff is added. I like reviewing noop patches as I don't have to think much (so
> > can do it when I'm supposedly in a meeting ;)
> >
>
> Ok. I'll add an earlier patch that introduces cxl_setup_rcrb() and first moves this
> chunk into cxl_setup_rcrb(). The following patch will replace the cxl_setup_rcrb()
> logic with the AER and RAS discovery.
>
> My understanding is the requested refactoring changes then splits this patch into
> the 3 patches listed below (using git log latest first order):
> - Add RCH downstream port AER and RAS register discovery
> - Refactor RCD component discovery into separate function
> - Refactor RCRB register mapping into separate function

Spot on I think.

Thanks,

Jonathan