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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 06/24] net: dsa: mt7530: read XTAL value from correct register Date: Tue, 25 Apr 2023 11:29:15 +0300 Message-Id: <20230425082933.84654-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Arınç ÜNAL On commit 7ef6f6f8d237 ("net: dsa: mt7530: Add MT7621 TRGMII mode support") bit mask macros were added under the MT7530_HWTRAP register to read the crystal frequency. However, the value given to the xtal variable on mt7530_pad_clk_setup() is read from the MT7530_MHWTRAP register instead. It doesn't seem to matter as my testing on MCM and standalone MT7530 shows the value is correctly read from both registers but change it anyway. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index d0eae8e8c41d..98ef5ba0b19b 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -406,7 +406,7 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) struct mt7530_priv *priv = ds->priv; u32 ncpo1, ssc_delta, trgint, xtal; - xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; + xtal = mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; if (xtal == HWTRAP_XTAL_20MHZ) { dev_err(priv->dev, -- 2.37.2