RE: [PATCH 0/2] Add rs485 support to uartps driver

Guntupalli, Manikanta
2023-05-10T16:27:48Z

Hi Maarten,

> -----Original Message-----
> From: m.brock@vanmierlo.com <m.brock@vanmierlo.com>
> Sent: Thursday, May 4, 2023 5:52 PM
> To: Guntupalli, Manikanta <manikanta.guntupalli@amd.com>
> Cc: gregkh@linuxfoundation.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; michal.simek@xilinx.com; linux-
> serial@vger.kernel.org; devicetree@vger.kernel.org; linux-
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> (AMD-Xilinx) <git@amd.com>; Pandey, Radhey Shyam
> <radhey.shyam.pandey@amd.com>; Datta, Shubhrajyoti
> <shubhrajyoti.datta@amd.com>; Goud, Srinivas <srinivas.goud@amd.com>;
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> Subject: Re: [PATCH 0/2] Add rs485 support to uartps driver
>
> Manikanta Guntupalli wrote 2023-04-26 14:29:
> > Add optional gpio property to uartps node to support rs485 Add rs485
> > support to uartps driver
> >
> > Manikanta Guntupalli (2):
> > dt-bindings: Add optional gpio property to uartps node to support
> > rs485
> > tty: serial: uartps: Add rs485 support to uartps driver
> >
> > .../devicetree/bindings/serial/cdns,uart.yaml | 5 +
> > drivers/tty/serial/xilinx_uartps.c | 96 ++++++++++++++++++-
> > 2 files changed, 100 insertions(+), 1 deletion(-)
>
> Why would you want to use a GPIO and not RTS for choosing the direction as
> is more common in this case?
In ZynqMp platform Cadence UART Controller RTS signal routed to external through the PL(Programmable Logic) design not through Multiplexed IO.

> And have you thought about configuring the polarity?
GPIO polarity configured through device tree property.

&uart0 {
...
txrx-gpios = <&gpio 72 GPIO_ACTIVE_LOW>;
linux,rs485-enabled-at-boot-time;
};

> How long will the signal be active before the real transmission begins so the
> driver can settle?
Default is RE(GPIO LOW) and while sending we drive the pin to HIGH. We wait for transmission completion, for that we check Transmitter state machine active status to ZERO and TX FIFO EMPTY.

Thanks,
Manikanta.