From: Evan Green <evan@rivosinc.com>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: Evan Green <evan@rivosinc.com>, Albert Ou <aou@eecs.berkeley.edu>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <apatel@ventanamicro.com>,
Conor Dooley <conor.dooley@microchip.com>,
Dao Lu <daolu@rivosinc.com>,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
Jisheng Zhang <jszhang@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Sunil V L <sunilvl@ventanamicro.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH 1/3] RISC-V: Add Zba extension probing
Date: Fri, 28 Apr 2023 12:06:06 -0700 [thread overview]
Message-ID: <20230428190609.3239486-2-evan@rivosinc.com> (raw)
In-Reply-To: <20230428190609.3239486-1-evan@rivosinc.com>
Add the Zba address bit manipulation extension into those the kernel is
aware of and maintains in its riscv_isa bitmap.
Signed-off-by: Evan Green <evan@rivosinc.com>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 9af793970855..fa36db9281ab 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -44,6 +44,7 @@
#define RISCV_ISA_EXT_ZIHINTPAUSE 32
#define RISCV_ISA_EXT_SVNAPOT 33
#define RISCV_ISA_EXT_ZICBOZ 34
+#define RISCV_ISA_EXT_ZBA 35
#define RISCV_ISA_EXT_MAX 64
#define RISCV_ISA_EXT_NAME_LEN_MAX 32
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 3df38052dcbd..2f85b1656557 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -184,6 +184,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
+ __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 52585e088873..1a80474e308e 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -233,6 +233,7 @@ void __init riscv_fill_hwcap(void)
SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
+ SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
--
2.25.1
next prev parent reply other threads:[~2023-04-28 19:06 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 19:06 [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe Evan Green
2023-04-28 19:06 ` Evan Green [this message]
2023-04-29 13:41 ` [PATCH 1/3] RISC-V: Add Zba extension probing Conor Dooley
2023-04-29 20:07 ` Palmer Dabbelt
2023-04-28 19:06 ` [PATCH 2/3] RISC-V: Track ISA extensions per hart Evan Green
2023-04-29 13:36 ` Conor Dooley
2023-04-29 20:07 ` Palmer Dabbelt
2023-04-28 19:06 ` [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb Evan Green
2023-04-29 13:40 ` Conor Dooley
2023-04-29 20:07 ` Palmer Dabbelt
2023-05-01 15:33 ` Evan Green
2023-04-29 12:34 ` [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe Andrew Jones
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