From: Conor Dooley <conor@kernel.org>
To: Evan Green <evan@rivosinc.com>
Cc: Palmer Dabbelt <palmer@rivosinc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Andrew Jones <ajones@ventanamicro.com>,
Conor Dooley <conor.dooley@microchip.com>,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
Jisheng Zhang <jszhang@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH 2/3] RISC-V: Track ISA extensions per hart
Date: Sat, 29 Apr 2023 14:36:31 +0100 [thread overview]
Message-ID: <20230429-record-plunder-a21cf40d4cee@spud> (raw)
In-Reply-To: <20230428190609.3239486-3-evan@rivosinc.com>
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On Fri, Apr 28, 2023 at 12:06:07PM -0700, Evan Green wrote:
> @@ -112,14 +116,17 @@ void __init riscv_fill_hwcap(void)
> bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
>
> for_each_of_cpu_node(node) {
> + struct riscv_isainfo *isainfo;
> unsigned long this_hwcap = 0;
> - DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
> const char *temp;
> + unsigned int cpu_id;
>
> rc = riscv_of_processor_hartid(node, &hartid);
> if (rc < 0)
> continue;
>
> + cpu_id = riscv_hartid_to_cpuid(hartid);
> + isainfo = &hart_isa[cpu_id];
> if (of_property_read_string(node, "riscv,isa", &isa)) {
Would you mind adding a blank line above the if statement please?
Otherwise,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
> pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
> continue;
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next prev parent reply other threads:[~2023-04-29 13:36 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 19:06 [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe Evan Green
2023-04-28 19:06 ` [PATCH 1/3] RISC-V: Add Zba extension probing Evan Green
2023-04-29 13:41 ` Conor Dooley
2023-04-29 20:07 ` Palmer Dabbelt
2023-04-28 19:06 ` [PATCH 2/3] RISC-V: Track ISA extensions per hart Evan Green
2023-04-29 13:36 ` Conor Dooley [this message]
2023-04-29 20:07 ` Palmer Dabbelt
2023-04-28 19:06 ` [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb Evan Green
2023-04-29 13:40 ` Conor Dooley
2023-04-29 20:07 ` Palmer Dabbelt
2023-05-01 15:33 ` Evan Green
2023-04-29 12:34 ` [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe Andrew Jones
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