From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE615C77B7F for ; Sat, 6 May 2023 22:03:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229904AbjEFWDV (ORCPT ); Sat, 6 May 2023 18:03:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229628AbjEFWDT (ORCPT ); Sat, 6 May 2023 18:03:19 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93F007EF8 for ; Sat, 6 May 2023 15:03:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683410598; x=1714946598; h=date:from:to:cc:subject:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=85db/Q4ojopDoG5xswhFXtX+yoZa0a8Q5iJRo2143F0=; b=IVG+hcuCw+egRdlIfzfC+TL3F8eY/wcCPbq6ldE4YuVDU4nAKPvxL+Qk gm1m4c7XB6BC0d7kk9AGbR4dFhHokdqvcBBvNXTKjUODJ95HTMbFh5m6d J3KCBg3GuGz2LEY3NncfsqUKfRyohbINyH+bMkxQ1X8TDGIX0dcU0xpJx CVFoLkAoETiA9lFBGHrh/tJQra4ydJIR+WUXV7paOT4B+9g3+0ELOJIxT YskKvAjrquyOfEm6NFqCgsphUtHz/BHiX0C560bg9c7JjqI2izExsZiLY yVz/bMBrhSOt5onUlVJI+OHqb7LO1pxbveFFeKGlmWeOcTz/0Yk7Bp5gb w==; X-IronPort-AV: E=McAfee;i="6600,9927,10702"; a="377506826" X-IronPort-AV: E=Sophos;i="5.99,255,1677571200"; d="scan'208";a="377506826" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2023 15:03:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10702"; a="698019248" X-IronPort-AV: E=Sophos;i="5.99,255,1677571200"; d="scan'208";a="698019248" Received: from jacob-builder.jf.intel.com (HELO jacob-builder) ([10.24.100.114]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2023 15:03:17 -0700 Date: Sat, 6 May 2023 15:07:41 -0700 From: Jacob Pan To: Linus Torvalds Cc: LKML , iommu@lists.linux.dev, Jason Gunthorpe , Lu Baolu , Joerg Roedel , Jean-Philippe Brucker , Robin Murphy , Will Deacon , Raj Ashok , "Tian, Kevin" , Yi Liu , "Yu, Fenghua" , jacob.jun.pan@linux.intel.com Subject: Re: [PATCH] iommu: Add Kconfig help text for IOMMU_SVA Message-ID: <20230506150741.2e3d2dcc@jacob-builder> In-Reply-To: References: <20230506133134.1492395-1-jacob.jun.pan@linux.intel.com> Organization: OTC X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Linus, On Sat, 6 May 2023 08:43:08 -0700, Linus Torvalds wrote: > On Sat, May 6, 2023 at 6:27=E2=80=AFAM Jacob Pan > wrote: > > > > Shared Virtual Addressing (SVA) is not immediately intuitive to people > > who work outside IOMMU subsystem, add some explanation to make it less > > opaque. =20 >=20 > So the patch has at least two problems. >=20 > The first is that you corrupted the SPDX line. >=20 Sorry, my mistake. Will not try sending patches before fully waking up. > But the second is that the change from >=20 > - bool > + bool "Shared Virtual Addressing" >=20 > means that now Kconfig *asks* about this thing, which was never the > intent. The other Kconfig options that need it all do a >=20 > select IOMMU_SVA >=20 > to get it picked. >=20 > I suspect that's why it then causes errors - because now the test > robot can enable the option even in situations where it makes no sense > and doesn't work. >=20 > So no, it's not that the option needs a help entry that can be queried > at Kconfig time. It's that the option needs a name that makes sense > and isn't some random jumble of letters that is only understandable to > people who already know exactly what it is. Right, how about IOMMU_SHARING_CPU_PGTABLE? Since this is more of a one-sided relationship where IOMMU walks CPU page tables. Thanks, Jacob