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From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Pavel Machek <pavel@denx.de>
Cc: stable@vger.kernel.org, patches@lists.linux.dev,
	linux-kernel@vger.kernel.org, torvalds@linux-foundation.org,
	akpm@linux-foundation.org, linux@roeck-us.net, shuah@kernel.org,
	patches@kernelci.org, lkft-triage@lists.linaro.org,
	jonathanh@nvidia.com, f.fainelli@gmail.com,
	sudipm.mukherjee@gmail.com, srw@sladewatkins.net, rwarsow@gmx.de,
	l.sanfilippo@kunbus.com, jarkko@kernel.org
Subject: Re: Wrong/strange TPM patches was Re: [PATCH 6.1 000/119] 6.1.31-rc1 review
Date: Tue, 30 May 2023 14:02:47 +0100	[thread overview]
Message-ID: <2023053014-sanctuary-attractor-13ed@gregkh> (raw)
In-Reply-To: <ZHXUGdFMIcB5HL8s@duo.ucw.cz>

On Tue, May 30, 2023 at 12:46:49PM +0200, Pavel Machek wrote:
> Hi!
> 
> > This is the start of the stable review cycle for the 6.1.31 release.
> > There are 119 patches in this series, all will be posted as a response
> > to this one.  If anyone has any issues with these being applied, please
> > let me know.
> 
> > Lino Sanfilippo <l.sanfilippo@kunbus.com>
> >     tpm, tpm_tis: Avoid cache incoherency in test for interrupts
> 
> Description on this one is wrong/confused. There's no cache problem in
> the code. Plus test_bit and friend already use bit number, so
> 
> -       bool itpm = priv->flags & TPM_TIS_ITPM_WORKAROUND;
> +       bool itpm = test_bit(TPM_TIS_ITPM_WORKAROUND, &priv->flags);
> 
> @@ -87,6 +87,7 @@ enum tpm_tis_flags {
>         TPM_TIS_ITPM_WORKAROUND         = BIT(0),
>         TPM_TIS_INVALID_STATUS          = BIT(1),
>         TPM_TIS_DEFAULT_CANCELLATION    = BIT(2),
> +       TPM_TIS_IRQ_TESTED              = BIT(3),
>  };
> 
> this enum needs to go from BIT() to raw numbers.
> 
> You can just do return tpm_pm_resume();
> 
> > Jarkko Sakkinen <jarkko@kernel.org>
> >     tpm: Prevent hwrng from activating during resume
> 
> @@ -429,6 +431,14 @@ int tpm_pm_resume(struct device *dev)
>         if (chip == NULL)
>                 return -ENODEV;
>  
> +       chip->flags &= ~TPM_CHIP_FLAG_SUSPENDED;
> +
> +       /*
> +        * Guarantee that SUSPENDED is written last, so that hwrng does not
> +        * activate before the chip has been fully resumed.
> +        */
> +       wmb();
> +
>         return 0;
>  }
>  EXPORT_SYMBOL_GPL(tpm_pm_resume);
> 
> This code is confused. First, either you don't need memory barriers
> here, or you need real locking. Second, if you want to guarantee flags
> are written last, you need to put the barrier before the
> assignment. (But ... get rid of that confusion, first).

Care to submit patches to resolve this?  It's this way in Linus's tree
now from what I can tell, and these changes were needed for another
stable-marked change, so I'll leave them in for now.

thanks,

greg k-h

  parent reply	other threads:[~2023-05-30 13:03 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-28 19:10 [PATCH 6.1 000/119] 6.1.31-rc1 review Greg Kroah-Hartman
2023-05-28 19:10 ` [PATCH 6.1 018/119] platform/x86/intel/ifs: Annotate work queue on stack so object debug does not complain Greg Kroah-Hartman
2023-05-29  5:11 ` [PATCH 6.1 000/119] 6.1.31-rc1 review Bagas Sanjaya
2023-05-29 10:09 ` ogasawara takeshi
2023-05-29 12:03 ` Conor Dooley
2023-05-29 13:12 ` Markus Reichelt
2023-05-29 13:28 ` Naresh Kamboju
2023-05-29 16:07 ` Guenter Roeck
2023-05-29 21:49 ` Ron Economos
2023-05-30  9:19 ` Jon Hunter
2023-05-30 10:46 ` Wrong/strange TPM patches was " Pavel Machek
2023-05-30 11:50   ` Linus Torvalds
2023-05-30 13:02   ` Greg Kroah-Hartman [this message]
2023-05-30 13:58     ` Lino Sanfilippo
2023-05-30 11:52 ` Chris Paterson
2023-05-30 17:02 ` Allen Pais
2023-05-30 19:29 ` Florian Fainelli

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