From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
<linux-cxl@vger.kernel.org>, <rrichter@amd.com>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: Re: [PATCH v4 14/23] cxl/port: Remove Component Register base address from struct cxl_port
Date: Thu, 1 Jun 2023 14:27:18 +0100 [thread overview]
Message-ID: <20230601142718.00001855@Huawei.com> (raw)
In-Reply-To: <20230523232214.55282-15-terry.bowman@amd.com>
On Tue, 23 May 2023 18:22:05 -0500
Terry Bowman <terry.bowman@amd.com> wrote:
> From: Robert Richter <rrichter@amd.com>
>
> The Component Register base address @component_reg_phys is no longer
> used after the rework of the Component Register setup which now uses
> struct member @comp_map instead. Remove the base address.
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/port.c | 4 +---
> drivers/cxl/cxl.h | 2 --
> 2 files changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index db2ba0c886e2..183f9f8548e2 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -615,7 +615,6 @@ static int devm_cxl_link_parent_dport(struct device *host,
> static struct lock_class_key cxl_port_key;
>
> static struct cxl_port *cxl_port_alloc(struct device *uport,
> - resource_size_t component_reg_phys,
> struct cxl_dport *parent_dport)
> {
> struct cxl_port *port;
> @@ -665,7 +664,6 @@ static struct cxl_port *cxl_port_alloc(struct device *uport,
> } else
> dev->parent = uport;
>
> - port->component_reg_phys = component_reg_phys;
> ida_init(&port->decoder_ida);
> port->hdm_end = -1;
> port->commit_end = -1;
> @@ -724,7 +722,7 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host,
> struct device *dev;
> int rc;
>
> - port = cxl_port_alloc(uport, component_reg_phys, parent_dport);
> + port = cxl_port_alloc(uport, parent_dport);
> if (IS_ERR(port))
> return port;
>
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index dc83c1d0396e..4365d46606df 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -556,7 +556,6 @@ struct cxl_dax_region {
> * @nr_dports: number of entries in @dports
> * @hdm_end: track last allocated HDM decoder instance for allocation ordering
> * @commit_end: cursor to track highest committed decoder for commit ordering
> - * @component_reg_phys: component register capability base address (optional)
> * @dead: last ep has been removed, force port re-creation
> * @depth: How deep this port is relative to the root. depth 0 is the root.
> * @cdat: Cached CDAT data
> @@ -576,7 +575,6 @@ struct cxl_port {
> int nr_dports;
> int hdm_end;
> int commit_end;
> - resource_size_t component_reg_phys;
> bool dead;
> unsigned int depth;
> struct cxl_cdat {
next prev parent reply other threads:[~2023-06-01 13:28 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-23 23:21 [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-05-23 23:21 ` [PATCH v4 01/23] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-01 10:13 ` Jonathan Cameron
2023-06-02 14:16 ` Robert Richter
2023-05-23 23:21 ` [PATCH v4 02/23] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-01 10:38 ` Jonathan Cameron
2023-06-02 14:53 ` Robert Richter
2023-05-23 23:21 ` [PATCH v4 03/23] cxl: Rename member @dport of struct cxl_dport to @dev Terry Bowman
2023-06-01 10:41 ` Jonathan Cameron
2023-05-23 23:21 ` [PATCH v4 04/23] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-01 10:49 ` Jonathan Cameron
2023-06-02 15:11 ` Robert Richter
2023-05-23 23:21 ` [PATCH v4 05/23] cxl/pci: Refactor component register discovery for reuse Terry Bowman
2023-06-01 10:52 ` Jonathan Cameron
2023-05-23 23:21 ` [PATCH v4 06/23] cxl/acpi: Moving add_host_bridge_uport() around Terry Bowman
2023-06-01 10:54 ` Jonathan Cameron
2023-05-23 23:21 ` [PATCH v4 07/23] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-01 12:45 ` Jonathan Cameron
2023-06-02 15:42 ` Robert Richter
2023-05-23 23:21 ` [PATCH v4 08/23] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-01 12:49 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 09/23] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-01 12:59 ` Jonathan Cameron
2023-06-02 15:45 ` Robert Richter
2023-05-23 23:22 ` [PATCH v4 10/23] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-01 13:06 ` Jonathan Cameron
2023-06-02 15:58 ` Robert Richter
2023-05-23 23:22 ` [PATCH v4 11/23] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-01 13:07 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 12/23] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-01 13:07 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 13/23] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-05-24 1:12 ` kernel test robot
2023-05-24 9:49 ` Robert Richter
2023-05-25 20:23 ` kernel test robot
2023-06-01 13:11 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 14/23] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-01 13:27 ` Jonathan Cameron [this message]
2023-05-23 23:22 ` [PATCH v4 15/23] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-01 13:28 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 16/23] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-06-01 13:28 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 17/23] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-01 13:36 ` Jonathan Cameron
2023-06-01 13:38 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 18/23] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-05-24 16:55 ` Bjorn Helgaas
2023-05-25 21:38 ` Terry Bowman
2023-05-23 23:22 ` [PATCH v4 19/23] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-01 13:42 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 20/23] cxl/pci: Prepare for logging RCH downstream port protocol errors Terry Bowman
2023-06-01 13:49 ` Jonathan Cameron
2023-06-01 14:06 ` Terry Bowman
2023-06-01 14:12 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 21/23] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-01 14:03 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 22/23] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-05-24 21:32 ` Bjorn Helgaas
2023-05-25 21:29 ` Robert Richter
2023-05-25 22:01 ` Bjorn Helgaas
2023-05-25 22:28 ` Robert Richter
2023-06-01 14:06 ` Jonathan Cameron
2023-05-23 23:22 ` [PATCH v4 23/23] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-05-24 21:45 ` Bjorn Helgaas
2023-05-25 22:08 ` Robert Richter
2023-05-26 20:31 ` Bjorn Helgaas
2023-06-01 14:11 ` Jonathan Cameron
2023-06-02 16:41 ` Robert Richter
2023-05-23 23:29 ` [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling - CHANGELOG Terry Bowman
2023-05-24 1:39 ` [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling Terry Bowman
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