Re: [PATCH v4 16/23] cxl/pci: Remove Component Register base address from struct cxl_dev_state

Jonathan Cameron
2023-06-01T13:30:04Z

On Tue, 23 May 2023 18:22:07 -0500
Terry Bowman <terry.bowman@amd.com> wrote:

> From: Robert Richter <rrichter@amd.com>
>
> The Component Register base address @component_reg_phys is no longer
> used after the rework of the Component Register setup which now uses
> struct member @comp_map instead. Remove the base address.
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
> drivers/cxl/cxlmem.h | 2 --
> drivers/cxl/mem.c | 4 ++--
> drivers/cxl/pci.c | 3 ---
> 3 files changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 2823c5aaf3db..7b5b2d3187bf 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -287,7 +287,6 @@ struct cxl_poison_state {
> * @active_persistent_bytes: sum of hard + soft persistent
> * @next_volatile_bytes: volatile capacity change pending device reset
> * @next_persistent_bytes: persistent capacity change pending device reset
> - * @component_reg_phys: register base of component registers
> * @info: Cached DVSEC information about the device.
> * @serial: PCIe Device Serial Number
> * @event: event log driver state
> @@ -326,7 +325,6 @@ struct cxl_dev_state {
> u64 next_volatile_bytes;
> u64 next_persistent_bytes;
>
> - resource_size_t component_reg_phys;
> u64 serial;
>
> struct cxl_event_state event;
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 0643852444f3..618e839919eb 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -49,7 +49,6 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
> struct cxl_dport *parent_dport)
> {
> struct cxl_port *parent_port = parent_dport->port;
> - struct cxl_dev_state *cxlds = cxlmd->cxlds;
> struct cxl_port *endpoint, *iter, *down;
> int rc;
>
> @@ -65,8 +64,9 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
> ep->next = down;
> }
>
> + /* The Endpoint's component regs are located in cxlds. */
> endpoint = devm_cxl_add_port(host, &cxlmd->dev,
> - cxlds->component_reg_phys,
> + CXL_RESOURCE_NONE,
> parent_dport);
> if (IS_ERR(endpoint))
> return PTR_ERR(endpoint);
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 00983770ea7b..0db71493db5d 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -661,7 +661,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> * If the component registers can't be found, the cxl_pci driver may
> * still be useful for management functions so don't return an error.
> */
> - cxlds->component_reg_phys = CXL_RESOURCE_NONE;
> rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,
> &cxlds->comp_map);
> if (rc)
> @@ -669,8 +668,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> else if (!cxlds->comp_map.component_map.ras.valid)
> dev_dbg(&pdev->dev, "RAS registers not found\n");
>
> - cxlds->component_reg_phys = cxlds->comp_map.resource;
> -
> rc = cxl_map_component_regs(&cxlds->comp_map, &cxlds->regs.component,
> BIT(CXL_CM_CAP_CAP_ID_RAS));
> if (rc)