Re: [PATCH v4 00/23] cxl/pci: Add support for RCH RAS error handling - CHANGELOG

Terry Bowman
2023-05-23T23:33:46Z

Dropped the change log somehow, Adding here.

Changes in V4:
- Made port RAS register discovery common and called from
__devm_cxl_add_dport().
- Changed RCH AER register discovery to be called from
__devm_cxl_add_dport().
- Changed RAS and RCH AER register mapping to be called from
__devm_cxl_add_dport().
- Changed component register mapping to use common mapping,
cxl_map_component_regs().
- Added cxl_regs to 'struct cxl_dport' for providing RCH downstream port
mapped registers used in error handler.
- Refactored cxl_map_reg() to be like devm_cxl_iomap_block().
- PCI/AER:
- Removed patch for cper_mem_err_unpack().
- Renamed cper_print_aer() to pci_print_aer().
- Changed pci_print_aer() export to use
EXPORT_SYMBOL_NS_GPL(pci_print_aer, CXL).
- Improved description of PCIEAER_CXL option in Kconfig.
- Renamed function to pci_aer_unmask_internal_errors(), added
pcie_aer_is_native() check.
- Improved comments and added spec refs.
- Renamed functions to cxl_rch_handle_error*().
- Modified cxl_rch_handle_error_iter() to only call the handler
callbacks, this also simplifies refcounting of the pdev.
- Refactored handle_error_source(), created pci_aer_handle_error().
- Changed printk messages to pci_*() variants.
- Added check for pcie_aer_is_native() to the RCEC.
- Introduced function cxl_rch_enable_rcec().
- Updated patch description ("PCI/AER: Forward RCH downstream
port-detected errors to the CXL.mem dev handler").

Changes in V3:
- Correct base commit in cover sheet.
- Change hardcoded return 0 to NULL in regs.c.
- Remove calls to pci_disable_pcie_error_reporting(pdev) and
pci_enable_pcie_error_reporting(pdev) in mem.c;
- Move RCEC interrupt unmask to PCIe port AER driver's probe.
- Fixes missing PCIEAER and PCIEPORTBUS config option error.
- Rename cxl_rcrb_setup() to cxl_setup_rcrb() in mem.c.
- Update cper_mem_err_unpack() patch subject and description.

Changes in V2:
- Refactor RCH initialization into cxl_mem driver.
- Includes RCH RAS and AER register discovery and mapping.
- Add RCEC protocol error interrupt forwarding to CXL endpoint
handler.
- Change AER and RAS logging to use existing trace routines.
- Enable RCEC AER internal errors.

Regards,
Terry

On 5/23/23 18:21, Terry Bowman wrote:
> Patches #1 to #16 are a rework of the Component Register setup. This
> is needed to share multiple CXL capabilities (HDM and RAS) for the
> same component, also there can be different components implementing
> the same capability, finally RCH mode should be supported too. The
> general approach to solve this is to:
>
> * Unify code for components and capabilities in VH and RCH modes.
>
> * Early setup of the Component Register base address.
>
> * Create and store the register mappings to later use it for mapping
> the capability I/O ranges.
>
> Patches #17 to #23 enable CXL RCH error handling. These are needed because
> RCH downstream port protocol error handling is implemented uniquely and not
> currently supported. These patches address the following:
>
> * Discovery and mapping of RCH downstream port AER registers.
>
> * AER portdrv changes to support CXL RCH protocol errors.
>
> * Interrupt setup specific to RCH mode: enabling RCEC internal
> errors and disabling root port interrupts.
>
> Dan Williams (1):
> cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
>
> Robert Richter (16):
> cxl/acpi: Probe RCRB later during RCH downstream port creation
> cxl: Rename member @dport of struct cxl_dport to @dev
> cxl/core/regs: Add @dev to cxl_register_map
> cxl/acpi: Moving add_host_bridge_uport() around
> cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's
> port
> cxl/regs: Remove early capability checks in Component Register setup
> cxl/pci: Early setup RCH dport component registers from RCRB
> cxl/port: Store the port's Component Register mappings in struct
> cxl_port
> cxl/port: Store the downstream port's Component Register mappings in
> struct cxl_dport
> cxl/pci: Store the endpoint's Component Register mappings in struct
> cxl_dev_state
> cxl/hdm: Use stored Component Register mappings to map HDM decoder
> capability
> cxl/port: Remove Component Register base address from struct cxl_port
> cxl/port: Remove Component Register base address from struct cxl_dport
> cxl/pci: Remove Component Register base address from struct
> cxl_dev_state
> PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem
> dev handler
> PCI/AER: Unmask RCEC internal errors to enable RCH downstream port
> error handling
>
> Terry Bowman (6):
> cxl/pci: Refactor component register discovery for reuse
> cxl/pci: Add RCH downstream port AER register discovery
> PCI/AER: Refactor cper_print_aer() for use by CXL driver module
> cxl/pci: Update CXL error logging to use RAS register address
> cxl/pci: Prepare for logging RCH downstream port protocol errors
> cxl/pci: Add RCH downstream port error logging
>
> base-commit: a70fc4ed20a6118837b0aecbbf789074935f473b
>
> drivers/cxl/acpi.c | 191 +++++++++++++++++++---------------
> drivers/cxl/core/hdm.c | 59 +++++------
> drivers/cxl/core/pci.c | 140 ++++++++++++++++++++++---
> drivers/cxl/core/port.c | 157 ++++++++++++++++++++++++----
> drivers/cxl/core/region.c | 4 +-
> drivers/cxl/core/regs.c | 152 ++++++++++++++++++++++++---
> drivers/cxl/cxl.h | 56 ++++++----
> drivers/cxl/cxlmem.h | 5 +-
> drivers/cxl/mem.c | 16 +--
> drivers/cxl/pci.c | 109 +++++++------------
> drivers/cxl/port.c | 5 +-
> drivers/pci/pcie/Kconfig | 12 +++
> drivers/pci/pcie/aer.c | 173 ++++++++++++++++++++++++++++--
> include/linux/aer.h | 2 +-
> tools/testing/cxl/Kbuild | 2 +-
> tools/testing/cxl/test/cxl.c | 10 +-
> tools/testing/cxl/test/mock.c | 12 +--
> tools/testing/cxl/test/mock.h | 7 +-
> 18 files changed, 824 insertions(+), 288 deletions(-)
>