From: Terry Bowman <terry.bowman@amd.com>
To: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
<Jonathan.Cameron@huawei.com>, <linux-cxl@vger.kernel.org>
Cc: <terry.bowman@amd.com>, <rrichter@amd.com>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: [PATCH v5 06/26] cxl/pci: Refactor component register discovery for reuse
Date: Wed, 7 Jun 2023 17:16:31 -0500 [thread overview]
Message-ID: <20230607221651.2454764-7-terry.bowman@amd.com> (raw)
In-Reply-To: <20230607221651.2454764-1-terry.bowman@amd.com>
The endpoint implements component register setup code. Refactor it for
reuse with RCRB, downstream port, and upstream port setup.
Move PCI specifics from cxl_setup_regs() into cxl_pci_setup_regs().
Move cxl_setup_regs() into cxl/core/regs.c and export it. This also
includes supporting static functions cxl_map_registerblock(),
cxl_unmap_register_block() and cxl_probe_regs().
Co-developed-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/cxl/core/regs.c | 78 ++++++++++++++++++++++++++++++++++++++++
drivers/cxl/cxl.h | 1 +
drivers/cxl/pci.c | 80 +++--------------------------------------
3 files changed, 84 insertions(+), 75 deletions(-)
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 3b4e56fb36a8..bf80e371ef27 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -338,6 +338,84 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
}
EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL);
+static int cxl_map_regblock(struct cxl_register_map *map)
+{
+ struct device *dev = map->dev;
+
+ map->base = ioremap(map->resource, map->max_size);
+ if (!map->base) {
+ dev_err(dev, "failed to map registers\n");
+ return -ENOMEM;
+ }
+
+ dev_dbg(dev, "Mapped CXL Memory Device resource %pa\n", &map->resource);
+
+ return 0;
+}
+
+static void cxl_unmap_regblock(struct cxl_register_map *map)
+{
+ iounmap(map->base);
+ map->base = NULL;
+}
+
+static int cxl_probe_regs(struct cxl_register_map *map)
+{
+ struct cxl_component_reg_map *comp_map;
+ struct cxl_device_reg_map *dev_map;
+ struct device *dev = map->dev;
+ void __iomem *base = map->base;
+
+ switch (map->reg_type) {
+ case CXL_REGLOC_RBI_COMPONENT:
+ comp_map = &map->component_map;
+ cxl_probe_component_regs(dev, base, comp_map);
+ if (!comp_map->hdm_decoder.valid) {
+ dev_err(dev, "HDM decoder registers not found\n");
+ return -ENXIO;
+ }
+
+ if (!comp_map->ras.valid)
+ dev_dbg(dev, "RAS registers not found\n");
+
+ dev_dbg(dev, "Set up component registers\n");
+ break;
+ case CXL_REGLOC_RBI_MEMDEV:
+ dev_map = &map->device_map;
+ cxl_probe_device_regs(dev, base, dev_map);
+ if (!dev_map->status.valid || !dev_map->mbox.valid ||
+ !dev_map->memdev.valid) {
+ dev_err(dev, "registers not found: %s%s%s\n",
+ !dev_map->status.valid ? "status " : "",
+ !dev_map->mbox.valid ? "mbox " : "",
+ !dev_map->memdev.valid ? "memdev " : "");
+ return -ENXIO;
+ }
+
+ dev_dbg(dev, "Probing device registers...\n");
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+int cxl_setup_regs(struct cxl_register_map *map)
+{
+ int rc;
+
+ rc = cxl_map_regblock(map);
+ if (rc)
+ return rc;
+
+ rc = cxl_probe_regs(map);
+ cxl_unmap_regblock(map);
+
+ return rc;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_setup_regs, CXL);
+
resource_size_t cxl_probe_rcrb(struct device *dev, resource_size_t rcrb,
struct cxl_rcrb_info *ri, enum cxl_rcrb which)
{
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 095b767c21e9..1c6fe53e9dc7 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -264,6 +264,7 @@ int cxl_map_device_regs(struct cxl_register_map *map,
enum cxl_regloc_type;
int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
struct cxl_register_map *map);
+int cxl_setup_regs(struct cxl_register_map *map);
enum cxl_rcrb {
CXL_RCRB_DOWNSTREAM,
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 9c1b44f42e49..ac17bc0430dc 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -274,71 +274,8 @@ static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds)
return 0;
}
-static int cxl_map_regblock(struct cxl_register_map *map)
-{
- struct device *dev = map->dev;
-
- map->base = ioremap(map->resource, map->max_size);
- if (!map->base) {
- dev_err(dev, "failed to map registers\n");
- return -ENOMEM;
- }
-
- dev_dbg(dev, "Mapped CXL Memory Device resource %pa\n", &map->resource);
-
- return 0;
-}
-
-static void cxl_unmap_regblock(struct cxl_register_map *map)
-{
- iounmap(map->base);
- map->base = NULL;
-}
-
-static int cxl_probe_regs(struct cxl_register_map *map)
-{
- struct cxl_component_reg_map *comp_map;
- struct cxl_device_reg_map *dev_map;
- struct device *dev = map->dev;
- void __iomem *base = map->base;
-
- switch (map->reg_type) {
- case CXL_REGLOC_RBI_COMPONENT:
- comp_map = &map->component_map;
- cxl_probe_component_regs(dev, base, comp_map);
- if (!comp_map->hdm_decoder.valid) {
- dev_err(dev, "HDM decoder registers not found\n");
- return -ENXIO;
- }
-
- if (!comp_map->ras.valid)
- dev_dbg(dev, "RAS registers not found\n");
-
- dev_dbg(dev, "Set up component registers\n");
- break;
- case CXL_REGLOC_RBI_MEMDEV:
- dev_map = &map->device_map;
- cxl_probe_device_regs(dev, base, dev_map);
- if (!dev_map->status.valid || !dev_map->mbox.valid ||
- !dev_map->memdev.valid) {
- dev_err(dev, "registers not found: %s%s%s\n",
- !dev_map->status.valid ? "status " : "",
- !dev_map->mbox.valid ? "mbox " : "",
- !dev_map->memdev.valid ? "memdev " : "");
- return -ENXIO;
- }
-
- dev_dbg(dev, "Probing device registers...\n");
- break;
- default:
- break;
- }
-
- return 0;
-}
-
-static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
- struct cxl_register_map *map)
+static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
+ struct cxl_register_map *map)
{
int rc;
@@ -346,14 +283,7 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
if (rc)
return rc;
- rc = cxl_map_regblock(map);
- if (rc)
- return rc;
-
- rc = cxl_probe_regs(map);
- cxl_unmap_regblock(map);
-
- return rc;
+ return cxl_setup_regs(map);
}
/*
@@ -684,7 +614,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
dev_warn(&pdev->dev,
"Device DVSEC not present, skip CXL.mem init\n");
- rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
+ rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map);
if (rc)
return rc;
@@ -697,7 +627,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
* still be useful for management functions so don't return an error.
*/
cxlds->component_reg_phys = CXL_RESOURCE_NONE;
- rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
+ rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
if (rc)
dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
--
2.34.1
next prev parent reply other threads:[~2023-06-07 22:18 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-07 22:16 [PATCH v5 00/26] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-07 22:16 ` [PATCH v5 01/26] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-08 1:03 ` Dan Williams
2023-06-08 1:11 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 02/26] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-08 4:53 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 03/26] cxl: Rename member @dport of struct cxl_dport to @dev Terry Bowman
2023-06-08 6:42 ` Dan Williams
2023-06-08 14:36 ` Terry Bowman
2023-06-08 19:08 ` Dan Williams
2023-06-08 19:22 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 04/26] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-06-08 6:47 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 05/26] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-08 19:29 ` Dan Williams
2023-06-08 21:50 ` Terry Bowman
2023-06-07 22:16 ` Terry Bowman [this message]
2023-06-08 19:57 ` [PATCH v5 06/26] cxl/pci: Refactor component register discovery for reuse Dan Williams
2023-06-07 22:16 ` [PATCH v5 07/26] cxl/acpi: Moving add_host_bridge_uport() around Terry Bowman
2023-06-08 20:02 ` Dan Williams
2023-06-08 21:50 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 08/26] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-09 4:24 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 09/26] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-10 0:18 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 10/26] cxl/mem: Prepare for early RCH dport component register setup Terry Bowman
2023-06-10 0:26 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 11/26] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-10 1:36 ` Dan Williams
2023-06-10 1:44 ` Dan Williams
2023-06-12 20:39 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 12/26] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-10 2:18 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 13/26] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-10 2:23 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 14/26] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-10 2:29 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 15/26] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-06-10 2:34 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 16/26] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-10 2:36 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 17/26] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-10 2:37 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 18/26] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-06-10 2:38 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 19/26] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-10 3:09 ` Dan Williams
2023-06-12 14:41 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 20/26] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-10 3:11 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 21/26] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-10 3:12 ` Dan Williams
2023-06-12 21:12 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 22/26] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-10 3:23 ` Dan Williams
2023-06-12 18:19 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 23/26] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-12 20:29 ` Dan Williams
2023-06-13 15:28 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 24/26] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-12 21:38 ` Dan Williams
2023-06-16 16:17 ` Terry Bowman
2023-06-16 16:28 ` Terry Bowman
2023-06-07 22:16 ` [PATCH v5 25/26] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-08 22:54 ` kernel test robot
2023-06-12 22:49 ` Dan Williams
2023-06-07 22:16 ` [PATCH v5 26/26] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-08 19:21 ` Bjorn Helgaas
2023-06-12 22:57 ` Dan Williams
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