From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Paul Cercueil <paul@crapouillou.net>
Cc: Paul Burton <paulburton@kernel.org>,
Siarhei Volkau <lis8215@gmail.com>,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
list@opendingux.net
Subject: Re: [PATCH 1/4] MIPS: uaccess: emulate Ingenic LXW/LXH/LXHU uaccess
Date: Fri, 9 Jun 2023 10:22:42 +0200 [thread overview]
Message-ID: <20230609082242.GG8160@alpha.franken.de> (raw)
In-Reply-To: <20230604122655.69698-1-paul@crapouillou.net>
On Sun, Jun 04, 2023 at 02:26:52PM +0200, Paul Cercueil wrote:
> From: Siarhei Volkau <lis8215@gmail.com>
>
> The LXW, LXH, LXHU opcodes are part of the MXU ASE found in Ingenic
> XBurst based SoCs.
>
> While technically part of the MXU ASE, they do not touch any of the SIMD
> registers, and can be used even when the MXU ASE is disabled.
>
> This patch makes it possible to emulate unaligned access for those
> instructions.
>
> Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
> ---
> arch/mips/include/uapi/asm/inst.h | 33 +++++++++++++++++++++++++
> arch/mips/kernel/unaligned.c | 41 +++++++++++++++++++++++++++++++
> 2 files changed, 74 insertions(+)
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
prev parent reply other threads:[~2023-06-09 8:27 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-04 12:26 [PATCH 1/4] MIPS: uaccess: emulate Ingenic LXW/LXH/LXHU uaccess Paul Cercueil
2023-06-04 12:26 ` [PATCH 2/4] mips: ingenic: Remove useless __maybe_unused Paul Cercueil
2023-06-09 8:22 ` Thomas Bogendoerfer
2023-06-04 12:26 ` [PATCH 3/4] mips: ingenic: Enable EXT/2 divider on JZ4750/55/60 if EXT is 24 MHz Paul Cercueil
2023-06-09 8:23 ` Thomas Bogendoerfer
2023-06-04 12:26 ` [PATCH 4/4] MIPS: DTS: qi_lb60: Don't use unit address for regulators Paul Cercueil
2023-06-09 8:23 ` Thomas Bogendoerfer
2023-06-09 8:22 ` Thomas Bogendoerfer [this message]
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