Re: [PATCH v4 07/10] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC

Anup Patel
2023-06-15T05:47:38Z

On Thu, Jun 15, 2023 at 12:57 AM Conor Dooley <conor@kernel.org> wrote:
>
> Hey Anup,
>
> Mostly looks good, once minor comment.
>
> On Tue, Jun 13, 2023 at 09:04:12PM +0530, Anup Patel wrote:
>
> > + riscv,children:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + minItems: 1
> > + maxItems: 1024
> > + items:
> > + maxItems: 1
> > + description:
> > + A list of child APLIC domains for the given APLIC domain. Each child
> > + APLIC domain is assigned a child index in increasing order, with the
> > + first child APLIC domain assigned child index 0. The APLIC domain child
> > + index is used by firmware to delegate interrupts from the given APLIC
> > + domain to a particular child APLIC domain.
> > +
> > + riscv,delegation:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + minItems: 1
> > + maxItems: 1024
> > + items:
> > + items:
> > + - description: child APLIC domain phandle
> > + - description: first interrupt number of the parent APLIC domain (inclusive)
> > + - description: last interrupt number of the parent APLIC domain (inclusive)
> > + description:
> > + A interrupt delegation list where each entry is a triple consisting
> > + of child APLIC domain phandle, first interrupt number of the parent
> > + APLIC domain, and last interrupt number of the parent APLIC domain.
> > + Firmware must configure interrupt delegation registers based on
> > + interrupt delegation list.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupt-controller
> > + - "#interrupt-cells"
> > + - riscv,num-sources
> > +
> > +anyOf:
> > + - required:
> > + - interrupts-extended
> > + - required:
> > + - msi-parent
>
> Not sure if you missed this from the last version, but I asked if we
> needed a
> dependencies:
> riscv,delegate: [ riscv,children ]
>
> IOW, I don't think it is valid to have a delegation without having
> children?

Ahh, yes. I missed this one. I will update in the next revision.

>
> Otherwise,
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Cheers,
> Conor.

Regards,
Anup