From: Yang Li <yang.lee@linux.alibaba.com>
To: sboyd@kernel.org
Cc: mturquette@baylibre.com, orsonzhai@gmail.com,
baolin.wang@linux.alibaba.com, zhang.lyra@gmail.com,
pdeschrijver@nvidia.com, pgaikwad@nvidia.com,
thierry.reding@gmail.com, jonathanh@nvidia.com,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Yang Li <yang.lee@linux.alibaba.com>,
Abaci Robot <abaci@linux.alibaba.com>
Subject: [PATCH -next 3/3] clk: tegra: Fix unsigned comparison with less than zero
Date: Wed, 14 Jun 2023 09:29:13 +0800 [thread overview]
Message-ID: <20230614012913.122220-3-yang.lee@linux.alibaba.com> (raw)
In-Reply-To: <20230614012913.122220-1-yang.lee@linux.alibaba.com>
The return value of the round_rate() is long. However, the
return value is being assigned to an unsigned long variable
'rate', so making 'rate' to long.
silence the warnings:
./drivers/clk/tegra/clk-periph.c:59:5-9: WARNING: Unsigned expression compared with zero: rate < 0
./drivers/clk/tegra/clk-super.c:156:5-9: WARNING: Unsigned expression compared with zero: rate < 0
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5519
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
---
drivers/clk/tegra/clk-periph.c | 2 +-
drivers/clk/tegra/clk-super.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 0626650a7011..9eaac49facd4 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -51,7 +51,7 @@ static int clk_periph_determine_rate(struct clk_hw *hw,
struct tegra_clk_periph *periph = to_clk_periph(hw);
const struct clk_ops *div_ops = periph->div_ops;
struct clk_hw *div_hw = &periph->divider.hw;
- unsigned long rate;
+ long rate;
__clk_hw_set_clk(div_hw, hw);
diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 7ec47942720c..7a121de526c0 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -147,7 +147,7 @@ static int clk_super_determine_rate(struct clk_hw *hw,
{
struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
struct clk_hw *div_hw = &super->frac_div.hw;
- unsigned long rate;
+ long rate;
__clk_hw_set_clk(div_hw, hw);
--
2.20.1.7.g153144c
next prev parent reply other threads:[~2023-06-14 1:29 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-14 1:29 [PATCH -next 1/3] clk: sprd: composite: Fix unsigned comparison with less than zero Yang Li
2023-06-14 1:29 ` [PATCH -next 2/3] clk: stm32: core: " Yang Li
2023-06-14 19:57 ` Stephen Boyd
2023-06-14 1:29 ` Yang Li [this message]
2023-06-14 20:01 ` [PATCH -next 3/3] clk: tegra: " Stephen Boyd
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