From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56D55EB64D9 for ; Thu, 15 Jun 2023 09:55:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245618AbjFOJzs (ORCPT ); Thu, 15 Jun 2023 05:55:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343787AbjFOJzP (ORCPT ); Thu, 15 Jun 2023 05:55:15 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 564E326B8; Thu, 15 Jun 2023 02:55:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686822911; x=1718358911; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=tgLchCQOCm3NxEtP7yRUXwmiZkL4G/bjAirc8TrgyEY=; b=QwNF9fBHEY2EapsOvVGDhwdjERdA5zB/Tl3iixCWWt6WMgLzGkpyMgev CfKEu59Iqdq4M5x/wjIMZa6mFMoNd/EAu16aEBhxQ27dhNMUut0l2TgRB gXKdfQqAlNKkdakkTE1f+TfFu+YOUSPu+FCeBEArm7KkiZxR9XGDl9uvn XvGv8WI5B3TAj/kqlZvezSd8xnAN0j9rrCQzmOYua2U7d2WyRaQ23cArW Adghvj820Qc8bIN++vFyat4zfhV18ZPGjtXqEMQ9ckQ6NRH9+LYA8XAm/ RsuHXFKcy05iFM3A2NJOjYfzeL5Ob7FYSV0qqkPfgTckiqbLbG/NQHbCP Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10741"; a="357746579" X-IronPort-AV: E=Sophos;i="6.00,244,1681196400"; d="scan'208";a="357746579" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2023 02:55:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10741"; a="706598947" X-IronPort-AV: E=Sophos;i="6.00,244,1681196400"; d="scan'208";a="706598947" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga007.jf.intel.com with ESMTP; 15 Jun 2023 02:55:08 -0700 Received: by black.fi.intel.com (Postfix, from userid 1001) id 7769D403; Thu, 15 Jun 2023 12:55:17 +0300 (EEST) Date: Thu, 15 Jun 2023 12:55:17 +0300 From: "mika.westerberg@linux.intel.com" To: "Jadav, Raag" Cc: Andy Shevchenko , "linus.walleij@linaro.org" , "linux-gpio@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "Sangannavar, Mallikarjunappa" , "N, Pandith" Subject: Re: [PATCH v3 2/3] pinctrl: intel: refine ->irq_set_type() hook Message-ID: <20230615095517.GV45886@black.fi.intel.com> References: <20230613085054.10976-1-raag.jadav@intel.com> <20230613085054.10976-3-raag.jadav@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jun 15, 2023 at 09:48:12AM +0000, Jadav, Raag wrote: > > On Tue, Jun 13, 2023 at 02:20:53PM +0530, Raag Jadav wrote: > > > Utilize a temporary variable for common shift operation in > > > ->irq_set_type() hook and improve readability. > > > While at it, simplify if-else-if chain and save a few bytes. > > > > > > add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-16 (-16) > > > Function old new delta > > > intel_gpio_irq_type 317 301 -16 > > > Total: Before=10469, After=10453, chg -0.15% > > > > ... > > > > > value = readl(reg); > > > - > > > value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); > > > > > > if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { > > > - value |= PADCFG0_RXEVCFG_EDGE_BOTH << > > PADCFG0_RXEVCFG_SHIFT; > > > + rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH; > > > } else if (type & IRQ_TYPE_EDGE_FALLING) { > > > - value |= PADCFG0_RXEVCFG_EDGE << > > PADCFG0_RXEVCFG_SHIFT; > > > - value |= PADCFG0_RXINV; > > > + rxevcfg = PADCFG0_RXEVCFG_EDGE; > > > } else if (type & IRQ_TYPE_EDGE_RISING) { > > > - value |= PADCFG0_RXEVCFG_EDGE << > > PADCFG0_RXEVCFG_SHIFT; > > > + rxevcfg = PADCFG0_RXEVCFG_EDGE; > > > } else if (type & IRQ_TYPE_LEVEL_MASK) { > > > - if (type & IRQ_TYPE_LEVEL_LOW) > > > - value |= PADCFG0_RXINV; > > > + rxevcfg = PADCFG0_RXEVCFG_LEVEL; > > > } else { > > > - value |= PADCFG0_RXEVCFG_DISABLED << > > PADCFG0_RXEVCFG_SHIFT; > > > + rxevcfg = PADCFG0_RXEVCFG_DISABLED; > > > } > > > > > > + if (type == IRQ_TYPE_EDGE_FALLING || type == > > IRQ_TYPE_LEVEL_LOW) > > > + value |= PADCFG0_RXINV; > > > + > > > + value |= rxevcfg << PADCFG0_RXEVCFG_SHIFT; > > > writel(value, reg); > > > > Looking at this I realized that entire temporary variable assignments can be > > done outside of spin lock. You probably would need another one for keeping > > rxinv value. > > Something like this? > > u32 value, rxevcfg; > u32 rxinv = 0; > > if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { > rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH; > } else if (type & IRQ_TYPE_EDGE_FALLING) { > rxevcfg = PADCFG0_RXEVCFG_EDGE; > } else if (type & IRQ_TYPE_EDGE_RISING) { > rxevcfg = PADCFG0_RXEVCFG_EDGE; > } else if (type & IRQ_TYPE_LEVEL_MASK) { > rxevcfg = PADCFG0_RXEVCFG_LEVEL; > } else { > rxevcfg = PADCFG0_RXEVCFG_DISABLED; > } > > if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) > rxinv = PADCFG0_RXINV; > > raw_spin_lock_irqsave(&pctrl->lock, flags); > > intel_gpio_set_gpio_mode(reg); > > value = readl(reg); > > value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV); > value |= rxinv; > value |= rxevcfg << PADCFG0_RXEVCFG_SHIFT; > > writel(value, reg); This one looks better. > > Will it give us any memory reduction in comparison to the current code? > > add/remove: 0/0 grow/shrink: 1/0 up/down: 4/0 (4) > Function old new delta > intel_gpio_irq_type 317 321 +4 > Total: Before=10469, After=10473, chg +0.04% > > Unfortunately gcc doesn't seem to consider this as best of the sequence, > and I'm not entirely sure why. It's fine as is, readability counts more than few bytes here.