Re: [PATCH bpf-next v3 3/3] bpf, arm64: use bpf_jit_binary_pack_alloc

Alexei Starovoitov
2023-06-21T16:25:12Z

On Wed, Jun 21, 2023 at 8:31 AM Mark Rutland <mark.rutland@arm.com> wrote:
>
> On Mon, Jun 19, 2023 at 10:01:21AM +0000, Puranjay Mohan wrote:
> > Use bpf_jit_binary_pack_alloc for memory management of JIT binaries in
> > ARM64 BPF JIT. The bpf_jit_binary_pack_alloc creates a pair of RW and RX
> > buffers. The JIT writes the program into the RW buffer. When the JIT is
> > done, the program is copied to the final RX buffer
> > with bpf_jit_binary_pack_finalize.
> >
> > Implement bpf_arch_text_copy() and bpf_arch_text_invalidate() for ARM64
> > JIT as these functions are required by bpf_jit_binary_pack allocator.
> >
> > Signed-off-by: Puranjay Mohan <puranjay12@gmail.com>
>
> From a quick look, I don't beleive the I-cache maintenance is quite right --
> explanation below.
>
> > @@ -1562,34 +1610,39 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
> >
> > /* 3. Extra pass to validate JITed code. */
> > if (validate_ctx(&ctx)) {
> > - bpf_jit_binary_free(header);
> > prog = orig_prog;
> > - goto out_off;
> > + goto out_free_hdr;
> > }
> >
> > /* And we're done. */
> > if (bpf_jit_enable > 1)
> > bpf_jit_dump(prog->len, prog_size, 2, ctx.image);
> >
> > - bpf_flush_icache(header, ctx.image + ctx.idx);
> > + bpf_flush_icache(ro_header, ctx.ro_image + ctx.idx);
>
> I think this is too early; we haven't copied the instructions into the
> ro_header yet, so that still contains stale instructions.
>
> IIUC at the whole point of this is to pack multiple programs into shared ROX
> pages, and so there can be an executable mapping of the RO page at this point,
> and the CPU can fetch stale instructions throught that.
>
> Note that *regardless* of whether there is an executeable mapping at this point
> (and even if no executable mapping exists until after the copy), we at least
> need a data cache clean to the PoU *after* the copy (so fetches don't get a
> stale value from the PoU), and the I-cache maintenance has to happeon the VA
> the instrutions will be executed from (or VIPT I-caches can still contain stale
> instructions).

Good catch.
Also considering the boot issue reported in the other thread
I removed this series from bpf-next.
Looks like another respin is necessary.