Re: [PATCH v4 1/5] mtd: rawnand: qcom: Implement exec_op()

[kernel test robot <lkp@intel.com>]

Hi Md,

kernel test robot noticed the following build warnings:

[auto build test WARNING on mtd/nand/next]
[also build test WARNING on linus/master v6.4-rc7 next-20230620]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Md-Sadre-Alam/mtd-rawnand-qcom-Add-support-for-reset-readid-status-exec_op/20230615-153448
base:   https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next
patch link:    https://lore.kernel.org/r/20230615073143.25079-1-quic_mdalam%40quicinc.com
patch subject: [PATCH v4 1/5] mtd: rawnand: qcom: Implement exec_op()
config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20230620/202306201734.SmmrhWYJ-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230620/202306201734.SmmrhWYJ-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306201734.SmmrhWYJ-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/mtd/nand/raw/qcom_nandc.c: In function 'qcom_parse_instructions':
>> drivers/mtd/nand/raw/qcom_nandc.c:2944:38: warning: variable 'naddrs' set but not used [-Wunused-but-set-variable]
    2944 |                 unsigned int offset, naddrs;
         |                                      ^~~~~~
   drivers/mtd/nand/raw/qcom_nandc.c: At top level:
   drivers/mtd/nand/raw/qcom_nandc.c:2932:13: warning: 'qcom_parse_instructions' defined but not used [-Wunused-function]
    2932 | static void qcom_parse_instructions(struct nand_chip *chip,
         |             ^~~~~~~~~~~~~~~~~~~~~~~


vim +/naddrs +2944 drivers/mtd/nand/raw/qcom_nandc.c

  2930	
  2931	/* NAND framework ->exec_op() hooks and related helpers */
  2932	static void qcom_parse_instructions(struct nand_chip *chip,
  2933					    const struct nand_subop *subop,
  2934						struct qcom_op *q_op)
  2935	{
  2936		struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
  2937		const struct nand_op_instr *instr = NULL;
  2938		unsigned int op_id;
  2939		int i;
  2940	
  2941		memset(q_op, 0, sizeof(*q_op));
  2942	
  2943		for (op_id = 0; op_id < subop->ninstrs; op_id++) {
> 2944			unsigned int offset, naddrs;
  2945			const u8 *addrs;
  2946	
  2947			instr = &subop->instrs[op_id];
  2948	
  2949			switch (instr->type) {
  2950			case NAND_OP_CMD_INSTR:
  2951				q_op->cmd_reg = qcom_op_cmd_mapping(nandc, instr->ctx.cmd.opcode, q_op);
  2952				q_op->rdy_delay_ns = instr->delay_ns;
  2953				break;
  2954	
  2955			case NAND_OP_ADDR_INSTR:
  2956				offset = nand_subop_get_addr_start_off(subop, op_id);
  2957				naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
  2958				addrs = &instr->ctx.addr.addrs[offset];
  2959				for (i = 0; i < MAX_ADDRESS_CYCLE; i++) {
  2960					if (i < 4)
  2961						q_op->addr1_reg |= (u32)addrs[i] << i * 8;
  2962					else
  2963						q_op->addr2_reg |= addrs[i];
  2964				}
  2965				q_op->rdy_delay_ns = instr->delay_ns;
  2966				break;
  2967	
  2968			case NAND_OP_DATA_IN_INSTR:
  2969				q_op->data_instr = instr;
  2970				q_op->data_instr_idx = op_id;
  2971				q_op->rdy_delay_ns = instr->delay_ns;
  2972				fallthrough;
  2973			case NAND_OP_DATA_OUT_INSTR:
  2974				q_op->rdy_delay_ns = instr->delay_ns;
  2975				break;
  2976	
  2977			case NAND_OP_WAITRDY_INSTR:
  2978				q_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;
  2979				q_op->rdy_delay_ns = instr->delay_ns;
  2980				break;
  2981			}
  2982		}
  2983	}
  2984	

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