From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
<linux-cxl@vger.kernel.org>, <rrichter@amd.com>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: Re: [PATCH v6 03/27] cxl: Updates for CXL Test to work with RCH
Date: Thu, 22 Jun 2023 10:53:26 +0100 [thread overview]
Message-ID: <20230622105326.00006302@Huawei.com> (raw)
In-Reply-To: <20230622035126.4130151-4-terry.bowman@amd.com>
On Wed, 21 Jun 2023 22:51:02 -0500
Terry Bowman <terry.bowman@amd.com> wrote:
> From: Dan Williams <dan.j.williams@intel.com>
>
> CXL test needs to be updated to work with latest RCH changes.
> Add CXL test support for devm_cxl_add_rch_dport and
> cxl_rcd_component_reg_phys functions.
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Robert Richter <rrichter@amd.com>
This chain is getting confusing.
Why a SoB from Robert on this one?
As Terry sent the series I'd expect Terry to be last unless there
was some codevelopment involved in which case that should be indicated
in the tags.
For weird corner cases it's worth adding some comments on why a SoB chain
is non obvious.
I'm far from an expert on cxl-test so I'll leave reviewing this in
depth to others. FWIW looks fine to me.
Jonathan
next prev parent reply other threads:[~2023-06-22 9:56 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-22 3:50 [PATCH v6 00/27] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-22 3:51 ` [PATCH v6 01/27] cxl/port: Fix NULL pointer access in devm_cxl_add_port() Terry Bowman
2023-06-22 7:17 ` Robert Richter
2023-06-22 3:51 ` [PATCH v6 02/27] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-22 22:36 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 03/27] cxl: Updates for CXL Test to work with RCH Terry Bowman
2023-06-22 9:53 ` Jonathan Cameron [this message]
2023-06-22 10:03 ` Robert Richter
2023-06-22 14:02 ` Terry Bowman
2023-06-22 22:38 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 04/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-22 22:51 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 05/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev Terry Bowman
2023-06-22 9:54 ` Jonathan Cameron
2023-06-22 22:53 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 06/27] cxl: Rename 'uport' to 'uport_dev' Terry Bowman
2023-06-22 9:56 ` Jonathan Cameron
2023-06-22 22:54 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 07/27] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-22 11:14 ` Jonathan Cameron
2023-06-22 23:07 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 08/27] cxl/pci: Refactor component register discovery for reuse Terry Bowman
2023-06-22 23:14 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 09/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs() Terry Bowman
2023-06-22 23:17 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 10/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-22 23:28 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 11/27] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-22 23:47 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 12/27] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-22 23:48 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 13/27] cxl/mem: Prepare for early RCH dport component register setup Terry Bowman
2023-06-22 11:17 ` Jonathan Cameron
2023-06-22 23:50 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 14/27] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-22 23:58 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 15/27] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-22 13:20 ` Jonathan Cameron
2023-06-23 0:00 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 16/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-23 0:01 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 17/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-23 0:02 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 18/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-06-23 0:03 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 19/27] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-23 0:04 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 20/27] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-22 13:17 ` Jonathan Cameron
2023-06-23 0:10 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 21/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-22 3:51 ` [PATCH v6 22/27] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-22 3:51 ` [PATCH v6 23/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-22 13:16 ` Jonathan Cameron
2023-06-22 14:42 ` Terry Bowman
2023-06-22 3:51 ` [PATCH v6 24/27] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-22 3:51 ` [PATCH v6 25/27] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-22 13:12 ` Jonathan Cameron
2023-06-22 16:33 ` Terry Bowman
2023-06-23 13:28 ` Jonathan Cameron
2023-06-22 3:51 ` [PATCH v6 26/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-22 3:51 ` [PATCH v6 27/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-22 13:07 ` Jonathan Cameron
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