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From: Terry Bowman <terry.bowman@amd.com>
To: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
	<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
	<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
	<Jonathan.Cameron@huawei.com>, <linux-cxl@vger.kernel.org>
Cc: <terry.bowman@amd.com>, <rrichter@amd.com>,
	<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: [PATCH v7 16/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
Date: Thu, 22 Jun 2023 15:55:12 -0500	[thread overview]
Message-ID: <20230622205523.85375-17-terry.bowman@amd.com> (raw)
In-Reply-To: <20230622205523.85375-1-terry.bowman@amd.com>

From: Robert Richter <rrichter@amd.com>

Same as for ports and dports, also store the endpoint's Component
Register mappings, use struct cxl_dev_state for that.

The Component Register base address @component_reg_phys is no longer
used after the rework of the Component Register setup which now uses
struct member @comp_map instead. Remove the base address.

Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/cxl/cxlmem.h         |  5 ++---
 drivers/cxl/mem.c            |  4 ++--
 drivers/cxl/pci.c            | 10 ++++------
 tools/testing/cxl/test/mem.c |  1 -
 4 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 76743016b64c..8aee1a42d9af 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -263,6 +263,7 @@ struct cxl_poison_state {
  *
  * @dev: The device associated with this CXL state
  * @cxlmd: The device representing the CXL.mem capabilities of @dev
+ * @comp_map: component register capability mappings
  * @regs: Parsed register blocks
  * @cxl_dvsec: Offset to the PCIe device DVSEC
  * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
@@ -286,7 +287,6 @@ struct cxl_poison_state {
  * @active_persistent_bytes: sum of hard + soft persistent
  * @next_volatile_bytes: volatile capacity change pending device reset
  * @next_persistent_bytes: persistent capacity change pending device reset
- * @component_reg_phys: register base of component registers
  * @info: Cached DVSEC information about the device.
  * @serial: PCIe Device Serial Number
  * @event: event log driver state
@@ -299,7 +299,7 @@ struct cxl_poison_state {
 struct cxl_dev_state {
 	struct device *dev;
 	struct cxl_memdev *cxlmd;
-
+	struct cxl_register_map comp_map;
 	struct cxl_regs regs;
 	int cxl_dvsec;
 
@@ -325,7 +325,6 @@ struct cxl_dev_state {
 	u64 next_volatile_bytes;
 	u64 next_persistent_bytes;
 
-	resource_size_t component_reg_phys;
 	u64 serial;
 
 	struct cxl_event_state event;
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 205e2e280aed..92c6151b7206 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -49,7 +49,6 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
 				 struct cxl_dport *parent_dport)
 {
 	struct cxl_port *parent_port = parent_dport->port;
-	struct cxl_dev_state *cxlds = cxlmd->cxlds;
 	struct cxl_port *endpoint, *iter, *down;
 	int rc;
 
@@ -65,8 +64,9 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
 		ep->next = down;
 	}
 
+	/* The Endpoint's component regs are located in cxlds. */
 	endpoint = devm_cxl_add_port(host, &cxlmd->dev,
-				     cxlds->component_reg_phys,
+				     CXL_RESOURCE_NONE,
 				     parent_dport);
 	if (IS_ERR(endpoint))
 		return PTR_ERR(endpoint);
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 99a75c54ee39..ad4cfcd95e17 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -665,16 +665,14 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	 * If the component registers can't be found, the cxl_pci driver may
 	 * still be useful for management functions so don't return an error.
 	 */
-	cxlds->component_reg_phys = CXL_RESOURCE_NONE;
-	rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
+	rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,
+				&cxlds->comp_map);
 	if (rc)
 		dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
-	else if (!map.component_map.ras.valid)
+	else if (!cxlds->comp_map.component_map.ras.valid)
 		dev_dbg(&pdev->dev, "RAS registers not found\n");
 
-	cxlds->component_reg_phys = map.resource;
-
-	rc = cxl_map_component_regs(&map, &cxlds->regs.component,
+	rc = cxl_map_component_regs(&cxlds->comp_map, &cxlds->regs.component,
 				    BIT(CXL_CM_CAP_CAP_ID_RAS));
 	if (rc)
 		dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");
diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
index 34b48027b3de..fd562a5fa06f 100644
--- a/tools/testing/cxl/test/mem.c
+++ b/tools/testing/cxl/test/mem.c
@@ -1241,7 +1241,6 @@ static int cxl_mock_mem_probe(struct platform_device *pdev)
 	cxlds->event.buf = (struct cxl_get_event_payload *) mdata->event_buf;
 	if (is_rcd(pdev)) {
 		cxlds->rcd = true;
-		cxlds->component_reg_phys = CXL_RESOURCE_NONE;
 	}
 
 	rc = cxl_enumerate_cmds(cxlds);
-- 
2.34.1


  parent reply	other threads:[~2023-06-22 21:02 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-22 20:54 [PATCH v7 00/27] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-22 20:54 ` [PATCH v7 01/27] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-25 19:34   ` Dan Williams
2023-06-22 20:54 ` [PATCH v7 02/27] cxl: Updates for CXL Test to work with RCH Terry Bowman
2023-06-22 20:54 ` [PATCH v7 03/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-22 20:55 ` [PATCH v7 04/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev Terry Bowman
2023-06-22 20:55 ` [PATCH v7 05/27] cxl: Rename 'uport' to 'uport_dev' Terry Bowman
2023-06-22 20:55 ` [PATCH v7 06/27] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-22 20:55 ` [PATCH v7 07/27] cxl/pci: Refactor component register discovery for reuse Terry Bowman
2023-06-22 20:55 ` [PATCH v7 08/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs() Terry Bowman
2023-06-22 20:55 ` [PATCH v7 09/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-22 20:55 ` [PATCH v7 10/27] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-22 20:55 ` [PATCH v7 11/27] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-22 20:55 ` [PATCH v7 12/27] cxl/mem: Prepare for early RCH dport component register setup Terry Bowman
2023-06-22 20:55 ` [PATCH v7 13/27] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-22 20:55 ` [PATCH v7 14/27] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-23 13:32   ` Jonathan Cameron
2023-06-22 20:55 ` [PATCH v7 15/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-22 20:55 ` Terry Bowman [this message]
2023-06-25 17:38   ` [PATCH v7 16/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Dan Williams
2023-06-26 14:16     ` Terry Bowman
2023-06-30 19:51     ` Robert Richter
2023-06-30 19:56     ` Robert Richter
2023-07-03  3:55       ` Jonathan Cameron
2023-06-22 20:55 ` [PATCH v7 17/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-06-22 20:55 ` [PATCH v7 18/27] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-22 20:55 ` [PATCH v7 19/27] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-22 20:55 ` [PATCH v7 20/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-23 21:22   ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 21/27] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-23 21:43   ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 22/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-23 21:58   ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 23/27] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-23 22:07   ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 24/27] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-23 22:08   ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 25/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-23 22:16   ` Dave Jiang
2023-06-25  5:47     ` Dan Williams
2023-06-22 20:55 ` [PATCH v7 26/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-23 22:18   ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 27/27] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-06-23 13:30   ` Jonathan Cameron
2023-06-23 22:19   ` Dave Jiang

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