From: Terry Bowman <terry.bowman@amd.com>
To: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
<Jonathan.Cameron@huawei.com>, <linux-cxl@vger.kernel.org>
Cc: <terry.bowman@amd.com>, <rrichter@amd.com>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: [PATCH v7 18/27] cxl/port: Remove Component Register base address from struct cxl_port
Date: Thu, 22 Jun 2023 15:55:14 -0500 [thread overview]
Message-ID: <20230622205523.85375-19-terry.bowman@amd.com> (raw)
In-Reply-To: <20230622205523.85375-1-terry.bowman@amd.com>
From: Robert Richter <rrichter@amd.com>
The Component Register base address @component_reg_phys is no longer
used after the rework of the Component Register setup which now uses
struct member @comp_map instead. Remove the base address.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/cxl/core/port.c | 4 +---
drivers/cxl/cxl.h | 2 --
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index cbd3d17f6410..95d5aae1f97b 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -616,7 +616,6 @@ static int devm_cxl_link_parent_dport(struct device *host,
static struct lock_class_key cxl_port_key;
static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
- resource_size_t component_reg_phys,
struct cxl_dport *parent_dport)
{
struct cxl_port *port;
@@ -667,7 +666,6 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
} else
dev->parent = uport_dev;
- port->component_reg_phys = component_reg_phys;
ida_init(&port->decoder_ida);
port->hdm_end = -1;
port->commit_end = -1;
@@ -727,7 +725,7 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host,
struct device *dev;
int rc;
- port = cxl_port_alloc(uport_dev, component_reg_phys, parent_dport);
+ port = cxl_port_alloc(uport_dev, parent_dport);
if (IS_ERR(port))
return port;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index b1adca9b27ba..9f46a4e1fbec 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -551,7 +551,6 @@ struct cxl_dax_region {
* @nr_dports: number of entries in @dports
* @hdm_end: track last allocated HDM decoder instance for allocation ordering
* @commit_end: cursor to track highest committed decoder for commit ordering
- * @component_reg_phys: component register capability base address (optional)
* @dead: last ep has been removed, force port re-creation
* @depth: How deep this port is relative to the root. depth 0 is the root.
* @cdat: Cached CDAT data
@@ -571,7 +570,6 @@ struct cxl_port {
int nr_dports;
int hdm_end;
int commit_end;
- resource_size_t component_reg_phys;
bool dead;
unsigned int depth;
struct cxl_cdat {
--
2.34.1
next prev parent reply other threads:[~2023-06-22 21:03 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-22 20:54 [PATCH v7 00/27] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-22 20:54 ` [PATCH v7 01/27] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-25 19:34 ` Dan Williams
2023-06-22 20:54 ` [PATCH v7 02/27] cxl: Updates for CXL Test to work with RCH Terry Bowman
2023-06-22 20:54 ` [PATCH v7 03/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-22 20:55 ` [PATCH v7 04/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev Terry Bowman
2023-06-22 20:55 ` [PATCH v7 05/27] cxl: Rename 'uport' to 'uport_dev' Terry Bowman
2023-06-22 20:55 ` [PATCH v7 06/27] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-22 20:55 ` [PATCH v7 07/27] cxl/pci: Refactor component register discovery for reuse Terry Bowman
2023-06-22 20:55 ` [PATCH v7 08/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs() Terry Bowman
2023-06-22 20:55 ` [PATCH v7 09/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-22 20:55 ` [PATCH v7 10/27] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-22 20:55 ` [PATCH v7 11/27] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-22 20:55 ` [PATCH v7 12/27] cxl/mem: Prepare for early RCH dport component register setup Terry Bowman
2023-06-22 20:55 ` [PATCH v7 13/27] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-22 20:55 ` [PATCH v7 14/27] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-23 13:32 ` Jonathan Cameron
2023-06-22 20:55 ` [PATCH v7 15/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-22 20:55 ` [PATCH v7 16/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-25 17:38 ` Dan Williams
2023-06-26 14:16 ` Terry Bowman
2023-06-30 19:51 ` Robert Richter
2023-06-30 19:56 ` Robert Richter
2023-07-03 3:55 ` Jonathan Cameron
2023-06-22 20:55 ` [PATCH v7 17/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-06-22 20:55 ` Terry Bowman [this message]
2023-06-22 20:55 ` [PATCH v7 19/27] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-22 20:55 ` [PATCH v7 20/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-23 21:22 ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 21/27] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-23 21:43 ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 22/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-23 21:58 ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 23/27] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-23 22:07 ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 24/27] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-23 22:08 ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 25/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-23 22:16 ` Dave Jiang
2023-06-25 5:47 ` Dan Williams
2023-06-22 20:55 ` [PATCH v7 26/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-23 22:18 ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 27/27] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-06-23 13:30 ` Jonathan Cameron
2023-06-23 22:19 ` Dave Jiang
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