[PATCH v7 00/27] cxl/pci: Add support for RCH RAS error handling

Terry Bowman
2023-06-22T20:55:43Z

Patches #1 to #18 are a rework of the Component Register setup. This
is needed to share multiple CXL capabilities (HDM and RAS) for the
same component, also there can be different components implementing
the same capability, finally RCH mode should be supported too. The
general approach to solve this is to:

* Unify code for components and capabilities in VH and RCH modes.

* Early setup of the Component Register base address.

* Create and store the register mappings to later use it for mapping
the capability I/O ranges.

Patches #19 to #27 enable CXL RCH error handling. These are needed because
RCH downstream port protocol error handling is implemented uniquely and not
currently supported. These patches address the following:

* Discovery and mapping of RCH downstream port AER registers.

* AER portdrv changes to support CXL RCH protocol errors.

* Interrupt setup specific to RCH mode: enabling RCEC internal
errors and disabling root port interrupts.

Changes in V7:
- cxl: Updates for CXL Test to work with RCH
- Removed Robert's DSO.
- cxl/core/regs: Add @dev to cxl_register_map
- Corrected typo in patch description.
- PCI/AER: Unmask RCEC internal errors to enable RCH downstream port
error handling.
- Changed int variable to bool.
- cxl/pci: Map RCH downstream AER registers for logging protocol errors
- Corrected patch description.
- cxl/pci: Add RCH downstream port AER register discovery
- Reverted empty line removal.
- cxl/port: Store the port's Component Register mappings in struct
cxl_port
- Update to use structure initialization in cxl_setup_comp_regs().
- Remove first patch (already in the tree) and added patch 27/27.
- Was a one-off error caused when merging branches during internal
review.

Changes in V6:
- Added patch for cxl test fixes: 'cxl: Update CXl Test to Work with
RCH'. Patch from Dan.
- Simplified: 'cxl/rch: Prepare for caching the MMIO mapped PCIe AER
capability'. Patch from Dan.
- Added patch: 'cxl: Rename 'uport' to 'uport_dev''
- Updated patch: 'cxl: Rename member @dport of struct cxl_dport to
@dport_dev'
- Updated *map assignment to use structure init in 'cxl/core/regs: Add
@dev to cxl_register_map'. Also fixed whitespace.
- Removed extra whitespace in 'cxl/core/regs: Add @dev to
cxl_register_map'
- Updated patch subject: 'cxl/acpi: Move add_host_bridge_uport() after
cxl_get_chbs()'
- Changes to work with CXL test. 'cxl/acpi: Directly bind the CEDT
detected CHBCR to the Host Bridge's port'
- 'cxl/pci: Early setup RCH dport component registers from RCRB'
- Removed parameter from cxl_rcrb_get_comp_regs().
- Changed return value to EPROBE_DEFER for retry during ACPI
initialization.
- Changed map to us struct initialization.
- Remove ENODEV check in 'cxl/port: Store the downstream port's
Component Register mappings in struct cxl_dport'
- 'cxl/port: Remove Component Register base address from struct
cxl_dport'
- Moved earlier with same removal for cxl_port.
- cxl/pci: Add RCH downstream port AER register discovery
- Flattened {request,release}_mem_region() and ioremap() into
cxl_rcrb_to_aer().
- Add check if OS is assigned AER handling before discovering AER.
- Added CXL namespace import to cxl_core (drivers/cxl/core/port.c).
Needed for using pci_print_aer(). In 'PCI/AER: Refactor
cper_print_aer() for use by CXL driver module'.
- cxl/pci: Map RCH downstream AER registers for logging protocol errors
- Changed dport device used in devm_cxl_iomap_block() call to be
port->dev.
- Removed ENODEV check.
- cxl/pci: Disable root port interrupts in RCH mode
- Removed unnecessary 'rch' check.
- Moved cxl_disable_rch_root_ints() into core/pci.c.
- Added OSC AER assignment check before accessing AER registers.
- cxl/pci: Update CXL error logging to use RAS register address
- Renamed function handlers.
- cxl/pci: Add RCH downstream port error logging
- Moved RCD check to caller.
- Added put_dev() after call to cxl_pci_find_port().

Changes in V5:
- Split 'cxl/rch: Prepare for logging RCH downstream port protocol
errors' patch into 2 patches.
- Added:
cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
cxl/mem: Prepare for early RCH dport component register setup
- Correct comments CXL3.0 to CXL 3.0.
- changed cxl_port_get_comp_map() to static.

Changes in V4:
- Made port RAS register discovery common and called from
__devm_cxl_add_dport().
- Changed RCH AER register discovery to be called from
__devm_cxl_add_dport().
- Changed RAS and RCH AER register mapping to be called from
__devm_cxl_add_dport().
- Changed component register mapping to support all CXL component
mapping, cxl_map_component_regs().
- Added cxl_regs to 'struct cxl_dport' for providing RCH downstream port
mapped registers USED in error handler.
- PCI/AER:
- Improved description of PCIEAER_CXL option in Kconfig.
- Renamed function to pci_aer_unmask_internal_errors(), added
pcie_aer_is_native() check.
- Improved comments and added spec refs.
- Renamed functions to cxl_rch_handle_error*().
- Modified cxl_rch_handle_error_iter() to only call the handler
callbacks, this also simplifies refcounting of the pdev.
- Refactored handle_error_source(), created pci_aer_handle_error().
- Changed printk messages to pci_*() variants.
- Added check for pcie_aer_is_native() to the RCEC.
- Introduced function cxl_rch_enable_rcec().
- Updated patch description ("PCI/AER: Forward RCH downstream
port-detected errors to the CXL.mem dev handler").

Changes in V3:
- Correct base commit in cover sheet.
- Change hardcoded return 0 to NULL in regs.c.
- Remove calls to pci_disable_pcie_error_reporting(pdev) and
pci_enable_pcie_error_reporting(pdev) in mem.c;
- Move RCEC interrupt unmask to PCIe port AER driver's probe.
- Fixes missing PCIEAER and PCIEPORTBUS config option error.
- Rename cxl_rcrb_setup() to cxl_setup_rcrb() in mem.c.
- Update cper_mem_err_unpack() patch subject and description.

Changes in V2:
- Refactor RCH initialization into cxl_mem driver.
- Includes RCH RAS and AER register discovery and mapping.
- Add RCEC protocol error interrupt forwarding to CXL endpoint
handler.
- Change AER and RAS logging to use existing trace routines.
- Enable RCEC AER internal errors.

Dan Williams (3):
cxl: Updates for CXL Test to work with RCH
cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
cxl: Rename 'uport' to 'uport_dev'

Robert Richter (17):
cxl/acpi: Probe RCRB later during RCH downstream port creation
cxl: Rename member @dport of struct cxl_dport to @dport_dev
cxl/core/regs: Add @dev to cxl_register_map
cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs()
cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's
port
cxl/port: Remove Component Register base address from struct cxl_dport
cxl/regs: Remove early capability checks in Component Register setup
cxl/mem: Prepare for early RCH dport component register setup
cxl/pci: Early setup RCH dport component registers from RCRB
cxl/port: Store the port's Component Register mappings in struct
cxl_port
cxl/port: Store the downstream port's Component Register mappings in
struct cxl_dport
cxl/pci: Store the endpoint's Component Register mappings in struct
cxl_dev_state
cxl/hdm: Use stored Component Register mappings to map HDM decoder
capability
cxl/port: Remove Component Register base address from struct cxl_port
PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem
dev handler
PCI/AER: Unmask RCEC internal errors to enable RCH downstream port
error handling
cxl/core/regs: Rename phys_addr in cxl_map_component_regs()

Terry Bowman (7):
cxl/pci: Refactor component register discovery for reuse
cxl/pci: Add RCH downstream port AER register discovery
PCI/AER: Refactor cper_print_aer() for use by CXL driver module
cxl/pci: Update CXL error logging to use RAS register address
cxl/pci: Map RCH downstream AER registers for logging protocol errors
cxl/pci: Add RCH downstream port error logging
cxl/pci: Disable root port interrupts in RCH mode

base-commit: a70fc4ed20a6118837b0aecbbf789074935f473b

drivers/cxl/acpi.c | 206 +++++++++++++++++++---------------
drivers/cxl/core/core.h | 17 +++
drivers/cxl/core/hdm.c | 59 +++++-----
drivers/cxl/core/pci.c | 178 ++++++++++++++++++++++++++---
drivers/cxl/core/port.c | 195 ++++++++++++++++++++++++--------
drivers/cxl/core/region.c | 52 ++++-----
drivers/cxl/core/regs.c | 145 +++++++++++++++++++++---
drivers/cxl/cxl.h | 70 +++++++-----
drivers/cxl/cxlmem.h | 9 +-
drivers/cxl/mem.c | 18 +--
drivers/cxl/pci.c | 125 ++++++++-------------
drivers/cxl/port.c | 7 +-
drivers/pci/pcie/Kconfig | 12 ++
drivers/pci/pcie/aer.c | 162 +++++++++++++++++++++++++-
include/linux/aer.h | 2 +-
tools/testing/cxl/Kbuild | 3 +-
tools/testing/cxl/test/cxl.c | 30 ++---
tools/testing/cxl/test/mem.c | 1 -
tools/testing/cxl/test/mock.c | 46 ++++++--
tools/testing/cxl/test/mock.h | 3 -
20 files changed, 951 insertions(+), 389 deletions(-)

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2.34.1