RE: [PATCH v7 16/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state

Dan Williams
2023-06-25T17:38:41Z

Terry Bowman wrote:
> From: Robert Richter <rrichter@amd.com>
>
> Same as for ports and dports, also store the endpoint's Component
> Register mappings, use struct cxl_dev_state for that.
>
> The Component Register base address @component_reg_phys is no longer
> used after the rework of the Component Register setup which now uses
> struct member @comp_map instead. Remove the base address.
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Starting with this patch my QEMU cxl configuration fails to probe the
device:

# cxl list -Miu
{
"memdev":"mem0",
"pmem_size":"512.00 MiB (536.87 MB)",
"serial":"0",
"host":"0000:35:00.0",
"state":"disabled"
}

...the next patch changes where the failure occurs, but it still fails
and applying the rest of the patches does not fix the issue either. I
have not had the time to debug it. Please have a look and make sure that
at every step of this patch set the driver is still operational. I.e.
'git bisect' should never find this conversion in a broken state.

For now I will look at proceeding with patch 1-15.

The cxl bits of my QEMU config are:

-object memory-backend-file,id=cxl-mem1,share=on,mem-path=cxl-window1,size=$cxl_backend_size
-object memory-backend-file,id=cxl-label1,share=on,mem-path=cxl-label1,size=$cxl_label_size
-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52
-device cxl-rp,id=rp0,bus=cxl.0,addr=0.0,chassis=0,slot=0,port=0
-device cxl-type3,bus=rp0,memdev=cxl-mem1,id=cxl-pmem0,lsa=cxl-label1
-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G