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From: Terry Bowman <terry.bowman@amd.com>
To: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
	<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
	<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
	<Jonathan.Cameron@huawei.com>, <linux-cxl@vger.kernel.org>
Cc: <terry.bowman@amd.com>, <rrichter@amd.com>,
	<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: [PATCH v7 04/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev
Date: Thu, 22 Jun 2023 15:55:00 -0500	[thread overview]
Message-ID: <20230622205523.85375-5-terry.bowman@amd.com> (raw)
In-Reply-To: <20230622205523.85375-1-terry.bowman@amd.com>

From: Robert Richter <rrichter@amd.com>

Reading code like dport->dport does not immediately suggest that this
points to the corresponding device structure of the dport. Rename
struct member @dport to @dport_dev.

While at it, also rename @new argument of add_dport() to @dport. This
better describes the variable as a dport (e.g. new->dport becomes to
dport->dport_dev).

Co-developed-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/cxl/core/port.c   | 20 ++++++++++----------
 drivers/cxl/core/region.c |  4 ++--
 drivers/cxl/cxl.h         |  4 ++--
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 76888c75dae4..7d3079f5b7b5 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -605,7 +605,7 @@ static int devm_cxl_link_parent_dport(struct device *host,
 	if (!parent_dport)
 		return 0;
 
-	rc = sysfs_create_link(&port->dev.kobj, &parent_dport->dport->kobj,
+	rc = sysfs_create_link(&port->dev.kobj, &parent_dport->dport_dev->kobj,
 			       "parent_dport");
 	if (rc)
 		return rc;
@@ -658,7 +658,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport,
 		if (iter->host_bridge)
 			port->host_bridge = iter->host_bridge;
 		else if (parent_dport->rch)
-			port->host_bridge = parent_dport->dport;
+			port->host_bridge = parent_dport->dport_dev;
 		else
 			port->host_bridge = iter->uport;
 		dev_dbg(uport, "host-bridge: %s\n", dev_name(port->host_bridge));
@@ -847,22 +847,22 @@ static struct cxl_dport *find_dport(struct cxl_port *port, int id)
 	return NULL;
 }
 
-static int add_dport(struct cxl_port *port, struct cxl_dport *new)
+static int add_dport(struct cxl_port *port, struct cxl_dport *dport)
 {
 	struct cxl_dport *dup;
 	int rc;
 
 	device_lock_assert(&port->dev);
-	dup = find_dport(port, new->port_id);
+	dup = find_dport(port, dport->port_id);
 	if (dup) {
 		dev_err(&port->dev,
 			"unable to add dport%d-%s non-unique port id (%s)\n",
-			new->port_id, dev_name(new->dport),
-			dev_name(dup->dport));
+			dport->port_id, dev_name(dport->dport_dev),
+			dev_name(dup->dport_dev));
 		return -EBUSY;
 	}
 
-	rc = xa_insert(&port->dports, (unsigned long)new->dport, new,
+	rc = xa_insert(&port->dports, (unsigned long)dport->dport_dev, dport,
 		       GFP_KERNEL);
 	if (rc)
 		return rc;
@@ -895,8 +895,8 @@ static void cxl_dport_remove(void *data)
 	struct cxl_dport *dport = data;
 	struct cxl_port *port = dport->port;
 
-	xa_erase(&port->dports, (unsigned long) dport->dport);
-	put_device(dport->dport);
+	xa_erase(&port->dports, (unsigned long) dport->dport_dev);
+	put_device(dport->dport_dev);
 }
 
 static void cxl_dport_unlink(void *data)
@@ -954,7 +954,7 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
 		dev_dbg(dport_dev, "Component Registers found for dport: %pa\n",
 			&component_reg_phys);
 
-	dport->dport = dport_dev;
+	dport->dport_dev = dport_dev;
 	dport->port_id = port_id;
 	dport->component_reg_phys = component_reg_phys;
 	dport->port = port;
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index f822de44bee0..13cda989d944 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -1162,7 +1162,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
 			dev_dbg(&cxlr->dev, "%s:%s: %s expected %s at %d\n",
 				dev_name(port->uport), dev_name(&port->dev),
 				dev_name(&cxlsd->cxld.dev),
-				dev_name(ep->dport->dport),
+				dev_name(ep->dport->dport_dev),
 				cxl_rr->nr_targets_set);
 			return -ENXIO;
 		}
@@ -1173,7 +1173,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
 	cxl_rr->nr_targets_set += inc;
 	dev_dbg(&cxlr->dev, "%s:%s target[%d] = %s for %s:%s @ %d\n",
 		dev_name(port->uport), dev_name(&port->dev),
-		cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dport),
+		cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dport_dev),
 		dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos);
 
 	return 0;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 7c8674079f1a..7232c2a0e27c 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -589,7 +589,7 @@ struct cxl_rcrb_info {
 
 /**
  * struct cxl_dport - CXL downstream port
- * @dport: PCI bridge or firmware device representing the downstream link
+ * @dport_dev: PCI bridge or firmware device representing the downstream link
  * @port_id: unique hardware identifier for dport in decoder target list
  * @component_reg_phys: downstream port component registers
  * @rcrb: Data about the Root Complex Register Block layout
@@ -597,7 +597,7 @@ struct cxl_rcrb_info {
  * @port: reference to cxl_port that contains this downstream port
  */
 struct cxl_dport {
-	struct device *dport;
+	struct device *dport_dev;
 	int port_id;
 	resource_size_t component_reg_phys;
 	struct cxl_rcrb_info rcrb;
-- 
2.34.1


  parent reply	other threads:[~2023-06-22 20:56 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-22 20:54 [PATCH v7 00/27] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-22 20:54 ` [PATCH v7 01/27] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-25 19:34   ` Dan Williams
2023-06-22 20:54 ` [PATCH v7 02/27] cxl: Updates for CXL Test to work with RCH Terry Bowman
2023-06-22 20:54 ` [PATCH v7 03/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-22 20:55 ` Terry Bowman [this message]
2023-06-22 20:55 ` [PATCH v7 05/27] cxl: Rename 'uport' to 'uport_dev' Terry Bowman
2023-06-22 20:55 ` [PATCH v7 06/27] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-22 20:55 ` [PATCH v7 07/27] cxl/pci: Refactor component register discovery for reuse Terry Bowman
2023-06-22 20:55 ` [PATCH v7 08/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs() Terry Bowman
2023-06-22 20:55 ` [PATCH v7 09/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-22 20:55 ` [PATCH v7 10/27] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-22 20:55 ` [PATCH v7 11/27] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-22 20:55 ` [PATCH v7 12/27] cxl/mem: Prepare for early RCH dport component register setup Terry Bowman
2023-06-22 20:55 ` [PATCH v7 13/27] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-22 20:55 ` [PATCH v7 14/27] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-23 13:32   ` Jonathan Cameron
2023-06-22 20:55 ` [PATCH v7 15/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-22 20:55 ` [PATCH v7 16/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-25 17:38   ` Dan Williams
2023-06-26 14:16     ` Terry Bowman
2023-06-30 19:51     ` Robert Richter
2023-06-30 19:56     ` Robert Richter
2023-07-03  3:55       ` Jonathan Cameron
2023-06-22 20:55 ` [PATCH v7 17/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-06-22 20:55 ` [PATCH v7 18/27] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-22 20:55 ` [PATCH v7 19/27] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-22 20:55 ` [PATCH v7 20/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-23 21:22   ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 21/27] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-23 21:43   ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 22/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-23 21:58   ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 23/27] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-23 22:07   ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 24/27] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-23 22:08   ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 25/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-23 22:16   ` Dave Jiang
2023-06-25  5:47     ` Dan Williams
2023-06-22 20:55 ` [PATCH v7 26/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-23 22:18   ` Dave Jiang
2023-06-22 20:55 ` [PATCH v7 27/27] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-06-23 13:30   ` Jonathan Cameron
2023-06-23 22:19   ` Dave Jiang

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