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From: Lukas Wunner <lukas@wunner.de>
To: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	Bjorn Helgaas <bhelgaas@google.com>,
	oohall@gmail.com, Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
	Kuppuswamy Sathyanarayanan 
	<sathyanarayanan.kuppuswamy@linux.intel.com>,
	Yazen Ghannam <yazen.ghannam@amd.com>,
	Fontenot Nathan <Nathan.Fontenot@amd.com>,
	Jay Cornwall <Jay.Cornwall@amd.com>,
	Felix Kuehling <Felix.Kuehling@amd.com>
Subject: Re: [PATCH v3 2/2] PCI: pciehp: Clear the optional capabilities in DEVCTL2 on a hot-plug
Date: Wed, 28 Jun 2023 15:25:26 +0200	[thread overview]
Message-ID: <20230628132526.GA14276@wunner.de> (raw)
In-Reply-To: <4599d885-219f-3ee0-f425-62746f31cc67@amd.com>

On Tue, Jun 27, 2023 at 10:38:54AM -0700, Smita Koralahalli wrote:
> Okay, I see there are no objections except for Bjorn/Jay's comments on
> 
> "But there could be devices where AtomicOps are nominally supported but
> untested or broken.."
> 
> Would this be an issue?

I think you said that BIOS enables AtomicOps on certain AMD machines?
Or did that observation only apply to 10 Bit tags?

If BIOS does enable AtomicOps, it would be interesting to know which
logic BIOS follows, i.e. how does it determine whether to set
AtomicOp Requester Enable on Endpoints?

It would also be interesting to know how far that BIOS has proliferated,
i.e. how much experience with various Endpoint devices exists in the
real world.  If it turns out that BIOS has enabled the feature for
years on a wide range of Endpoints without any issues, I think
that would render concerns mute that enabling it in the kernel
might cause regressions.

I don't know why the spec says that "discovery of AtomicOp Requester
capabilities is outside the scope of this specification".  I imagine
it would be possible to set AtomicOp Requester Enable, then read it
to determine whether the bit is now indeed 1 or hard-wired to 0.
In the latter case, AtomicOp Requester capabilities can be assumed
to be absent.  So that would be a way to make do without any other
specific discovery of AtomicOp Requester capabilities.

Thanks,

Lukas

  reply	other threads:[~2023-06-28 13:28 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-21 18:51 [PATCH v3 0/2] PCI: pciehp: Add support for native AER and DPC handling on async remove Smita Koralahalli
2023-06-21 18:51 ` [PATCH v3 1/2] PCI: pciehp: Add support for async hotplug with native AER and DPC/EDR Smita Koralahalli
2023-06-22  9:04   ` Lukas Wunner
2023-06-22 21:02     ` Smita Koralahalli
2023-06-22 21:22       ` Lukas Wunner
2023-06-22 23:22   ` Sathyanarayanan Kuppuswamy
2023-06-27 17:48     ` Smita Koralahalli
2023-06-28 13:29       ` Lukas Wunner
2023-06-21 18:51 ` [PATCH v3 2/2] PCI: pciehp: Clear the optional capabilities in DEVCTL2 on a hot-plug Smita Koralahalli
2023-06-22  6:31   ` Lukas Wunner
2023-06-22 10:04     ` Lukas Wunner
2023-06-22 21:02     ` Smita Koralahalli
2023-06-22 21:42       ` Lukas Wunner
2023-06-23  3:59         ` Felix Kuehling
2023-06-23  6:06           ` Lukas Wunner
2023-06-23 13:12         ` Jay Cornwall
2023-06-27 17:38         ` Smita Koralahalli
2023-06-28 13:25           ` Lukas Wunner [this message]
2023-07-01  6:29             ` Smita Koralahalli
2023-08-15 21:22             ` Smita Koralahalli

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