From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
<linux-cxl@vger.kernel.org>, <rrichter@amd.com>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: Re: [PATCH v8 01/14] cxl/port: Pre-initialize component register mappings
Date: Mon, 3 Jul 2023 19:29:36 +0800 [thread overview]
Message-ID: <20230703192936.00003dbd@Huawei.com> (raw)
In-Reply-To: <20230630231635.3132638-2-terry.bowman@amd.com>
On Fri, 30 Jun 2023 18:16:22 -0500
Terry Bowman <terry.bowman@amd.com> wrote:
> From: Robert Richter <rrichter@amd.com>
>
> The component registers of a component may not exist or are not
> needed. The setup may fail for that reason. In some cases the
> initialization should continue anyway. Thus, always initialize struct
> cxl_register_map with valid values. In case of errors, zero it, set a
> value for @dev and make @resource a the valid value using
> CXL_RESOURCE_NONE.
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Seems reasonable to me.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/port.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 724be8448eb4..2d22e7a5629b 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -693,16 +693,17 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
> static int cxl_setup_comp_regs(struct device *dev, struct cxl_register_map *map,
> resource_size_t component_reg_phys)
> {
> - if (component_reg_phys == CXL_RESOURCE_NONE)
> - return 0;
> -
> *map = (struct cxl_register_map) {
> .dev = dev,
> - .reg_type = CXL_REGLOC_RBI_COMPONENT,
> .resource = component_reg_phys,
> - .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> };
>
> + if (component_reg_phys == CXL_RESOURCE_NONE)
> + return 0;
> +
> + map->reg_type = CXL_REGLOC_RBI_COMPONENT;
> + map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
> +
> return cxl_setup_regs(map);
> }
>
next prev parent reply other threads:[~2023-07-03 11:29 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-30 23:16 ` [PATCH v8 01/14] cxl/port: Pre-initialize component register mappings Terry Bowman
2023-07-03 11:29 ` Jonathan Cameron [this message]
2023-06-30 23:16 ` [PATCH v8 02/14] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-30 23:16 ` [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-07-04 0:39 ` Dan Williams
2023-07-14 17:46 ` Robert Richter
2023-08-08 3:00 ` Dan Williams
2023-08-25 14:32 ` Robert Richter
2023-06-30 23:16 ` [PATCH v8 04/14] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-06-30 23:16 ` [PATCH v8 05/14] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-30 23:16 ` [PATCH v8 06/14] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-30 23:16 ` [PATCH v8 07/14] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-30 23:16 ` [PATCH v8 08/14] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-30 23:16 ` [PATCH v8 09/14] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-30 23:16 ` [PATCH v8 10/14] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-30 23:16 ` [PATCH v8 11/14] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-30 23:16 ` [PATCH v8 12/14] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-30 23:16 ` [PATCH v8 13/14] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-30 23:16 ` [PATCH v8 14/14] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-07-01 0:20 ` [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Dan Williams
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