* [PATCH v8 01/14] cxl/port: Pre-initialize component register mappings
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-07-03 11:29 ` Jonathan Cameron
2023-06-30 23:16 ` [PATCH v8 02/14] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
` (13 subsequent siblings)
14 siblings, 1 reply; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
From: Robert Richter <rrichter@amd.com>
The component registers of a component may not exist or are not
needed. The setup may fail for that reason. In some cases the
initialization should continue anyway. Thus, always initialize struct
cxl_register_map with valid values. In case of errors, zero it, set a
value for @dev and make @resource a the valid value using
CXL_RESOURCE_NONE.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
drivers/cxl/core/port.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 724be8448eb4..2d22e7a5629b 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -693,16 +693,17 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
static int cxl_setup_comp_regs(struct device *dev, struct cxl_register_map *map,
resource_size_t component_reg_phys)
{
- if (component_reg_phys == CXL_RESOURCE_NONE)
- return 0;
-
*map = (struct cxl_register_map) {
.dev = dev,
- .reg_type = CXL_REGLOC_RBI_COMPONENT,
.resource = component_reg_phys,
- .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
};
+ if (component_reg_phys == CXL_RESOURCE_NONE)
+ return 0;
+
+ map->reg_type = CXL_REGLOC_RBI_COMPONENT;
+ map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
+
return cxl_setup_regs(map);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v8 01/14] cxl/port: Pre-initialize component register mappings
2023-06-30 23:16 ` [PATCH v8 01/14] cxl/port: Pre-initialize component register mappings Terry Bowman
@ 2023-07-03 11:29 ` Jonathan Cameron
0 siblings, 0 replies; 21+ messages in thread
From: Jonathan Cameron @ 2023-07-03 11:29 UTC (permalink / raw)
To: Terry Bowman
Cc: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, linux-cxl, rrichter, linux-kernel,
bhelgaas
On Fri, 30 Jun 2023 18:16:22 -0500
Terry Bowman <terry.bowman@amd.com> wrote:
> From: Robert Richter <rrichter@amd.com>
>
> The component registers of a component may not exist or are not
> needed. The setup may fail for that reason. In some cases the
> initialization should continue anyway. Thus, always initialize struct
> cxl_register_map with valid values. In case of errors, zero it, set a
> value for @dev and make @resource a the valid value using
> CXL_RESOURCE_NONE.
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Seems reasonable to me.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/port.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 724be8448eb4..2d22e7a5629b 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -693,16 +693,17 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
> static int cxl_setup_comp_regs(struct device *dev, struct cxl_register_map *map,
> resource_size_t component_reg_phys)
> {
> - if (component_reg_phys == CXL_RESOURCE_NONE)
> - return 0;
> -
> *map = (struct cxl_register_map) {
> .dev = dev,
> - .reg_type = CXL_REGLOC_RBI_COMPONENT,
> .resource = component_reg_phys,
> - .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> };
>
> + if (component_reg_phys == CXL_RESOURCE_NONE)
> + return 0;
> +
> + map->reg_type = CXL_REGLOC_RBI_COMPONENT;
> + map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
> +
> return cxl_setup_regs(map);
> }
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v8 02/14] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-30 23:16 ` [PATCH v8 01/14] cxl/port: Pre-initialize component register mappings Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-06-30 23:16 ` [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
` (12 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
From: Robert Richter <rrichter@amd.com>
Same as for ports and dports, also store the endpoint's Component
Register mappings, use struct cxl_dev_state for that.
Keep the Component Register base address @component_reg_phys a bit to
not break functionality. It will be removed after the transition in a
later patch.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/cxlmem.h | 2 ++
drivers/cxl/pci.c | 9 +++++----
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 79e99c873ca2..607ee34b0ce7 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -382,6 +382,7 @@ enum cxl_devtype {
*
* @dev: The device associated with this CXL state
* @cxlmd: The device representing the CXL.mem capabilities of @dev
+ * @comp_map: component register capability mappings
* @regs: Parsed register blocks
* @cxl_dvsec: Offset to the PCIe device DVSEC
* @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
@@ -396,6 +397,7 @@ enum cxl_devtype {
struct cxl_dev_state {
struct device *dev;
struct cxl_memdev *cxlmd;
+ struct cxl_register_map comp_map;
struct cxl_regs regs;
int cxl_dvsec;
bool rcd;
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 48f88d96029d..054cfa2f6a2d 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -836,15 +836,16 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
* still be useful for management functions so don't return an error.
*/
cxlds->component_reg_phys = CXL_RESOURCE_NONE;
- rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
+ rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,
+ &cxlds->comp_map);
if (rc)
dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
- else if (!map.component_map.ras.valid)
+ else if (!cxlds->comp_map.component_map.ras.valid)
dev_dbg(&pdev->dev, "RAS registers not found\n");
- cxlds->component_reg_phys = map.resource;
+ cxlds->component_reg_phys = cxlds->comp_map.resource;
- rc = cxl_map_component_regs(&map, &cxlds->regs.component,
+ rc = cxl_map_component_regs(&cxlds->comp_map, &cxlds->regs.component,
BIT(CXL_CM_CAP_CAP_ID_RAS));
if (rc)
dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-30 23:16 ` [PATCH v8 01/14] cxl/port: Pre-initialize component register mappings Terry Bowman
2023-06-30 23:16 ` [PATCH v8 02/14] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-07-04 0:39 ` Dan Williams
2023-06-30 23:16 ` [PATCH v8 04/14] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
` (11 subsequent siblings)
14 siblings, 1 reply; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
From: Robert Richter <rrichter@amd.com>
Now, that the Component Register mappings are stored, use them to
enable and map the HDM decoder capabilities. The Component Registers
do not need to be probed again for this, remove probing code.
The HDM capability applies to Endpoints, USPs and VH Host Bridges. The
Endpoint's component register mappings are located in the cxlds and
else in the port's structure. Provide a helper function
cxl_port_get_comp_map() to locate the mappings depending on the
component's type.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/hdm.c | 64 +++++++++++++++++++++++-------------------
1 file changed, 35 insertions(+), 29 deletions(-)
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 4449b34a80cc..b0f59e63e0d2 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -81,26 +81,6 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
cxlhdm->interleave_mask |= GENMASK(14, 12);
}
-static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
- struct cxl_component_regs *regs)
-{
- struct cxl_register_map map = {
- .dev = &port->dev,
- .resource = port->component_reg_phys,
- .base = crb,
- .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
- };
-
- cxl_probe_component_regs(&port->dev, crb, &map.component_map);
- if (!map.component_map.hdm_decoder.valid) {
- dev_dbg(&port->dev, "HDM decoder registers not implemented\n");
- /* unique error code to indicate no HDM decoder capability */
- return -ENODEV;
- }
-
- return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));
-}
-
static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
{
struct cxl_hdm *cxlhdm;
@@ -145,6 +125,22 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
return true;
}
+static struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port)
+{
+ /*
+ * HDM capability applies to Endpoints, USPs and VH Host
+ * Bridges. The Endpoint's component register mappings are
+ * located in the cxlds.
+ */
+ if (is_cxl_endpoint(port)) {
+ struct cxl_memdev *memdev = to_cxl_memdev(port->uport_dev);
+
+ return &memdev->cxlds->comp_map;
+ }
+
+ return &port->comp_map;
+}
+
/**
* devm_cxl_setup_hdm - map HDM decoder component registers
* @port: cxl_port to map
@@ -155,7 +151,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
{
struct device *dev = &port->dev;
struct cxl_hdm *cxlhdm;
- void __iomem *crb;
+ struct cxl_register_map *comp_map;
int rc;
cxlhdm = devm_kzalloc(dev, sizeof(*cxlhdm), GFP_KERNEL);
@@ -164,19 +160,29 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
cxlhdm->port = port;
dev_set_drvdata(dev, cxlhdm);
- crb = ioremap(port->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);
- if (!crb && info && info->mem_enabled) {
- cxlhdm->decoder_count = info->ranges;
- return cxlhdm;
- } else if (!crb) {
+ comp_map = cxl_port_get_comp_map(port);
+
+ if (comp_map->resource == CXL_RESOURCE_NONE) {
+ if (info && info->mem_enabled) {
+ cxlhdm->decoder_count = info->ranges;
+ return cxlhdm;
+ }
dev_err(dev, "No component registers mapped\n");
return ERR_PTR(-ENXIO);
}
- rc = map_hdm_decoder_regs(port, crb, &cxlhdm->regs);
- iounmap(crb);
- if (rc)
+ if (!comp_map->component_map.hdm_decoder.valid) {
+ dev_dbg(&port->dev, "HDM decoder registers not implemented\n");
+ /* unique error code to indicate no HDM decoder capability */
+ return ERR_PTR(-ENODEV);
+ }
+
+ rc = cxl_map_component_regs(comp_map, &cxlhdm->regs,
+ BIT(CXL_CM_CAP_CAP_ID_HDM));
+ if (rc) {
+ dev_dbg(dev, "Failed to map HDM capability.\n");
return ERR_PTR(rc);
+ }
parse_hdm_decoder_caps(cxlhdm);
if (cxlhdm->decoder_count == 0) {
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* RE: [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
2023-06-30 23:16 ` [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
@ 2023-07-04 0:39 ` Dan Williams
2023-07-14 17:46 ` Robert Richter
0 siblings, 1 reply; 21+ messages in thread
From: Dan Williams @ 2023-07-04 0:39 UTC (permalink / raw)
To: Terry Bowman, alison.schofield, vishal.l.verma, ira.weiny,
bwidawsk, dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
Terry Bowman wrote:
> From: Robert Richter <rrichter@amd.com>
>
> Now, that the Component Register mappings are stored, use them to
> enable and map the HDM decoder capabilities. The Component Registers
> do not need to be probed again for this, remove probing code.
>
> The HDM capability applies to Endpoints, USPs and VH Host Bridges. The
> Endpoint's component register mappings are located in the cxlds and
> else in the port's structure. Provide a helper function
> cxl_port_get_comp_map() to locate the mappings depending on the
> component's type.
This causes a regression that cxl_test tripped over. It's likely
something you could reproduce without cxl_test just be reloading the
cxl_port driver. Root cause below, but here is what I see on a test run:
# meson test -C build --suite cxl
ninja: no work to do.
ninja: Entering directory `/root/git/ndctl/build'
[113/113] Linking target ndctl/ndctl
1/6 ndctl:cxl / cxl-topology.sh OK 12.78s
2/6 ndctl:cxl / cxl-region-sysfs.sh OK 7.72s
3/6 ndctl:cxl / cxl-labels.sh FAIL 1.53s (exit status 129 or signal 1 SIGHUP)
>>> LD_LIBRARY_PATH=/root/git/ndctl/build/cxl/lib:/root/git/ndctl/build/ndctl/lib:/root/git/ndctl/build/daxctl/lib NDCTL=/root/git/ndctl/build/ndctl/ndctl DAXCTL=/root/git/ndctl/build/daxctl/daxctl MALLOC_PERTURB_=67 TEST_PATH=/root/git/ndctl/build/test DATA_PATH=/root/git/ndctl/test /bin/bash /root/git/ndctl/test/cxl-labels.sh
4/6 ndctl:cxl / cxl-create-region.sh OK 17.05s
5/6 ndctl:cxl / cxl-xor-region.sh OK 5.18s
6/6 ndctl:cxl / cxl-security.sh OK 4.68s
Ok: 5
Expected Fail: 0
Fail: 1
Unexpected Pass: 0
Skipped: 0
Timeout: 0
Full log written to /root/git/ndctl/build/meson-logs/testlog.txt
It's not that cxl-labels.sh causes the error, it is loading and
unloading the port driver trips over the problem below:
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/core/hdm.c | 64 +++++++++++++++++++++++-------------------
> 1 file changed, 35 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 4449b34a80cc..b0f59e63e0d2 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -81,26 +81,6 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
> cxlhdm->interleave_mask |= GENMASK(14, 12);
> }
>
> -static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
> - struct cxl_component_regs *regs)
> -{
> - struct cxl_register_map map = {
> - .dev = &port->dev,
> - .resource = port->component_reg_phys,
> - .base = crb,
> - .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> - };
> -
> - cxl_probe_component_regs(&port->dev, crb, &map.component_map);
> - if (!map.component_map.hdm_decoder.valid) {
> - dev_dbg(&port->dev, "HDM decoder registers not implemented\n");
> - /* unique error code to indicate no HDM decoder capability */
> - return -ENODEV;
> - }
> -
> - return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));
> -}
> -
> static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> {
> struct cxl_hdm *cxlhdm;
> @@ -145,6 +125,22 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> return true;
> }
>
> +static struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port)
> +{
> + /*
> + * HDM capability applies to Endpoints, USPs and VH Host
> + * Bridges. The Endpoint's component register mappings are
> + * located in the cxlds.
> + */
> + if (is_cxl_endpoint(port)) {
> + struct cxl_memdev *memdev = to_cxl_memdev(port->uport_dev);
> +
> + return &memdev->cxlds->comp_map;
...but why? The issue here is that the @dev argument in that map is the
memdev parent PCI device. However, in this context the @dev for devm
operations wants to be &port->dev.
> + }
> +
> + return &port->comp_map;
...so this is fine, and folding in the following resolves the test
failure.
diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index b0f59e63e0d2..6f111f487795 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -125,22 +125,6 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
return true;
}
-static struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port)
-{
- /*
- * HDM capability applies to Endpoints, USPs and VH Host
- * Bridges. The Endpoint's component register mappings are
- * located in the cxlds.
- */
- if (is_cxl_endpoint(port)) {
- struct cxl_memdev *memdev = to_cxl_memdev(port->uport_dev);
-
- return &memdev->cxlds->comp_map;
- }
-
- return &port->comp_map;
-}
-
/**
* devm_cxl_setup_hdm - map HDM decoder component registers
* @port: cxl_port to map
@@ -160,8 +144,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
cxlhdm->port = port;
dev_set_drvdata(dev, cxlhdm);
- comp_map = cxl_port_get_comp_map(port);
-
+ comp_map = &port->comp_map;
if (comp_map->resource == CXL_RESOURCE_NONE) {
if (info && info->mem_enabled) {
cxlhdm->decoder_count = info->ranges;
Am I missing why the cxlds->comp_map needs to be reused?
Note that I am out and may not be able to respond further until next
week.
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
2023-07-04 0:39 ` Dan Williams
@ 2023-07-14 17:46 ` Robert Richter
2023-08-08 3:00 ` Dan Williams
0 siblings, 1 reply; 21+ messages in thread
From: Robert Richter @ 2023-07-14 17:46 UTC (permalink / raw)
To: Dan Williams
Cc: Terry Bowman, alison.schofield, vishal.l.verma, ira.weiny,
bwidawsk, dave.jiang, Jonathan.Cameron, linux-cxl, linux-kernel,
bhelgaas
Dan,
On 03.07.23 17:39:38, Dan Williams wrote:
> Terry Bowman wrote:
> > From: Robert Richter <rrichter@amd.com>
> >
> > Now, that the Component Register mappings are stored, use them to
> > enable and map the HDM decoder capabilities. The Component Registers
> > do not need to be probed again for this, remove probing code.
> >
> > The HDM capability applies to Endpoints, USPs and VH Host Bridges. The
> > Endpoint's component register mappings are located in the cxlds and
> > else in the port's structure. Provide a helper function
> > cxl_port_get_comp_map() to locate the mappings depending on the
> > component's type.
>
> This causes a regression that cxl_test tripped over. It's likely
> something you could reproduce without cxl_test just be reloading the
> cxl_port driver. Root cause below, but here is what I see on a test run:
>
> # meson test -C build --suite cxl
> ninja: no work to do.
> ninja: Entering directory `/root/git/ndctl/build'
> [113/113] Linking target ndctl/ndctl
> 1/6 ndctl:cxl / cxl-topology.sh OK 12.78s
> 2/6 ndctl:cxl / cxl-region-sysfs.sh OK 7.72s
> 3/6 ndctl:cxl / cxl-labels.sh FAIL 1.53s (exit status 129 or signal 1 SIGHUP)
> >>> LD_LIBRARY_PATH=/root/git/ndctl/build/cxl/lib:/root/git/ndctl/build/ndctl/lib:/root/git/ndctl/build/daxctl/lib NDCTL=/root/git/ndctl/build/ndctl/ndctl DAXCTL=/root/git/ndctl/build/daxctl/daxctl MALLOC_PERTURB_=67 TEST_PATH=/root/git/ndctl/build/test DATA_PATH=/root/git/ndctl/test /bin/bash /root/git/ndctl/test/cxl-labels.sh
I have tried various combinations of revisions and setups (patch #3,
#5 and #14, ndctl:pending/v77, cxl_test only with both, "ACPI0017" and
cxl_pci_probe() disabled), but could not reproduce this. Tests always
pass for me:
[51/51] Linking target ndctl/ndctl
1/6 ndctl:cxl / cxl-topology.sh OK 18.59s
2/6 ndctl:cxl / cxl-region-sysfs.sh OK 12.26s
3/6 ndctl:cxl / cxl-labels.sh OK 28.25s
4/6 ndctl:cxl / cxl-create-region.sh OK 19.56s
5/6 ndctl:cxl / cxl-xor-region.sh OK 10.57s
6/6 ndctl:cxl / cxl-security.sh OK 9.77s
Ok: 6
Expected Fail: 0
Fail: 0
Unexpected Pass: 0
Skipped: 0
Timeout: 0
Full log written to /root/ndctl/build/meson-logs/testlog.txt
>
> 4/6 ndctl:cxl / cxl-create-region.sh OK 17.05s
> 5/6 ndctl:cxl / cxl-xor-region.sh OK 5.18s
> 6/6 ndctl:cxl / cxl-security.sh OK 4.68s
>
> Ok: 5
> Expected Fail: 0
> Fail: 1
> Unexpected Pass: 0
> Skipped: 0
> Timeout: 0
>
> Full log written to /root/git/ndctl/build/meson-logs/testlog.txt
>
> It's not that cxl-labels.sh causes the error, it is loading and
> unloading the port driver trips over the problem below:
>
> >
> > Signed-off-by: Robert Richter <rrichter@amd.com>
> > Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> > ---
> > drivers/cxl/core/hdm.c | 64 +++++++++++++++++++++++-------------------
> > 1 file changed, 35 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> > index 4449b34a80cc..b0f59e63e0d2 100644
> > --- a/drivers/cxl/core/hdm.c
> > +++ b/drivers/cxl/core/hdm.c
> > @@ -81,26 +81,6 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
> > cxlhdm->interleave_mask |= GENMASK(14, 12);
> > }
> >
> > -static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
> > - struct cxl_component_regs *regs)
> > -{
> > - struct cxl_register_map map = {
> > - .dev = &port->dev,
> > - .resource = port->component_reg_phys,
> > - .base = crb,
> > - .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> > - };
> > -
> > - cxl_probe_component_regs(&port->dev, crb, &map.component_map);
> > - if (!map.component_map.hdm_decoder.valid) {
> > - dev_dbg(&port->dev, "HDM decoder registers not implemented\n");
> > - /* unique error code to indicate no HDM decoder capability */
> > - return -ENODEV;
> > - }
> > -
> > - return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));
> > -}
> > -
> > static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> > {
> > struct cxl_hdm *cxlhdm;
> > @@ -145,6 +125,22 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> > return true;
> > }
> >
> > +static struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port)
> > +{
> > + /*
> > + * HDM capability applies to Endpoints, USPs and VH Host
> > + * Bridges. The Endpoint's component register mappings are
> > + * located in the cxlds.
> > + */
> > + if (is_cxl_endpoint(port)) {
> > + struct cxl_memdev *memdev = to_cxl_memdev(port->uport_dev);
> > +
> > + return &memdev->cxlds->comp_map;
>
> ...but why? The issue here is that the @dev argument in that map is the
> memdev parent PCI device. However, in this context the @dev for devm
> operations wants to be &port->dev.
The cxl_pci driver stores the comp_map of the endpoint in the cxlds
structure, struct cxl_port is not yet available at this point. See
patch #2 of this series ("cxl/pci: Store the endpoint's Component
Register mappings in struct cxl_dev_state").
>
> > + }
> > +
> > + return &port->comp_map;
>
> ...so this is fine, and folding in the following resolves the test
> failure.
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index b0f59e63e0d2..6f111f487795 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -125,22 +125,6 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> return true;
> }
>
> -static struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port)
> -{
> - /*
> - * HDM capability applies to Endpoints, USPs and VH Host
> - * Bridges. The Endpoint's component register mappings are
> - * located in the cxlds.
> - */
> - if (is_cxl_endpoint(port)) {
> - struct cxl_memdev *memdev = to_cxl_memdev(port->uport_dev);
> -
> - return &memdev->cxlds->comp_map;
> - }
> -
> - return &port->comp_map;
> -}
> -
> /**
> * devm_cxl_setup_hdm - map HDM decoder component registers
> * @port: cxl_port to map
> @@ -160,8 +144,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
> cxlhdm->port = port;
> dev_set_drvdata(dev, cxlhdm);
>
> - comp_map = cxl_port_get_comp_map(port);
> -
> + comp_map = &port->comp_map;
Can you check if the following works instead, I think the
pre-initialization is missing in cxl_mock_mem_probe() for
cxl_test:
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index d6d067fbee97..4c4e33de4d74 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -1333,6 +1333,8 @@ struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev)
mutex_init(&mds->mbox_mutex);
mutex_init(&mds->event.log_lock);
mds->cxlds.dev = dev;
+ mds->cxlds.comp_map.dev = dev;
+ mds->cxlds.comp_map.resource = CXL_RESOURCE_NONE;
mds->cxlds.type = CXL_DEVTYPE_CLASSMEM;
return mds;
--
2.30.2
The cxl_pci driver always has something valid or fails otherwise.
If that works the change should be merged into patch #2.
Thanks,
-Robert
> if (comp_map->resource == CXL_RESOURCE_NONE) {
> if (info && info->mem_enabled) {
> cxlhdm->decoder_count = info->ranges;
>
>
> Am I missing why the cxlds->comp_map needs to be reused?
>
> Note that I am out and may not be able to respond further until next
> week.
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
2023-07-14 17:46 ` Robert Richter
@ 2023-08-08 3:00 ` Dan Williams
2023-08-25 14:32 ` Robert Richter
0 siblings, 1 reply; 21+ messages in thread
From: Dan Williams @ 2023-08-08 3:00 UTC (permalink / raw)
To: Robert Richter, Dan Williams
Cc: Terry Bowman, alison.schofield, vishal.l.verma, ira.weiny,
bwidawsk, dave.jiang, Jonathan.Cameron, linux-cxl, linux-kernel,
bhelgaas
Robert Richter wrote:
> Dan,
>
> On 03.07.23 17:39:38, Dan Williams wrote:
> > Terry Bowman wrote:
> > > From: Robert Richter <rrichter@amd.com>
> > >
> > > Now, that the Component Register mappings are stored, use them to
> > > enable and map the HDM decoder capabilities. The Component Registers
> > > do not need to be probed again for this, remove probing code.
> > >
> > > The HDM capability applies to Endpoints, USPs and VH Host Bridges. The
> > > Endpoint's component register mappings are located in the cxlds and
> > > else in the port's structure. Provide a helper function
> > > cxl_port_get_comp_map() to locate the mappings depending on the
> > > component's type.
> >
> > This causes a regression that cxl_test tripped over. It's likely
> > something you could reproduce without cxl_test just be reloading the
> > cxl_port driver. Root cause below, but here is what I see on a test run:
> >
> > # meson test -C build --suite cxl
> > ninja: no work to do.
> > ninja: Entering directory `/root/git/ndctl/build'
> > [113/113] Linking target ndctl/ndctl
> > 1/6 ndctl:cxl / cxl-topology.sh OK 12.78s
> > 2/6 ndctl:cxl / cxl-region-sysfs.sh OK 7.72s
> > 3/6 ndctl:cxl / cxl-labels.sh FAIL 1.53s (exit status 129 or signal 1 SIGHUP)
> > >>> LD_LIBRARY_PATH=/root/git/ndctl/build/cxl/lib:/root/git/ndctl/build/ndctl/lib:/root/git/ndctl/build/daxctl/lib NDCTL=/root/git/ndctl/build/ndctl/ndctl DAXCTL=/root/git/ndctl/build/daxctl/daxctl MALLOC_PERTURB_=67 TEST_PATH=/root/git/ndctl/build/test DATA_PATH=/root/git/ndctl/test /bin/bash /root/git/ndctl/test/cxl-labels.sh
>
> I have tried various combinations of revisions and setups (patch #3,
> #5 and #14, ndctl:pending/v77, cxl_test only with both, "ACPI0017" and
> cxl_pci_probe() disabled), but could not reproduce this. Tests always
> pass for me:
Apologies for the long delay in getting back to this. July had some
major personal interrupts to attend.
>
> [51/51] Linking target ndctl/ndctl
> 1/6 ndctl:cxl / cxl-topology.sh OK 18.59s
> 2/6 ndctl:cxl / cxl-region-sysfs.sh OK 12.26s
> 3/6 ndctl:cxl / cxl-labels.sh OK 28.25s
> 4/6 ndctl:cxl / cxl-create-region.sh OK 19.56s
> 5/6 ndctl:cxl / cxl-xor-region.sh OK 10.57s
> 6/6 ndctl:cxl / cxl-security.sh OK 9.77s
>
> Ok: 6
> Expected Fail: 0
> Fail: 0
> Unexpected Pass: 0
> Skipped: 0
> Timeout: 0
>
> Full log written to /root/ndctl/build/meson-logs/testlog.txt
So it turns out it is not cxl_test that is failing instead it is the
tests noticing a regression of the VH base case. I am running
cxl-topology.sh in a QEMU environment with a local device defined, and
that local device is hitting a probe regression.
When cxl_test goes to count the expected disabled devices it sees one
more because the QEMU device is also disabled.
++ jq 'map(select(.state == "disabled")) | length'
+ count=5
+ (( count == 4 ))
+ err 170
++ basename /root/git/ndctl/test/cxl-topology.sh
+ echo test/cxl-topology.sh: failed at line 170
...i.e. only 4 devices are expected to be disabled, not the 5th one that
was not on the cxl_test bus. I assume you are running without any other
CXL devices?
I will look into making that a more formalized case so that failure is
not QEMU configuration dependent, but please make sure that QEMU CXL
configs do not regress.
> >
> > 4/6 ndctl:cxl / cxl-create-region.sh OK 17.05s
> > 5/6 ndctl:cxl / cxl-xor-region.sh OK 5.18s
> > 6/6 ndctl:cxl / cxl-security.sh OK 4.68s
> >
> > Ok: 5
> > Expected Fail: 0
> > Fail: 1
> > Unexpected Pass: 0
> > Skipped: 0
> > Timeout: 0
> >
> > Full log written to /root/git/ndctl/build/meson-logs/testlog.txt
> >
> > It's not that cxl-labels.sh causes the error, it is loading and
> > unloading the port driver trips over the problem below:
> >
> > >
> > > Signed-off-by: Robert Richter <rrichter@amd.com>
> > > Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> > > ---
> > > drivers/cxl/core/hdm.c | 64 +++++++++++++++++++++++-------------------
> > > 1 file changed, 35 insertions(+), 29 deletions(-)
> > >
> > > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> > > index 4449b34a80cc..b0f59e63e0d2 100644
> > > --- a/drivers/cxl/core/hdm.c
> > > +++ b/drivers/cxl/core/hdm.c
> > > @@ -81,26 +81,6 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
> > > cxlhdm->interleave_mask |= GENMASK(14, 12);
> > > }
> > >
> > > -static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
> > > - struct cxl_component_regs *regs)
> > > -{
> > > - struct cxl_register_map map = {
> > > - .dev = &port->dev,
> > > - .resource = port->component_reg_phys,
> > > - .base = crb,
> > > - .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> > > - };
> > > -
> > > - cxl_probe_component_regs(&port->dev, crb, &map.component_map);
> > > - if (!map.component_map.hdm_decoder.valid) {
> > > - dev_dbg(&port->dev, "HDM decoder registers not implemented\n");
> > > - /* unique error code to indicate no HDM decoder capability */
> > > - return -ENODEV;
> > > - }
> > > -
> > > - return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));
> > > -}
> > > -
> > > static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> > > {
> > > struct cxl_hdm *cxlhdm;
> > > @@ -145,6 +125,22 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> > > return true;
> > > }
> > >
> > > +static struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port)
> > > +{
> > > + /*
> > > + * HDM capability applies to Endpoints, USPs and VH Host
> > > + * Bridges. The Endpoint's component register mappings are
> > > + * located in the cxlds.
> > > + */
> > > + if (is_cxl_endpoint(port)) {
> > > + struct cxl_memdev *memdev = to_cxl_memdev(port->uport_dev);
> > > +
> > > + return &memdev->cxlds->comp_map;
> >
> > ...but why? The issue here is that the @dev argument in that map is the
> > memdev parent PCI device. However, in this context the @dev for devm
> > operations wants to be &port->dev.
>
> The cxl_pci driver stores the comp_map of the endpoint in the cxlds
> structure, struct cxl_port is not yet available at this point.
When you say "this point" you mean "that point" in cxl_pci, right? I
initially took that to mean literally "this" point in the quoted code
above.
> See patch #2 of this series ("cxl/pci: Store the endpoint's Component
> Register mappings in struct cxl_dev_state").
>
> >
> > > + }
> > > +
> > > + return &port->comp_map;
> >
> > ...so this is fine, and folding in the following resolves the test
> > failure.
> >
> > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> > index b0f59e63e0d2..6f111f487795 100644
> > --- a/drivers/cxl/core/hdm.c
> > +++ b/drivers/cxl/core/hdm.c
> > @@ -125,22 +125,6 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> > return true;
> > }
> >
> > -static struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port)
> > -{
> > - /*
> > - * HDM capability applies to Endpoints, USPs and VH Host
> > - * Bridges. The Endpoint's component register mappings are
> > - * located in the cxlds.
> > - */
> > - if (is_cxl_endpoint(port)) {
> > - struct cxl_memdev *memdev = to_cxl_memdev(port->uport_dev);
> > -
> > - return &memdev->cxlds->comp_map;
> > - }
> > -
> > - return &port->comp_map;
> > -}
> > -
> > /**
> > * devm_cxl_setup_hdm - map HDM decoder component registers
> > * @port: cxl_port to map
> > @@ -160,8 +144,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
> > cxlhdm->port = port;
> > dev_set_drvdata(dev, cxlhdm);
> >
> > - comp_map = cxl_port_get_comp_map(port);
> > -
> > + comp_map = &port->comp_map;
>
> Can you check if the following works instead, I think the
> pre-initialization is missing in cxl_mock_mem_probe() for
> cxl_test:
>
>
> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> index d6d067fbee97..4c4e33de4d74 100644
> --- a/drivers/cxl/core/mbox.c
> +++ b/drivers/cxl/core/mbox.c
> @@ -1333,6 +1333,8 @@ struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev)
> mutex_init(&mds->mbox_mutex);
> mutex_init(&mds->event.log_lock);
> mds->cxlds.dev = dev;
> + mds->cxlds.comp_map.dev = dev;
> + mds->cxlds.comp_map.resource = CXL_RESOURCE_NONE;
This has the same problem. @dev is specifying the lifetime of the
mapping. The lifetime of the mapping needs to be relative to the driver
using the registers. So if the cxl_port driver is mapping the component
registers the only valid device in the comp_map is &port->dev.
I notice that cxl_port_get_comp_map() endpoint port as an argument. That
endpoint port was instantiated with @cxlmd, but it seems not with
@cxlmd->cxlds->comp_map information which is available. Lets just fix
that. I.e. move devm_cxl_add_endpoint() into the core and make it
initialize @endpoint->comp_map with @cxlds->comp_map while switching
@dev in the @endpoint->comp_map to be @endpoint->dev, and not
@cxlds->dev.
...but it turns out that is the second bug in this patch. As I went to
try to reproduce this failure for a single port VH configuration I
notice another bug, a regression of this fix:
7bba261e0aa6 cxl/port: Scan single-target ports for decoders
...because there is no requirement for single port switches /
host-bridges to have HDM decoders per the specification, and the
original patch is turning HDM decoders not present as a hard failure.
> mds->cxlds.type = CXL_DEVTYPE_CLASSMEM;
>
> return mds;
> --
> 2.30.2
>
> The cxl_pci driver always has something valid or fails otherwise.
Understood, just copy that map at __devm_cxl_add_port() time. I am
thinking devm_cxl_add_endpoint() moves into core/port.c and it calls
__devm_cxl_add_port() directly with a new parameter to take a passed in
@comp_map or @component_reg_phys for the switch port case.
>
> If that works the change should be merged into patch #2.
>
> Thanks,
>
> -Robert
>
>
> > if (comp_map->resource == CXL_RESOURCE_NONE) {
> > if (info && info->mem_enabled) {
> > cxlhdm->decoder_count = info->ranges;
> >
> >
> > Am I missing why the cxlds->comp_map needs to be reused?
> >
> > Note that I am out and may not be able to respond further until next
> > week.
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
2023-08-08 3:00 ` Dan Williams
@ 2023-08-25 14:32 ` Robert Richter
0 siblings, 0 replies; 21+ messages in thread
From: Robert Richter @ 2023-08-25 14:32 UTC (permalink / raw)
To: Dan Williams
Cc: Terry Bowman, alison.schofield, vishal.l.verma, ira.weiny,
bwidawsk, dave.jiang, Jonathan.Cameron, linux-cxl, linux-kernel,
bhelgaas
On 07.08.23 20:00:41, Dan Williams wrote:
> Robert Richter wrote:
> > On 03.07.23 17:39:38, Dan Williams wrote:
> > [51/51] Linking target ndctl/ndctl
> > 1/6 ndctl:cxl / cxl-topology.sh OK 18.59s
> > 2/6 ndctl:cxl / cxl-region-sysfs.sh OK 12.26s
> > 3/6 ndctl:cxl / cxl-labels.sh OK 28.25s
> > 4/6 ndctl:cxl / cxl-create-region.sh OK 19.56s
> > 5/6 ndctl:cxl / cxl-xor-region.sh OK 10.57s
> > 6/6 ndctl:cxl / cxl-security.sh OK 9.77s
> >
> > Ok: 6
> > Expected Fail: 0
> > Fail: 0
> > Unexpected Pass: 0
> > Skipped: 0
> > Timeout: 0
> >
> > Full log written to /root/ndctl/build/meson-logs/testlog.txt
>
> So it turns out it is not cxl_test that is failing instead it is the
> tests noticing a regression of the VH base case. I am running
> cxl-topology.sh in a QEMU environment with a local device defined, and
> that local device is hitting a probe regression.
>
> When cxl_test goes to count the expected disabled devices it sees one
> more because the QEMU device is also disabled.
>
> ++ jq 'map(select(.state == "disabled")) | length'
> + count=5
> + (( count == 4 ))
> + err 170
> ++ basename /root/git/ndctl/test/cxl-topology.sh
> + echo test/cxl-topology.sh: failed at line 170
>
> ...i.e. only 4 devices are expected to be disabled, not the 5th one that
> was not on the cxl_test bus. I assume you are running without any other
> CXL devices?
>
> I will look into making that a more formalized case so that failure is
> not QEMU configuration dependent, but please make sure that QEMU CXL
> configs do not regress.
I finally could reproduce and root cause the issue.
I have isolated this to the operation on the qemu mem0 device, without
cxl_test involved:
root@qemu:~# cxl list
[
{
"memdev":"mem0",
"pmem_size":536870912,
"serial":0,
"host":"0000:35:00.0"
}
]
root@qemu:~# echo mem0 >/sys/bus/cxl/drivers/cxl_mem/unbind
[ 65.957423] nvdimm nmem0: trace
[ 66.001986] nd_bus ndbus0: nvdimm.remove(nmem0)
[ 66.041053] cxl_mem mem0: disconnect mem0 from port1
root@qemu:~# echo mem0 >/sys/bus/cxl/drivers/cxl_mem/bind
[ 75.076881] cxl_mem mem0: scan: iter: mem0 dport_dev: 0000:34:00.0 parent: pci0000:34
[ 75.077349] cxl_mem mem0: found already registered port port1:pci0000:34
[ 75.077653] cxl_mem mem0: host-bridge: pci0000:34
[ 75.078003] cxl_pci 0000:35:00.0: Failed to request region 0x00000000fe841110-0x00000000fe84119f
[ 75.078415] cxl_port endpoint2: Failed to map HDM capability.
[ 75.078683] cxl_port endpoint2: probe: -12
[ 75.078911] cxl_port: probe of endpoint2 failed with error -12
[ 75.079223] cxl_mem mem0: endpoint2 added to port1
[ 75.079469] cxl_mem mem0: endpoint2 failed probe
[ 75.079706] cxl_mem mem0: probe: -6
[ 75.079943] cxl_mem mem0: disconnect mem0 from port1
bash: echo: write error: No such device or address
root@qemu:~# cxl list -i
[
{
"memdev":"mem0",
"pmem_size":536870912,
"serial":0,
"host":"0000:35:00.0",
"state":"disabled"
}
]
The issue causes ndctl cxl tests with the cxl_test module to fail too.
> > > > +static struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port)
> > > > +{
> > > > + /*
> > > > + * HDM capability applies to Endpoints, USPs and VH Host
> > > > + * Bridges. The Endpoint's component register mappings are
> > > > + * located in the cxlds.
> > > > + */
> > > > + if (is_cxl_endpoint(port)) {
> > > > + struct cxl_memdev *memdev = to_cxl_memdev(port->uport_dev);
> > > > +
> > > > + return &memdev->cxlds->comp_map;
> > >
> > > ...but why? The issue here is that the @dev argument in that map is the
> > > memdev parent PCI device. However, in this context the @dev for devm
> > > operations wants to be &port->dev.
Right, I fixed this by changing the function i/f to pass @dev for the
devm operation. See below.
> >
> > The cxl_pci driver stores the comp_map of the endpoint in the cxlds
> > structure, struct cxl_port is not yet available at this point.
>
> When you say "this point" you mean "that point" in cxl_pci, right? I
> initially took that to mean literally "this" point in the quoted code
> above.
Yes, exactly. The mapping is in cxlds->comp_map, not port->comp_map.
>
> > See patch #2 of this series ("cxl/pci: Store the endpoint's Component
> > Register mappings in struct cxl_dev_state").
> >
> > >
> > > > + }
> > > > +
> > > > + return &port->comp_map;
> > >
> > > ...so this is fine, and folding in the following resolves the test
> > > failure.
> > >
> > > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> > > index b0f59e63e0d2..6f111f487795 100644
> > > --- a/drivers/cxl/core/hdm.c
> > > +++ b/drivers/cxl/core/hdm.c
> > > @@ -125,22 +125,6 @@ static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> > > return true;
> > > }
> > >
> > > -static struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port)
> > > -{
> > > - /*
> > > - * HDM capability applies to Endpoints, USPs and VH Host
> > > - * Bridges. The Endpoint's component register mappings are
> > > - * located in the cxlds.
> > > - */
> > > - if (is_cxl_endpoint(port)) {
> > > - struct cxl_memdev *memdev = to_cxl_memdev(port->uport_dev);
> > > -
> > > - return &memdev->cxlds->comp_map;
> > > - }
> > > -
> > > - return &port->comp_map;
> > > -}
> > > -
> > > /**
> > > * devm_cxl_setup_hdm - map HDM decoder component registers
> > > * @port: cxl_port to map
> > > @@ -160,8 +144,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
> > > cxlhdm->port = port;
> > > dev_set_drvdata(dev, cxlhdm);
> > >
> > > - comp_map = cxl_port_get_comp_map(port);
> > > -
> > > + comp_map = &port->comp_map;
> >
> > Can you check if the following works instead, I think the
> > pre-initialization is missing in cxl_mock_mem_probe() for
> > cxl_test:
> >
> >
> > diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> > index d6d067fbee97..4c4e33de4d74 100644
> > --- a/drivers/cxl/core/mbox.c
> > +++ b/drivers/cxl/core/mbox.c
> > @@ -1333,6 +1333,8 @@ struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev)
> > mutex_init(&mds->mbox_mutex);
> > mutex_init(&mds->event.log_lock);
> > mds->cxlds.dev = dev;
> > + mds->cxlds.comp_map.dev = dev;
> > + mds->cxlds.comp_map.resource = CXL_RESOURCE_NONE;
>
> This has the same problem. @dev is specifying the lifetime of the
> mapping. The lifetime of the mapping needs to be relative to the driver
> using the registers. So if the cxl_port driver is mapping the component
> registers the only valid device in the comp_map is &port->dev.
>
> I notice that cxl_port_get_comp_map() endpoint port as an argument. That
> endpoint port was instantiated with @cxlmd, but it seems not with
> @cxlmd->cxlds->comp_map information which is available. Lets just fix
> that. I.e. move devm_cxl_add_endpoint() into the core and make it
> initialize @endpoint->comp_map with @cxlds->comp_map while switching
> @dev in the @endpoint->comp_map to be @endpoint->dev, and not
> @cxlds->dev.
That does not work as we need the RAS cap early once cxl_pci is bound.
There are multiple devices using the comp_map. For proper devm release
we need to assign different devices depending on the users. That is,
the RAS cap is released with cxl_pci driver unbinding and HDM with the
memdev release. The fix I have chosen is to expand
cxl_map_component_regs() to pass the devm device to release it
together with the device using it.
>
> ...but it turns out that is the second bug in this patch. As I went to
> try to reproduce this failure for a single port VH configuration I
> notice another bug, a regression of this fix:
>
> 7bba261e0aa6 cxl/port: Scan single-target ports for decoders
>
> ...because there is no requirement for single port switches /
> host-bridges to have HDM decoders per the specification, and the
> original patch is turning HDM decoders not present as a hard failure.
But if the HDM is not present, a -ENODEV is still returned?
cxl_switch_port_probe() does not fail then.
>
> > mds->cxlds.type = CXL_DEVTYPE_CLASSMEM;
> >
> > return mds;
> > --
> > 2.30.2
> >
> > The cxl_pci driver always has something valid or fails otherwise.
>
> Understood, just copy that map at __devm_cxl_add_port() time. I am
> thinking devm_cxl_add_endpoint() moves into core/port.c and it calls
> __devm_cxl_add_port() directly with a new parameter to take a passed in
> @comp_map or @component_reg_phys for the switch port case.
Please take a look at the cxl_map_component_regs() update in v9. We
will send it out today. The changes compared to v8 are
straightforward.
Thanks,
-Robert
>
> >
> > If that works the change should be merged into patch #2.
> >
> > Thanks,
> >
> > -Robert
> >
> >
> > > if (comp_map->resource == CXL_RESOURCE_NONE) {
> > > if (info && info->mem_enabled) {
> > > cxlhdm->decoder_count = info->ranges;
> > >
> > >
> > > Am I missing why the cxlds->comp_map needs to be reused?
> > >
> > > Note that I am out and may not be able to respond further until next
> > > week.
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v8 04/14] cxl/pci: Remove Component Register base address from struct cxl_dev_state
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
` (2 preceding siblings ...)
2023-06-30 23:16 ` [PATCH v8 03/14] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-06-30 23:16 ` [PATCH v8 05/14] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
` (10 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
From: Robert Richter <rrichter@amd.com>
The Component Register base address @component_reg_phys is no longer
used after the rework of the Component Register setup which now uses
struct member @comp_map instead. Remove the base address.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/cxlmem.h | 2 --
drivers/cxl/mem.c | 4 ++--
drivers/cxl/pci.c | 3 ---
tools/testing/cxl/test/mem.c | 1 -
4 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 607ee34b0ce7..fdfa6e5dd739 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -390,7 +390,6 @@ enum cxl_devtype {
* @dpa_res: Overall DPA resource tree for the device
* @pmem_res: Active Persistent memory capacity configuration
* @ram_res: Active Volatile memory capacity configuration
- * @component_reg_phys: register base of component registers
* @serial: PCIe Device Serial Number
* @type: Generic Memory Class device or Vendor Specific Memory device
*/
@@ -405,7 +404,6 @@ struct cxl_dev_state {
struct resource dpa_res;
struct resource pmem_res;
struct resource ram_res;
- resource_size_t component_reg_phys;
u64 serial;
enum cxl_devtype type;
};
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
index 317c7548e4e9..3af3218ebe0e 100644
--- a/drivers/cxl/mem.c
+++ b/drivers/cxl/mem.c
@@ -49,7 +49,6 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
struct cxl_dport *parent_dport)
{
struct cxl_port *parent_port = parent_dport->port;
- struct cxl_dev_state *cxlds = cxlmd->cxlds;
struct cxl_port *endpoint, *iter, *down;
int rc;
@@ -65,8 +64,9 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,
ep->next = down;
}
+ /* The Endpoint's component regs are located in cxlds. */
endpoint = devm_cxl_add_port(host, &cxlmd->dev,
- cxlds->component_reg_phys,
+ CXL_RESOURCE_NONE,
parent_dport);
if (IS_ERR(endpoint))
return PTR_ERR(endpoint);
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 054cfa2f6a2d..2a5031f73c34 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -835,7 +835,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
* If the component registers can't be found, the cxl_pci driver may
* still be useful for management functions so don't return an error.
*/
- cxlds->component_reg_phys = CXL_RESOURCE_NONE;
rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,
&cxlds->comp_map);
if (rc)
@@ -843,8 +842,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
else if (!cxlds->comp_map.component_map.ras.valid)
dev_dbg(&pdev->dev, "RAS registers not found\n");
- cxlds->component_reg_phys = cxlds->comp_map.resource;
-
rc = cxl_map_component_regs(&cxlds->comp_map, &cxlds->regs.component,
BIT(CXL_CM_CAP_CAP_ID_RAS));
if (rc)
diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
index 464fc39ed277..aa44d111fd28 100644
--- a/tools/testing/cxl/test/mem.c
+++ b/tools/testing/cxl/test/mem.c
@@ -1423,7 +1423,6 @@ static int cxl_mock_mem_probe(struct platform_device *pdev)
cxlds->serial = pdev->id;
if (is_rcd(pdev)) {
cxlds->rcd = true;
- cxlds->component_reg_phys = CXL_RESOURCE_NONE;
}
rc = cxl_enumerate_cmds(mds);
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v8 05/14] cxl/port: Remove Component Register base address from struct cxl_port
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
` (3 preceding siblings ...)
2023-06-30 23:16 ` [PATCH v8 04/14] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-06-30 23:16 ` [PATCH v8 06/14] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
` (9 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
From: Robert Richter <rrichter@amd.com>
The Component Register base address @component_reg_phys is no longer
used after the rework of the Component Register setup which now uses
struct member @comp_map instead. Remove the base address.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/port.c | 4 +---
drivers/cxl/cxl.h | 2 --
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 2d22e7a5629b..99cf5cfbbcb2 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -618,7 +618,6 @@ static int devm_cxl_link_parent_dport(struct device *host,
static struct lock_class_key cxl_port_key;
static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
- resource_size_t component_reg_phys,
struct cxl_dport *parent_dport)
{
struct cxl_port *port;
@@ -669,7 +668,6 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
} else
dev->parent = uport_dev;
- port->component_reg_phys = component_reg_phys;
ida_init(&port->decoder_ida);
port->hdm_end = -1;
port->commit_end = -1;
@@ -730,7 +728,7 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host,
struct device *dev;
int rc;
- port = cxl_port_alloc(uport_dev, component_reg_phys, parent_dport);
+ port = cxl_port_alloc(uport_dev, parent_dport);
if (IS_ERR(port))
return port;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 76d92561af29..6c045a13ecf3 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -576,7 +576,6 @@ struct cxl_dax_region {
* @nr_dports: number of entries in @dports
* @hdm_end: track last allocated HDM decoder instance for allocation ordering
* @commit_end: cursor to track highest committed decoder for commit ordering
- * @component_reg_phys: component register capability base address (optional)
* @dead: last ep has been removed, force port re-creation
* @depth: How deep this port is relative to the root. depth 0 is the root.
* @cdat: Cached CDAT data
@@ -596,7 +595,6 @@ struct cxl_port {
int nr_dports;
int hdm_end;
int commit_end;
- resource_size_t component_reg_phys;
bool dead;
unsigned int depth;
struct cxl_cdat {
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v8 06/14] cxl/pci: Add RCH downstream port AER register discovery
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
` (4 preceding siblings ...)
2023-06-30 23:16 ` [PATCH v8 05/14] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-06-30 23:16 ` [PATCH v8 07/14] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
` (8 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
Restricted CXL host (RCH) downstream port AER information is not currently
logged while in the error state. One problem preventing the error logging
is the AER and RAS registers are not accessible. The CXL driver requires
changes to find RCH downstream port AER and RAS registers for purpose of
error logging.
RCH downstream ports are not enumerated during a PCI bus scan and are
instead discovered using system firmware, ACPI in this case.[1] The
downstream port is implemented as a Root Complex Register Block (RCRB).
The RCRB is a 4k memory block containing PCIe registers based on the PCIe
root port.[2] The RCRB includes AER extended capability registers used for
reporting errors. Note, the RCH's AER Capability is located in the RCRB
memory space instead of PCI configuration space, thus its register access
is different. Existing kernel PCIe AER functions can not be used to manage
the downstream port AER capabilities and RAS registers because the port was
not enumerated during PCI scan and the registers are not PCI config
accessible.
Discover RCH downstream port AER extended capability registers. Use MMIO
accesses to search for extended AER capability in RCRB register space.
[1] CXL 3.0 Spec, 9.11.2 - System Firmware View of CXL 1.1 Hierarchy
[2] CXL 3.0 Spec, 8.2.1.1 - RCH Downstream Port RCRB
Co-developed-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/core.h | 1 +
drivers/cxl/core/port.c | 6 ++++++
drivers/cxl/core/regs.c | 35 +++++++++++++++++++++++++++++++++++
3 files changed, 42 insertions(+)
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 45e7e044cf4a..f470ef5c0a6a 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -73,6 +73,7 @@ struct cxl_rcrb_info;
resource_size_t __rcrb_to_component(struct device *dev,
struct cxl_rcrb_info *ri,
enum cxl_rcrb which);
+u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
extern struct rw_semaphore cxl_dpa_rwsem;
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 99cf5cfbbcb2..8dd9a44e8a7d 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -978,6 +978,8 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
return ERR_PTR(-ENOMEM);
if (rcrb != CXL_RESOURCE_NONE) {
+ struct pci_host_bridge *host_bridge;
+
dport->rcrb.base = rcrb;
component_reg_phys = __rcrb_to_component(dport_dev, &dport->rcrb,
CXL_RCRB_DOWNSTREAM);
@@ -986,6 +988,10 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
return ERR_PTR(-ENXIO);
}
+ host_bridge = to_pci_host_bridge(dport_dev);
+ if (host_bridge->native_cxl_error)
+ dport->rcrb.aer_cap = cxl_rcrb_to_aer(dport_dev, dport->rcrb.base);
+
dport->rch = true;
}
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 6281127b3e9d..b34192bad2af 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -470,6 +470,41 @@ int cxl_setup_regs(struct cxl_register_map *map)
}
EXPORT_SYMBOL_NS_GPL(cxl_setup_regs, CXL);
+u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb)
+{
+ void __iomem *addr;
+ u16 offset = 0;
+ u32 cap_hdr;
+
+ if (WARN_ON_ONCE(rcrb == CXL_RESOURCE_NONE))
+ return 0;
+
+ if (!request_mem_region(rcrb, SZ_4K, dev_name(dev)))
+ return 0;
+
+ addr = ioremap(rcrb, SZ_4K);
+ if (!addr) {
+ release_mem_region(rcrb, SZ_4K);
+ return 0;
+ }
+
+ cap_hdr = readl(addr + offset);
+ while (PCI_EXT_CAP_ID(cap_hdr) != PCI_EXT_CAP_ID_ERR) {
+ offset = PCI_EXT_CAP_NEXT(cap_hdr);
+ if (!offset)
+ break;
+ cap_hdr = readl(addr + offset);
+ }
+
+ if (offset)
+ dev_dbg(dev, "found AER extended capability (0x%x)\n", offset);
+
+ iounmap(addr);
+ release_mem_region(rcrb, SZ_4K);
+
+ return offset;
+}
+
resource_size_t __rcrb_to_component(struct device *dev, struct cxl_rcrb_info *ri,
enum cxl_rcrb which)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v8 07/14] PCI/AER: Refactor cper_print_aer() for use by CXL driver module
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
` (5 preceding siblings ...)
2023-06-30 23:16 ` [PATCH v8 06/14] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-06-30 23:16 ` [PATCH v8 08/14] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
` (7 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas,
Mahesh J Salgaonkar, Oliver O'Halloran, linux-pci
The CXL driver plans to use cper_print_aer() for logging restricted CXL
host (RCH) AER errors. cper_print_aer() is not currently exported and
therefore not usable by the CXL drivers built as loadable modules. Export
the cper_print_aer() function. Use the EXPORT_SYMBOL_NS_GPL() variant
to restrict the export to CXL drivers.
The CONFIG_ACPI_APEI_PCIEAER kernel config is currently used to enable
cper_print_aer(). cper_print_aer() logs the AER registers and is
useful in PCIE AER logging outside of APEI. Remove the
CONFIG_ACPI_APEI_PCIEAER dependency to enable cper_print_aer().
The cper_print_aer() function name implies CPER specific use but is useful
in non-CPER cases as well. Rename cper_print_aer() to pci_print_aer().
Also, update cxl_core to import CXL namespace imports.
Co-developed-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
Cc: "Oliver O'Halloran" <oohall@gmail.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/port.c | 1 +
drivers/pci/pcie/aer.c | 9 +++++----
include/linux/aer.h | 2 +-
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 8dd9a44e8a7d..f3bb7ea37b44 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -2062,3 +2062,4 @@ static void cxl_core_exit(void)
subsys_initcall(cxl_core_init);
module_exit(cxl_core_exit);
MODULE_LICENSE("GPL v2");
+MODULE_IMPORT_NS(CXL);
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index f6c24ded134c..d3344fcf1f79 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -771,9 +771,10 @@ int cper_severity_to_aer(int cper_severity)
}
}
EXPORT_SYMBOL_GPL(cper_severity_to_aer);
+#endif
-void cper_print_aer(struct pci_dev *dev, int aer_severity,
- struct aer_capability_regs *aer)
+void pci_print_aer(struct pci_dev *dev, int aer_severity,
+ struct aer_capability_regs *aer)
{
int layer, agent, tlp_header_valid = 0;
u32 status, mask;
@@ -812,7 +813,7 @@ void cper_print_aer(struct pci_dev *dev, int aer_severity,
trace_aer_event(dev_name(&dev->dev), (status & ~mask),
aer_severity, tlp_header_valid, &aer->header_log);
}
-#endif
+EXPORT_SYMBOL_NS_GPL(pci_print_aer, CXL);
/**
* add_error_device - list device to be handled
@@ -1009,7 +1010,7 @@ static void aer_recover_work_func(struct work_struct *work)
PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
continue;
}
- cper_print_aer(pdev, entry.severity, entry.regs);
+ pci_print_aer(pdev, entry.severity, entry.regs);
if (entry.severity == AER_NONFATAL)
pcie_do_recovery(pdev, pci_channel_io_normal,
aer_root_reset);
diff --git a/include/linux/aer.h b/include/linux/aer.h
index 97f64ba1b34a..8f124b904314 100644
--- a/include/linux/aer.h
+++ b/include/linux/aer.h
@@ -64,7 +64,7 @@ static inline void pci_save_aer_state(struct pci_dev *dev) {}
static inline void pci_restore_aer_state(struct pci_dev *dev) {}
#endif
-void cper_print_aer(struct pci_dev *dev, int aer_severity,
+void pci_print_aer(struct pci_dev *dev, int aer_severity,
struct aer_capability_regs *aer);
int cper_severity_to_aer(int cper_severity);
void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v8 08/14] cxl/pci: Update CXL error logging to use RAS register address
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
` (6 preceding siblings ...)
2023-06-30 23:16 ` [PATCH v8 07/14] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-06-30 23:16 ` [PATCH v8 09/14] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
` (6 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
The CXL error handler currently only logs endpoint RAS status. The CXL
topology includes several components providing RAS details to be logged
during error handling.[1] Update the current handler's RAS logging to use a
RAS register address. Also, update the error handler function names to be
consistent with correctable and uncorrectable RAS. This will allow for
adding support to log other CXL component's RAS details in the future.
[1] CXL3.0 Table 8-22 CXL_Capability_ID Assignment
Co-developed-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/pci.c | 44 +++++++++++++++++++++++++++++-------------
1 file changed, 31 insertions(+), 13 deletions(-)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index c7a7887ebdcf..edfee8035820 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -646,32 +646,36 @@ void read_cdat_data(struct cxl_port *port)
}
EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
-void cxl_cor_error_detected(struct pci_dev *pdev)
+static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds,
+ void __iomem *ras_base)
{
- struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
void __iomem *addr;
u32 status;
- if (!cxlds->regs.ras)
+ if (!ras_base)
return;
- addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
+ addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
status = readl(addr);
if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
trace_cxl_aer_correctable_error(cxlds->cxlmd, status);
}
}
-EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, CXL);
+
+static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds)
+{
+ return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras);
+}
/* CXL spec rev3.0 8.2.4.16.1 */
-static void header_log_copy(struct cxl_dev_state *cxlds, u32 *log)
+static void header_log_copy(void __iomem *ras_base, u32 *log)
{
void __iomem *addr;
u32 *log_addr;
int i, log_u32_size = CXL_HEADERLOG_SIZE / sizeof(u32);
- addr = cxlds->regs.ras + CXL_RAS_HEADER_LOG_OFFSET;
+ addr = ras_base + CXL_RAS_HEADER_LOG_OFFSET;
log_addr = log;
for (i = 0; i < log_u32_size; i++) {
@@ -685,17 +689,18 @@ static void header_log_copy(struct cxl_dev_state *cxlds, u32 *log)
* Log the state of the RAS status registers and prepare them to log the
* next error status. Return 1 if reset needed.
*/
-static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
+static bool __cxl_handle_ras(struct cxl_dev_state *cxlds,
+ void __iomem *ras_base)
{
u32 hl[CXL_HEADERLOG_SIZE_U32];
void __iomem *addr;
u32 status;
u32 fe;
- if (!cxlds->regs.ras)
+ if (!ras_base)
return false;
- addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET;
+ addr = ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET;
status = readl(addr);
if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK))
return false;
@@ -703,7 +708,7 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
/* If multiple errors, log header points to first error from ctrl reg */
if (hweight32(status) > 1) {
void __iomem *rcc_addr =
- cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
+ ras_base + CXL_RAS_CAP_CONTROL_OFFSET;
fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,
readl(rcc_addr)));
@@ -711,13 +716,26 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
fe = status;
}
- header_log_copy(cxlds, hl);
+ header_log_copy(ras_base, hl);
trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl);
writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
return true;
}
+static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds)
+{
+ return __cxl_handle_ras(cxlds, cxlds->regs.ras);
+}
+
+void cxl_cor_error_detected(struct pci_dev *pdev)
+{
+ struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
+
+ cxl_handle_endpoint_cor_ras(cxlds);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, CXL);
+
pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
{
@@ -732,7 +750,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
* chance the situation is recoverable dump the status of the RAS
* capability registers and bounce the active state of the memdev.
*/
- ue = cxl_report_and_clear(cxlds);
+ ue = cxl_handle_endpoint_ras(cxlds);
switch (state) {
case pci_channel_io_normal:
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v8 09/14] cxl/pci: Map RCH downstream AER registers for logging protocol errors
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
` (7 preceding siblings ...)
2023-06-30 23:16 ` [PATCH v8 08/14] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-06-30 23:16 ` [PATCH v8 10/14] cxl/pci: Add RCH downstream port error logging Terry Bowman
` (5 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
The restricted CXL host (RCH) error handler will log protocol errors
using AER and RAS status registers. The AER and RAS registers need
to be virtually memory mapped before enabling interrupts. Update
__devm_cxl_add_dport() to include RCH RAS and AER mapping.
Add 'struct cxl_regs' to 'struct cxl_dport' for saving a pointer to
the RCH downstream port's AER and RAS registers.
Co-developed-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/port.c | 33 +++++++++++++++++++++++++++++++++
drivers/cxl/core/regs.c | 1 +
drivers/cxl/cxl.h | 12 ++++++++++++
3 files changed, 46 insertions(+)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index f3bb7ea37b44..a482341c0d89 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -8,6 +8,7 @@
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/idr.h>
+#include <linux/aer.h>
#include <cxlmem.h>
#include <cxlpci.h>
#include <cxl.h>
@@ -948,6 +949,36 @@ static void cxl_dport_unlink(void *data)
sysfs_remove_link(&port->dev.kobj, link_name);
}
+static void cxl_dport_map_rch_aer(struct cxl_dport *dport)
+{
+ struct cxl_rcrb_info *ri = &dport->rcrb;
+ struct cxl_port *port = dport->port;
+ void __iomem *dport_aer = NULL;
+ resource_size_t aer_phys;
+
+ if (dport->rch && ri->aer_cap) {
+ aer_phys = ri->aer_cap + ri->base;
+ dport_aer = devm_cxl_iomap_block(&port->dev, aer_phys,
+ sizeof(struct aer_capability_regs));
+ }
+
+ dport->regs.dport_aer = dport_aer;
+}
+
+static void cxl_dport_map_regs(struct cxl_dport *dport)
+{
+ struct cxl_register_map *map = &dport->comp_map;
+
+ if (!map->component_map.ras.valid)
+ dev_dbg(dport->dport_dev, "RAS registers not found\n");
+ else if (cxl_map_component_regs(map, &dport->regs.component,
+ BIT(CXL_CM_CAP_CAP_ID_RAS)))
+ dev_dbg(dport->dport_dev, "Failed to map RAS capability.\n");
+
+ if (dport->rch)
+ cxl_dport_map_rch_aer(dport);
+}
+
static struct cxl_dport *
__devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
int port_id, resource_size_t component_reg_phys,
@@ -1007,6 +1038,8 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
if (rc)
return ERR_PTR(rc);
+ cxl_dport_map_regs(dport);
+
cond_cxl_root_lock(port);
rc = add_dport(port, dport);
cond_cxl_root_unlock(port);
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index b34192bad2af..2360b480c5c5 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -199,6 +199,7 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
return ret_val;
}
+EXPORT_SYMBOL_NS_GPL(devm_cxl_iomap_block, CXL);
int cxl_map_component_regs(const struct cxl_register_map *map,
struct cxl_component_regs *regs,
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 6c045a13ecf3..ec656abad9b3 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -221,6 +221,14 @@ struct cxl_regs {
struct_group_tagged(cxl_pmu_regs, pmu_regs,
void __iomem *pmu;
);
+
+ /*
+ * RCH downstream port specific RAS register
+ * @aer: CXL 3.0 8.2.1.1 RCH Downstream Port RCRB
+ */
+ struct_group_tagged(cxl_rch_regs, rch_regs,
+ void __iomem *dport_aer;
+ );
};
struct cxl_reg_map {
@@ -273,6 +281,8 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
struct cxl_component_reg_map *map);
void cxl_probe_device_regs(struct device *dev, void __iomem *base,
struct cxl_device_reg_map *map);
+void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
+ resource_size_t length);
int cxl_map_component_regs(const struct cxl_register_map *map,
struct cxl_component_regs *regs,
unsigned long map_mask);
@@ -623,6 +633,7 @@ struct cxl_rcrb_info {
* @rcrb: Data about the Root Complex Register Block layout
* @rch: Indicate whether this dport was enumerated in RCH or VH mode
* @port: reference to cxl_port that contains this downstream port
+ * @regs: Dport parsed register blocks
*/
struct cxl_dport {
struct device *dport_dev;
@@ -631,6 +642,7 @@ struct cxl_dport {
struct cxl_rcrb_info rcrb;
bool rch;
struct cxl_port *port;
+ struct cxl_regs regs;
};
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v8 10/14] cxl/pci: Add RCH downstream port error logging
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
` (8 preceding siblings ...)
2023-06-30 23:16 ` [PATCH v8 09/14] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-06-30 23:16 ` [PATCH v8 11/14] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
` (4 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
RCH downstream port error logging is missing in the current CXL driver. The
missing AER and RAS error logging is needed for communicating driver error
details to userspace. Update the driver to include PCIe AER and CXL RAS
error logging.
Add RCH downstream port error handling into the existing RCiEP handler.
The downstream port error handler is added to the RCiEP error handler
because the downstream port is implemented in a RCRB, is not PCI
enumerable, and as a result is not directly accessible to the PCI AER
root port driver. The AER root port driver calls the RCiEP handler for
handling RCD errors and RCH downstream port protocol errors.
Update existing RCiEP correctable and uncorrectable handlers to also call
the RCH handler. The RCH handler will read the RCH AER registers, check for
error severity, and if an error exists will log using an existing kernel
AER trace routine. The RCH handler will also log downstream port RAS errors
if they exist.
Co-developed-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/pci.c | 101 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 101 insertions(+)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index edfee8035820..1c40270968b6 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -5,6 +5,7 @@
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/pci-doe.h>
+#include <linux/aer.h>
#include <cxlpci.h>
#include <cxlmem.h>
#include <cxl.h>
@@ -728,10 +729,107 @@ static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds)
return __cxl_handle_ras(cxlds, cxlds->regs.ras);
}
+#ifdef CONFIG_PCIEAER_CXL
+
+static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds,
+ struct cxl_dport *dport)
+{
+ return __cxl_handle_cor_ras(cxlds, dport->regs.ras);
+}
+
+static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds,
+ struct cxl_dport *dport)
+{
+ return __cxl_handle_ras(cxlds, dport->regs.ras);
+}
+
+/*
+ * Copy the AER capability registers using 32 bit read accesses.
+ * This is necessary because RCRB AER capability is MMIO mapped. Clear the
+ * status after copying.
+ *
+ * @aer_base: base address of AER capability block in RCRB
+ * @aer_regs: destination for copying AER capability
+ */
+static bool cxl_rch_get_aer_info(void __iomem *aer_base,
+ struct aer_capability_regs *aer_regs)
+{
+ int read_cnt = sizeof(struct aer_capability_regs) / sizeof(u32);
+ u32 *aer_regs_buf = (u32 *)aer_regs;
+ int n;
+
+ if (!aer_base)
+ return false;
+
+ /* Use readl() to guarantee 32-bit accesses */
+ for (n = 0; n < read_cnt; n++)
+ aer_regs_buf[n] = readl(aer_base + n * sizeof(u32));
+
+ writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS);
+ writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS);
+
+ return true;
+}
+
+/* Get AER severity. Return false if there is no error. */
+static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs,
+ int *severity)
+{
+ if (aer_regs->uncor_status & ~aer_regs->uncor_mask) {
+ if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV)
+ *severity = AER_FATAL;
+ else
+ *severity = AER_NONFATAL;
+ return true;
+ }
+
+ if (aer_regs->cor_status & ~aer_regs->cor_mask) {
+ *severity = AER_CORRECTABLE;
+ return true;
+ }
+
+ return false;
+}
+
+static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)
+{
+ struct pci_dev *pdev = to_pci_dev(cxlds->dev);
+ struct aer_capability_regs aer_regs;
+ struct cxl_dport *dport;
+ struct cxl_port *port;
+ int severity;
+
+ port = cxl_pci_find_port(pdev, &dport);
+ if (!port)
+ return;
+
+ put_device(&port->dev);
+
+ if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs))
+ return;
+
+ if (!cxl_rch_get_aer_severity(&aer_regs, &severity))
+ return;
+
+ pci_print_aer(pdev, severity, &aer_regs);
+
+ if (severity == AER_CORRECTABLE)
+ cxl_handle_rdport_cor_ras(cxlds, dport);
+ else
+ cxl_handle_rdport_ras(cxlds, dport);
+}
+
+#else
+static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { }
+#endif
+
void cxl_cor_error_detected(struct pci_dev *pdev)
{
struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
+ if (cxlds->rcd)
+ cxl_handle_rdport_errors(cxlds);
+
cxl_handle_endpoint_cor_ras(cxlds);
}
EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, CXL);
@@ -744,6 +842,9 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
struct device *dev = &cxlmd->dev;
bool ue;
+ if (cxlds->rcd)
+ cxl_handle_rdport_errors(cxlds);
+
/*
* A frozen channel indicates an impending reset which is fatal to
* CXL.mem operation, and will likely crash the system. On the off
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v8 11/14] cxl/pci: Disable root port interrupts in RCH mode
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
` (9 preceding siblings ...)
2023-06-30 23:16 ` [PATCH v8 10/14] cxl/pci: Add RCH downstream port error logging Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-06-30 23:16 ` [PATCH v8 12/14] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
` (3 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
The RCH root port contains root command AER registers that should not be
enabled.[1] Disable these to prevent root port interrupts.
[1] CXL 3.0 - 12.2.1.1 RCH Downstream Port-detected Errors
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/core.h | 6 ++++++
drivers/cxl/core/pci.c | 29 +++++++++++++++++++++++++++++
drivers/cxl/core/port.c | 3 +++
3 files changed, 38 insertions(+)
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index f470ef5c0a6a..6b037030b936 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -87,4 +87,10 @@ enum cxl_poison_trace_type {
CXL_POISON_TRACE_CLEAR,
};
+#ifdef CONFIG_PCIEAER_CXL
+void cxl_disable_rch_root_ints(struct cxl_dport *dport);
+#else
+static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { };
+#endif
+
#endif /* __CXL_CORE_H__ */
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 1c40270968b6..e306d3c9638b 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -819,6 +819,35 @@ static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)
cxl_handle_rdport_ras(cxlds, dport);
}
+void cxl_disable_rch_root_ints(struct cxl_dport *dport)
+{
+ void __iomem *aer_base = dport->regs.dport_aer;
+ struct pci_host_bridge *bridge;
+ u32 aer_cmd_mask, aer_cmd;
+
+ if (!aer_base)
+ return;
+
+ bridge = to_pci_host_bridge(dport->dport_dev);
+
+ /*
+ * Disable RCH root port command interrupts.
+ * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors
+ *
+ * This sequence may not be necessary. CXL spec states disabling
+ * the root cmd register's interrupts is required. But, PCI spec
+ * shows these are disabled by default on reset.
+ */
+ if (bridge->native_cxl_error) {
+ aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN |
+ PCI_ERR_ROOT_CMD_NONFATAL_EN |
+ PCI_ERR_ROOT_CMD_FATAL_EN);
+ aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND);
+ aer_cmd &= ~aer_cmd_mask;
+ writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND);
+ }
+}
+
#else
static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { }
#endif
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index a482341c0d89..71df10309be8 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1040,6 +1040,9 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
cxl_dport_map_regs(dport);
+ if (dport->rch)
+ cxl_disable_rch_root_ints(dport);
+
cond_cxl_root_lock(port);
rc = add_dport(port, dport);
cond_cxl_root_unlock(port);
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v8 12/14] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
` (10 preceding siblings ...)
2023-06-30 23:16 ` [PATCH v8 11/14] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-06-30 23:16 ` [PATCH v8 13/14] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
` (2 subsequent siblings)
14 siblings, 0 replies; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas,
Oliver O'Halloran, linuxppc-dev, linux-pci
From: Robert Richter <rrichter@amd.com>
In Restricted CXL Device (RCD) mode a CXL device is exposed as an
RCiEP, but CXL downstream and upstream ports are not enumerated and
not visible in the PCIe hierarchy. [1] Protocol and link errors from
these non-enumerated ports are signaled as internal AER errors, either
Uncorrectable Internal Error (UIE) or Corrected Internal Errors (CIE)
via an RCEC.
Restricted CXL host (RCH) downstream port-detected errors have the
Requester ID of the RCEC set in the RCEC's AER Error Source ID
register. A CXL handler must then inspect the error status in various
CXL registers residing in the dport's component register space (CXL
RAS capability) or the dport's RCRB (PCIe AER extended
capability). [2]
Errors showing up in the RCEC's error handler must be handled and
connected to the CXL subsystem. Implement this by forwarding the error
to all CXL devices below the RCEC. Since the entire CXL device is
controlled only using PCIe Configuration Space of device 0, function
0, only pass it there [3]. The error handling is limited to currently
supported devices with the Memory Device class code set (CXL Type 3
Device, PCI_CLASS_MEMORY_CXL, 502h), handle downstream port errors in
the device's cxl_pci driver. Support for other CXL Device Types
(e.g. a CXL.cache Device) can be added later.
To handle downstream port errors in addition to errors directed to the
CXL endpoint device, a handler must also inspect the CXL RAS and PCIe
AER capabilities of the CXL downstream port the device is connected
to.
Since CXL downstream port errors are signaled using internal errors,
the handler requires those errors to be unmasked. This is subject of a
follow-on patch.
The reason for choosing this implementation is that the AER service
driver claims the RCEC device, but does not allow it to register a
custom specific handler to support CXL. Connecting the RCEC hard-wired
with a CXL handler does not work, as the CXL subsystem might not be
present all the time. The alternative to add an implementation to the
portdrv to allow the registration of a custom RCEC error handler isn't
worth doing it as CXL would be its only user. Instead, just check for
an CXL RCEC and pass it down to the connected CXL device's error
handler. With this approach the code can entirely be implemented in
the PCIe AER driver and is independent of the CXL subsystem. The CXL
driver only provides the handler.
[1] CXL 3.0 spec: 9.11.8 CXL Devices Attached to an RCH
[2] CXL 3.0 spec, 12.2.1.1 RCH Downstream Port-detected Errors
[3] CXL 3.0 spec, 8.1.3 PCIe DVSEC for CXL Devices
Co-developed-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Cc: "Oliver O'Halloran" <oohall@gmail.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-pci@vger.kernel.org
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/pci/pcie/Kconfig | 12 +++++
drivers/pci/pcie/aer.c | 96 +++++++++++++++++++++++++++++++++++++++-
2 files changed, 106 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig
index 228652a59f27..4f0e70fafe2d 100644
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -49,6 +49,18 @@ config PCIEAER_INJECT
gotten from:
https://git.kernel.org/cgit/linux/kernel/git/gong.chen/aer-inject.git/
+config PCIEAER_CXL
+ bool "PCI Express CXL RAS support for Restricted Hosts (RCH)"
+ default y
+ depends on PCIEAER && CXL_PCI
+ help
+ Enables error handling of downstream ports of a CXL host
+ that is operating in RCD mode (Restricted CXL Host, RCH).
+ The downstream port reports AER errors to a given RCEC.
+ Errors are handled by the CXL memory device driver.
+
+ If unsure, say Y.
+
#
# PCI Express ECRC
#
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index d3344fcf1f79..c354ca5e8f2b 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -946,14 +946,100 @@ static bool find_source_device(struct pci_dev *parent,
return true;
}
+#ifdef CONFIG_PCIEAER_CXL
+
+static bool is_cxl_mem_dev(struct pci_dev *dev)
+{
+ /*
+ * The capability, status, and control fields in Device 0,
+ * Function 0 DVSEC control the CXL functionality of the
+ * entire device (CXL 3.0, 8.1.3).
+ */
+ if (dev->devfn != PCI_DEVFN(0, 0))
+ return false;
+
+ /*
+ * CXL Memory Devices must have the 502h class code set (CXL
+ * 3.0, 8.1.12.1).
+ */
+ if ((dev->class >> 8) != PCI_CLASS_MEMORY_CXL)
+ return false;
+
+ return true;
+}
+
+static bool cxl_error_is_native(struct pci_dev *dev)
+{
+ struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
+
+ if (pcie_ports_native)
+ return true;
+
+ return host->native_aer && host->native_cxl_error;
+}
+
+static bool is_internal_error(struct aer_err_info *info)
+{
+ if (info->severity == AER_CORRECTABLE)
+ return info->status & PCI_ERR_COR_INTERNAL;
+
+ return info->status & PCI_ERR_UNC_INTN;
+}
+
+static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data)
+{
+ struct aer_err_info *info = (struct aer_err_info *)data;
+ const struct pci_error_handlers *err_handler;
+
+ if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev))
+ return 0;
+
+ /* protect dev->driver */
+ device_lock(&dev->dev);
+
+ err_handler = dev->driver ? dev->driver->err_handler : NULL;
+ if (!err_handler)
+ goto out;
+
+ if (info->severity == AER_CORRECTABLE) {
+ if (err_handler->cor_error_detected)
+ err_handler->cor_error_detected(dev);
+ } else if (err_handler->error_detected) {
+ if (info->severity == AER_NONFATAL)
+ err_handler->error_detected(dev, pci_channel_io_normal);
+ else if (info->severity == AER_FATAL)
+ err_handler->error_detected(dev, pci_channel_io_frozen);
+ }
+out:
+ device_unlock(&dev->dev);
+ return 0;
+}
+
+static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info)
+{
+ /*
+ * Internal errors of an RCEC indicate an AER error in an
+ * RCH's downstream port. Check and handle them in the CXL.mem
+ * device driver.
+ */
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC &&
+ is_internal_error(info))
+ pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info);
+}
+
+#else
+static inline void cxl_rch_handle_error(struct pci_dev *dev,
+ struct aer_err_info *info) { }
+#endif
+
/**
- * handle_error_source - handle logging error into an event log
+ * pci_aer_handle_error - handle logging error into an event log
* @dev: pointer to pci_dev data structure of error source device
* @info: comprehensive error information
*
* Invoked when an error being detected by Root Port.
*/
-static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
+static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info)
{
int aer = dev->aer_cap;
@@ -977,6 +1063,12 @@ static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset);
else if (info->severity == AER_FATAL)
pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset);
+}
+
+static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info)
+{
+ cxl_rch_handle_error(dev, info);
+ pci_aer_handle_error(dev, info);
pci_dev_put(dev);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v8 13/14] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
` (11 preceding siblings ...)
2023-06-30 23:16 ` [PATCH v8 12/14] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-06-30 23:16 ` [PATCH v8 14/14] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-07-01 0:20 ` [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Dan Williams
14 siblings, 0 replies; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
From: Robert Richter <rrichter@amd.com>
AER corrected and uncorrectable internal errors (CIE/UIE) are masked
in their corresponding mask registers per default once in power-up
state. [1][2] Enable internal errors for RCECs to receive CXL
downstream port errors of Restricted CXL Hosts (RCHs).
[1] CXL 3.0 Spec, 12.2.1.1 - RCH Downstream Port Detected Errors
[2] PCIe Base Spec r6.0, 7.8.4.3 Uncorrectable Error Mask Register,
7.8.4.6 Correctable Error Mask Register
Co-developed-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/pci/pcie/aer.c | 57 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index c354ca5e8f2b..916fbca95e53 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -948,6 +948,30 @@ static bool find_source_device(struct pci_dev *parent,
#ifdef CONFIG_PCIEAER_CXL
+/**
+ * pci_aer_unmask_internal_errors - unmask internal errors
+ * @dev: pointer to the pcie_dev data structure
+ *
+ * Unmasks internal errors in the Uncorrectable and Correctable Error
+ * Mask registers.
+ *
+ * Note: AER must be enabled and supported by the device which must be
+ * checked in advance, e.g. with pcie_aer_is_native().
+ */
+static void pci_aer_unmask_internal_errors(struct pci_dev *dev)
+{
+ int aer = dev->aer_cap;
+ u32 mask;
+
+ pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);
+ mask &= ~PCI_ERR_UNC_INTN;
+ pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask);
+
+ pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);
+ mask &= ~PCI_ERR_COR_INTERNAL;
+ pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);
+}
+
static bool is_cxl_mem_dev(struct pci_dev *dev)
{
/*
@@ -1027,7 +1051,39 @@ static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info)
pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info);
}
+static int handles_cxl_error_iter(struct pci_dev *dev, void *data)
+{
+ bool *handles_cxl = data;
+
+ if (!*handles_cxl)
+ *handles_cxl = is_cxl_mem_dev(dev) && cxl_error_is_native(dev);
+
+ /* Non-zero terminates iteration */
+ return *handles_cxl;
+}
+
+static bool handles_cxl_errors(struct pci_dev *rcec)
+{
+ bool handles_cxl = false;
+
+ if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC &&
+ pcie_aer_is_native(rcec))
+ pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl);
+
+ return handles_cxl;
+}
+
+static void cxl_rch_enable_rcec(struct pci_dev *rcec)
+{
+ if (!handles_cxl_errors(rcec))
+ return;
+
+ pci_aer_unmask_internal_errors(rcec);
+ pci_info(rcec, "CXL: Internal errors unmasked");
+}
+
#else
+static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { }
static inline void cxl_rch_handle_error(struct pci_dev *dev,
struct aer_err_info *info) { }
#endif
@@ -1428,6 +1484,7 @@ static int aer_probe(struct pcie_device *dev)
return status;
}
+ cxl_rch_enable_rcec(port);
aer_enable_rootport(rpc);
pci_info(port, "enabled with IRQ %d\n", dev->irq);
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v8 14/14] cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
` (12 preceding siblings ...)
2023-06-30 23:16 ` [PATCH v8 13/14] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
@ 2023-06-30 23:16 ` Terry Bowman
2023-07-01 0:20 ` [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Dan Williams
14 siblings, 0 replies; 21+ messages in thread
From: Terry Bowman @ 2023-06-30 23:16 UTC (permalink / raw)
To: alison.schofield, vishal.l.verma, ira.weiny, bwidawsk,
dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
From: Robert Richter <rrichter@amd.com>
Trivial change that renames variable phys_addr in
cxl_map_component_regs() to shorten its length to keep the 80 char
size limit for the line and also for consistency between the different
paths.
Signed-off-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/regs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 2360b480c5c5..d22ba5a76b33 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -217,16 +217,16 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
for (i = 0; i < ARRAY_SIZE(mapinfo); i++) {
struct mapinfo *mi = &mapinfo[i];
- resource_size_t phys_addr;
+ resource_size_t addr;
resource_size_t length;
if (!mi->rmap->valid)
continue;
if (!test_bit(mi->rmap->id, &map_mask))
continue;
- phys_addr = map->resource + mi->rmap->offset;
+ addr = map->resource + mi->rmap->offset;
length = mi->rmap->size;
- *(mi->addr) = devm_cxl_iomap_block(dev, phys_addr, length);
+ *(mi->addr) = devm_cxl_iomap_block(dev, addr, length);
if (!*(mi->addr))
return -ENOMEM;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling
2023-06-30 23:16 [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling Terry Bowman
` (13 preceding siblings ...)
2023-06-30 23:16 ` [PATCH v8 14/14] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
@ 2023-07-01 0:20 ` Dan Williams
14 siblings, 0 replies; 21+ messages in thread
From: Dan Williams @ 2023-07-01 0:20 UTC (permalink / raw)
To: Terry Bowman, alison.schofield, vishal.l.verma, ira.weiny,
bwidawsk, dan.j.williams, dave.jiang, Jonathan.Cameron, linux-cxl
Cc: terry.bowman, rrichter, linux-kernel, bhelgaas
Terry Bowman wrote:
> This patchset enables CXL RCH error handling. This is necessary because RCH
> downstream port protocol error handling is implemented uniquely and not
> currently supported. These patches address the following:
>
> * Discovery and mapping of RCH downstream port AER registers.
>
> * AER portdrv changes to support CXL RCH protocol errors.
>
> * Interrupt setup specific to RCH mode: enabling RCEC internal
> errors and disabling root port interrupts.
>
> Changes in V8:
> - Rebased onto: commit
> 0c0df63177e3 ("Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl")
> - cxl/port: Pre-initialize component register mappings
> - Added patch to pre-initialize component register mappings.
> - cxl/pci: Remove Component Register base address from
> - Separated removal of Component Register base address in struct
> cxl_dev_state to not break functionality.
> - cxl/hdm: Use stored Component Register mappings to map HDM decoder
> capability
> - Implemented a less strict check in devm_cxl_setup_hdm(), be tolerant
> if HDM decoder registers are not implemented.
> - cxl/pci: Map RCH downstream AER registers for logging protocol errors
> - Fixed uninitialized access of map->dev in cxl_dport_map_regs().
> - PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem
> dev handler
> - Fix typo in patch description.
> - cxl/pci: Update CXL error logging to use RAS register address
> - Fix typo in patch description.
Hey Terry, thank you for turning this around so quickly. I will have a
look and see if this is suitable as a follow-up merge for v6.5 next week
since it would be nice to finish this off this cycle, but no promises.
^ permalink raw reply [flat|nested] 21+ messages in thread