From: Peter Zijlstra <peterz@infradead.org>
To: Borislav Petkov <bp@alien8.de>
Cc: X86 ML <x86@kernel.org>,
Kishon VijayAbraham <Kishon.VijayAbraham@amd.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] x86/barrier: Do not serialize MSR accesses on AMD
Date: Tue, 4 Jul 2023 11:01:32 +0200 [thread overview]
Message-ID: <20230704090132.GP4253@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20230704074631.GAZKPOV/9BfqP0aU8v@fat_crate.local>
On Tue, Jul 04, 2023 at 09:46:31AM +0200, Borislav Petkov wrote:
> On Mon, Jul 03, 2023 at 02:54:19PM +0200, Peter Zijlstra wrote:
> > So you're saying that AMD tsc_deadline and x2apic MSRs *do* imply
> > ordering constraints unlike the Intel ones?
>
> Yah, that's the default situation. Only those two - TSC_DEADLINE and
> x2APIC MSRs - and on *Intel* are special.
So they are normal MSRs like all other? AMD doesn't have any exceptions
for MSRs, they all the same?
> > Both instructions are 3 bytes, a 6 byte nop would be better, no?
>
> Why? You wanna save the branch insn when sending IPIs through the
> x2APIC? Does that really matter? I doubt it...
Dunno, code density, speculation, many raisons to avoid jumps :-)
> > asm volatile (ALTERNATIVE("mfence; lfence;", "", X86_FEATURE_AMD));
>
> There's no X86_FEATURE_AMD :)
I know, but that's easily fixed.
next prev parent reply other threads:[~2023-07-04 9:03 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-22 9:52 [PATCH] x86/barrier: Do not serialize MSR accesses on AMD Borislav Petkov
2023-07-03 12:54 ` Peter Zijlstra
2023-07-04 7:46 ` Borislav Petkov
2023-07-04 9:01 ` Peter Zijlstra [this message]
2023-07-04 9:22 ` Borislav Petkov
[not found] ` <20231027153327.GKZTvYR3qslaTUjtCT@fat_crate.local>
[not found] ` <20231027153418.GLZTvYejCkXb03rArO@fat_crate.local>
2023-10-27 18:11 ` [PATCH 1/2] x86/alternative: Add per-vendor patching Peter Zijlstra
2023-10-27 18:25 ` Borislav Petkov
[not found] ` <20231027153458.GMZTvYou1tlK6HD8/Y@fat_crate.local>
2023-10-27 18:56 ` [PATCH 2/2] x86/barrier: Do not serialize MSR accesses on AMD Peter Zijlstra
2023-10-27 19:16 ` Borislav Petkov
2023-10-27 19:29 ` Borislav Petkov
2023-10-27 20:09 ` Andrew Cooper
2023-10-27 20:23 ` Borislav Petkov
2023-10-29 10:35 ` [PATCH -v3] " Borislav Petkov
2023-11-02 11:08 ` [PATCH 2/2] " Borislav Petkov
2023-11-13 8:56 ` [tip: x86/cpu] " tip-bot2 for Borislav Petkov (AMD)
2023-11-13 9:21 ` tip-bot2 for Borislav Petkov (AMD)
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