Re: [PATCH] Revert "PCI: dwc: Wait for link up only if link is started"

Manivannan Sadhasivam
2023-07-06T12:58:25Z

On Thu, Jul 06, 2023 at 10:26:10AM +0200, Johan Hovold wrote:
> This reverts commit da56a1bfbab55189595e588f1d984bdfb5cf5924.
>
> A recent commit broke controller probe by returning an error in case the
> link does not come up during host initialisation.
>
> As explained in commit 886a9c134755 ("PCI: dwc: Move link handling into
> common code") and as indicated by the comment "Ignore errors, the link
> may come up later" in the code, waiting for link up and ignoring errors
> is the intended behaviour:
>
> Let's standardize this to succeed as there are usecases where
> devices (and the link) appear later even without hotplug. For
> example, a reconfigured FPGA device.
>
> Reverting the offending commit specifically fixes a regression on
> Qualcomm platforms like the Lenovo ThinkPad X13s which no longer reach
> the interconnect sync state if a slot does not have a device populated
> (e.g. an optional modem).
>
> Note that enabling asynchronous probing by default as was done for
> Qualcomm platforms by commit c0e1eb441b1d ("PCI: qcom: Enable async
> probe by default"), should take care of any related boot time concerns.
>
> Finally, note that the intel-gw driver is the only driver currently not
> providing a start_link callback and instead starts the link in its
> host_init callback, and which may avoid an additional one-second timeout
> during probe by making the link-up wait conditional. If anyone cares,
> that can be done in a follow-up patch with a proper motivation.
>

The offending commit is bogus since it makes the intel-gw _special_ w.r.t
waiting for the link up. Most of the drivers call dw_pcie_host_init() during the
probe time and they all have to wait for 1 sec if the slot is empty.

As Johan noted, intel-gw should make use of the async probe to avoid the boot
delay instead of adding a special case.

> Fixes: da56a1bfbab5 ("PCI: dwc: Wait for link up only if link is started")
> Reported-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Cc: Sajid Dalvi <sdalvi@google.com>
> Cc: Ajay Agarwal <ajayagarwal@google.com>
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> ---
> .../pci/controller/dwc/pcie-designware-host.c | 13 ++++--------
> drivers/pci/controller/dwc/pcie-designware.c | 20 +++++++------------
> drivers/pci/controller/dwc/pcie-designware.h | 1 -
> 3 files changed, 11 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index cf61733bf78d..9952057c8819 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -485,20 +485,15 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
> if (ret)
> goto err_remove_edma;
>
> - if (dw_pcie_link_up(pci)) {
> - dw_pcie_print_link_status(pci);
> - } else {
> + if (!dw_pcie_link_up(pci)) {
> ret = dw_pcie_start_link(pci);
> if (ret)
> goto err_remove_edma;
> -
> - if (pci->ops && pci->ops->start_link) {
> - ret = dw_pcie_wait_for_link(pci);
> - if (ret)
> - goto err_stop_link;
> - }
> }
>
> + /* Ignore errors, the link may come up later */
> + dw_pcie_wait_for_link(pci);
> +
> bridge->sysdata = pp;
>
> ret = pci_host_probe(bridge);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index df092229e97d..8e33e6e59e68 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -644,20 +644,9 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index)
> dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0);
> }
>
> -void dw_pcie_print_link_status(struct dw_pcie *pci)
> -{
> - u32 offset, val;
> -
> - offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> - val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
> -
> - dev_info(pci->dev, "PCIe Gen.%u x%u link up\n",
> - FIELD_GET(PCI_EXP_LNKSTA_CLS, val),
> - FIELD_GET(PCI_EXP_LNKSTA_NLW, val));
> -}
> -
> int dw_pcie_wait_for_link(struct dw_pcie *pci)
> {
> + u32 offset, val;
> int retries;
>
> /* Check if the link is up or not */
> @@ -673,7 +662,12 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci)
> return -ETIMEDOUT;
> }
>
> - dw_pcie_print_link_status(pci);
> + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> + val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
> +
> + dev_info(pci->dev, "PCIe Gen.%u x%u link up\n",
> + FIELD_GET(PCI_EXP_LNKSTA_CLS, val),
> + FIELD_GET(PCI_EXP_LNKSTA_NLW, val));
>
> return 0;
> }
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 615660640801..79713ce075cc 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -429,7 +429,6 @@ void dw_pcie_setup(struct dw_pcie *pci);
> void dw_pcie_iatu_detect(struct dw_pcie *pci);
> int dw_pcie_edma_detect(struct dw_pcie *pci);
> void dw_pcie_edma_remove(struct dw_pcie *pci);
> -void dw_pcie_print_link_status(struct dw_pcie *pci);
>
> static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
> {
> --
> 2.39.3
>

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