[PATCH 0/2] Misc RISC-V timer driver improvements

[PATCH 0/2] Misc RISC-V timer driver improvements

[Anup Patel]

This series does two improvements to the RISC-V timer driver:
1) Keep timer interrupt enable state in-sync with interrupt subsystem
2) Increase rating of clock event device when Sstc is available

These patches can also be found in the riscv_timer_imp_v1 branch at:
https://github.com/avpatel/linux.git

Anup Patel (2):
  clocksource: timer-riscv: Don't enable/disable timer interrupt
  clocksource: timer-riscv: Increase rating of clock_event_device for
    Sstc

 drivers/clocksource/timer-riscv.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH 1/2] clocksource: timer-riscv: Don't enable/disable timer interrupt

[Anup Patel]

Currently, we enable/disable timer interrupt at runtime to start/stop
timer events. This makes timer interrupt state go out-of-sync with
the Linux interrupt subsystem.

To address the above issue, we can stop a per-HART timer interrupt
by setting U64_MAX in timecmp CSR (or sbi_set_timer()) at the time
of handling timer interrupt.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 drivers/clocksource/timer-riscv.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index da3071b387eb..f2ea2b3d2d43 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -22,6 +22,7 @@
 #include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/interrupt.h>
 #include <linux/of_irq.h>
+#include <linux/limits.h>
 #include <clocksource/timer-riscv.h>
 #include <asm/smp.h>
 #include <asm/hwcap.h>
@@ -31,12 +32,22 @@
 static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
 static bool riscv_timer_cannot_wake_cpu;
 
+static void riscv_clock_event_stop(void)
+{
+	if (static_branch_likely(&riscv_sstc_available)) {
+		csr_write(CSR_STIMECMP, ULONG_MAX);
+		if (IS_ENABLED(CONFIG_32BIT))
+			csr_write(CSR_STIMECMPH, ULONG_MAX);
+	} else {
+		sbi_set_timer(U64_MAX);
+	}
+}
+
 static int riscv_clock_next_event(unsigned long delta,
 		struct clock_event_device *ce)
 {
 	u64 next_tval = get_cycles64() + delta;
 
-	csr_set(CSR_IE, IE_TIE);
 	if (static_branch_likely(&riscv_sstc_available)) {
 #if defined(CONFIG_32BIT)
 		csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
@@ -119,7 +130,7 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
 {
 	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
 
-	csr_clear(CSR_IE, IE_TIE);
+	riscv_clock_event_stop();
 	evdev->event_handler(evdev);
 
 	return IRQ_HANDLED;
-- 
2.34.1

[PATCH 2/2] clocksource: timer-riscv: Increase rating of clock_event_device for Sstc

[Anup Patel]

When Sstc is available the RISC-V timer clock_event_device should be
the preferred clock_event_device hence we increase clock_event_device
rating for Sstc.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 drivers/clocksource/timer-riscv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index f2ea2b3d2d43..9c8f3e2decc2 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -105,6 +105,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
 	ce->irq = riscv_clock_event_irq;
 	if (riscv_timer_cannot_wake_cpu)
 		ce->features |= CLOCK_EVT_FEAT_C3STOP;
+	if (static_branch_likely(&riscv_sstc_available))
+		ce->rating = 450;
 	clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
 
 	enable_percpu_irq(riscv_clock_event_irq,
-- 
2.34.1

Re: [PATCH 0/2] Misc RISC-V timer driver improvements

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 555 bytes --]

On Mon, Jul 10, 2023 at 06:49:00PM +0530, Anup Patel wrote:
> This series does two improvements to the RISC-V timer driver:
> 1) Keep timer interrupt enable state in-sync with interrupt subsystem
> 2) Increase rating of clock event device when Sstc is available
> 
> These patches can also be found in the riscv_timer_imp_v1 branch at:
> https://github.com/avpatel/linux.git

Other than wondering why you opted for 450 (curiosity really), this
stuff looks fine to me.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 0/2] Misc RISC-V timer driver improvements

[Anup Patel]

On Tue, Jul 11, 2023 at 4:51 PM Conor Dooley <conor.dooley@microchip.com> wrote:
>
> On Mon, Jul 10, 2023 at 06:49:00PM +0530, Anup Patel wrote:
> > This series does two improvements to the RISC-V timer driver:
> > 1) Keep timer interrupt enable state in-sync with interrupt subsystem
> > 2) Increase rating of clock event device when Sstc is available
> >
> > These patches can also be found in the riscv_timer_imp_v1 branch at:
> > https://github.com/avpatel/linux.git
>
> Other than wondering why you opted for 450 (curiosity really), this
> stuff looks fine to me.

It is the same as the rating for clock_event_device used by ARM arch timer.
(Refer, __arch_timer_setup() in drivers/clocksource/arm_arch_timer.c)

>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Cheers,
> Conor.

Regards,
Anup

Re: [PATCH 0/2] Misc RISC-V timer driver improvements

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 368 bytes --]

On Tue, Jul 11, 2023 at 05:07:11PM +0530, Anup Patel wrote:
> On Tue, Jul 11, 2023 at 4:51 PM Conor Dooley <conor.dooley@microchip.com> wrote:

> > Other than wondering why you opted for 450 (curiosity really), this
> > stuff looks fine to me.
> 
> It is the same as the rating for clock_event_device used by ARM arch timer.

That's what I figured, thanks!

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 0/2] Misc RISC-V timer driver improvements

[Palmer Dabbelt]

On Mon, 10 Jul 2023 06:19:00 PDT (-0700), apatel@ventanamicro.com wrote:
> This series does two improvements to the RISC-V timer driver:
> 1) Keep timer interrupt enable state in-sync with interrupt subsystem
> 2) Increase rating of clock event device when Sstc is available
>
> These patches can also be found in the riscv_timer_imp_v1 branch at:
> https://github.com/avpatel/linux.git
>
> Anup Patel (2):
>   clocksource: timer-riscv: Don't enable/disable timer interrupt
>   clocksource: timer-riscv: Increase rating of clock_event_device for
>     Sstc
>
>  drivers/clocksource/timer-riscv.c | 17 +++++++++++++++--
>  1 file changed, 15 insertions(+), 2 deletions(-)

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

in case the clock folks want to pick these up.  Otherwise I'll look more 
closely and take them via the RISC-V tree.  Thanks!