[PATCH 0/2] scsi: ufs: qcom: Add interconnect support

[PATCH 0/2] scsi: ufs: qcom: Add interconnect support

[Manivannan Sadhasivam]

Hi,

This series adds interconnect support to Qcom UFS driver. Interconnect support
is added to Qcom UFS driver for scaling the interconnect path dynamically. This
is required to avoid boot crash in recent SoCs and also to save power during
runtime. More information is available in patch 2/2.

Credits
=======

This series is a continuation of previous work by Brian Masney [1].

Testing
=======

This series is tested on 96Boards RB3 (SDM845 SoC) and RB5 (SM8250 SoC)
development boards.

NOTE: This series is a spin-off from previous OPP and interconnect series:
https://lore.kernel.org/all/20230720054100.9940-1-manivannan.sadhasivam@linaro.org/

Since the devicetree patches are already merged to Qcom tree, they are excluded
from this series.

Thanks,
Mani

[1] https://lore.kernel.org/all/20221117104957.254648-1-bmasney@redhat.com/

Manivannan Sadhasivam (2):
  scsi: ufs: core: Add enums for UFS lanes
  scsi: ufs: qcom: Add support for scaling interconnects

 drivers/ufs/core/ufshcd.c        |   4 +-
 drivers/ufs/host/ufs-qcom.c      | 131 ++++++++++++++++++++++++++++++-
 drivers/ufs/host/ufs-qcom.h      |   3 +
 drivers/ufs/host/ufshcd-pltfrm.c |   4 +-
 include/ufs/unipro.h             |   6 ++
 5 files changed, 143 insertions(+), 5 deletions(-)

-- 
2.25.1

[PATCH 1/2] scsi: ufs: core: Add enums for UFS lanes

[Manivannan Sadhasivam]

Since there are enums available for UFS gears, let's add enums for lanes
as well to maintain uniformity.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/ufs/core/ufshcd.c        | 4 ++--
 drivers/ufs/host/ufshcd-pltfrm.c | 4 ++--
 include/ufs/unipro.h             | 6 ++++++
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 90a7c817b7be..3839b58dc892 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -4375,8 +4375,8 @@ static void ufshcd_init_pwr_info(struct ufs_hba *hba)
 {
 	hba->pwr_info.gear_rx = UFS_PWM_G1;
 	hba->pwr_info.gear_tx = UFS_PWM_G1;
-	hba->pwr_info.lane_rx = 1;
-	hba->pwr_info.lane_tx = 1;
+	hba->pwr_info.lane_rx = UFS_LANE_1;
+	hba->pwr_info.lane_tx = UFS_LANE_1;
 	hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
 	hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
 	hba->pwr_info.hs_rate = 0;
diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
index 0b7430033047..7005046e8a69 100644
--- a/drivers/ufs/host/ufshcd-pltfrm.c
+++ b/drivers/ufs/host/ufshcd-pltfrm.c
@@ -305,8 +305,8 @@ EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
 void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
 {
 	*dev_param = (struct ufs_dev_params){
-		.tx_lanes = 2,
-		.rx_lanes = 2,
+		.tx_lanes = UFS_LANE_2,
+		.rx_lanes = UFS_LANE_2,
 		.hs_rx_gear = UFS_HS_G3,
 		.hs_tx_gear = UFS_HS_G3,
 		.pwm_rx_gear = UFS_PWM_G4,
diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h
index dc9dd1d23f0f..256eb3a43f54 100644
--- a/include/ufs/unipro.h
+++ b/include/ufs/unipro.h
@@ -230,6 +230,12 @@ enum ufs_hs_gear_tag {
 	UFS_HS_G5		/* HS Gear 5 */
 };
 
+enum ufs_lanes {
+	UFS_LANE_DONT_CHANGE,	/* Don't change Lane */
+	UFS_LANE_1,		/* Lane 1 (default for reset) */
+	UFS_LANE_2,		/* Lane 2 */
+};
+
 enum ufs_unipro_ver {
 	UFS_UNIPRO_VER_RESERVED = 0,
 	UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
-- 
2.25.1

[PATCH 2/2] scsi: ufs: qcom: Add support for scaling interconnects

[Manivannan Sadhasivam]

Qcom SoCs require scaling the interconnect paths for proper working of the
peripherals connected through interconnects. Even for accessing the UFS
controller, someone should setup the interconnect paths. So far, the
bootloaders used to setup the interconnect paths before booting linux as
they need to access the UFS storage for things like fetching boot firmware.
But with the advent of multi boot options, bootloader nowadays like in
SA8540p SoC do not setup the interconnect paths at all.

So trying to configure UFS in the absence of the interconnect path
configuration, results in boot crash.

To fix this issue and also to dynamically scale the interconnects (UFS-DDR
and CPU-UFS), interconnect API support is added to the Qcom UFS driver.
With this support, the interconnect paths are scaled dynamically based on
the gear configuration.

During the early stage of ufs_qcom_init(), ufs_qcom_icc_init() will setup
the paths to max bandwidth to allow configuring the UFS registers. Touching
the registers without configuring the icc paths would result in a crash.
However, we don't really need to set max vote for the icc paths as any
minimal vote would suffice. But the max value would allow initialization to
be done faster. After init, the bandwidth will get updated using
ufs_qcom_icc_update_bw() based on the gear and lane configuration.

The bandwidth values defined in ufs_qcom_bw_table struct are taken from
Qcom downstream vendor devicetree source and are calculated as per the
UFS3.1 Spec, Section 6.4.1, HS Gear Rates. So it is fixed across platforms.

Cc: Brian Masney <bmasney@redhat.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/ufs/host/ufs-qcom.c | 131 +++++++++++++++++++++++++++++++++++-
 drivers/ufs/host/ufs-qcom.h |   3 +
 2 files changed, 133 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 5728e94b6527..75a1fd295f34 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -7,6 +7,7 @@
 #include <linux/time.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/interconnect.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
@@ -46,6 +47,49 @@ enum {
 	TSTBUS_MAX,
 };
 
+#define QCOM_UFS_MAX_GEAR 4
+#define QCOM_UFS_MAX_LANE 2
+
+enum {
+	MODE_MIN,
+	MODE_PWM,
+	MODE_HS_RA,
+	MODE_HS_RB,
+	MODE_MAX,
+};
+
+struct __ufs_qcom_bw_table {
+	u32 mem_bw;
+	u32 cfg_bw;
+} ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = {
+	[MODE_MIN][0][0]		   = { 0,		0 }, /* Bandwidth values in KB/s */
+	[MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922,		1000 },
+	[MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844,		1000 },
+	[MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688,		1000 },
+	[MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376,		1000 },
+	[MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844,		1000 },
+	[MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688,		1000 },
+	[MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376,		1000 },
+	[MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752,		1000 },
+	[MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796,		1000 },
+	[MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591,		1000 },
+	[MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582,	102400 },
+	[MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200,	204800 },
+	[MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591,		1000 },
+	[MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181,		1000 },
+	[MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582,	204800 },
+	[MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200,	409600 },
+	[MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422,		1000 },
+	[MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189,		1000 },
+	[MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582,	102400 },
+	[MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200,	204800 },
+	[MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189,		1000 },
+	[MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378,		1000 },
+	[MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582,	204800 },
+	[MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200,	409600 },
+	[MODE_MAX][0][0]		    = { 7643136,	307200 },
+};
+
 static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS];
 
 static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host);
@@ -789,6 +833,51 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
 	}
 }
 
+static int ufs_qcom_icc_set_bw(struct ufs_qcom_host *host, u32 mem_bw, u32 cfg_bw)
+{
+	struct device *dev = host->hba->dev;
+	int ret;
+
+	ret = icc_set_bw(host->icc_ddr, 0, mem_bw);
+	if (ret < 0) {
+		dev_err(dev, "failed to set bandwidth request: %d\n", ret);
+		return ret;
+	}
+
+	ret = icc_set_bw(host->icc_cpu, 0, cfg_bw);
+	if (ret < 0) {
+		dev_err(dev, "failed to set bandwidth request: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static struct __ufs_qcom_bw_table ufs_qcom_get_bw_table(struct ufs_qcom_host *host)
+{
+	struct ufs_pa_layer_attr *p = &host->dev_req_params;
+	int gear = max_t(u32, p->gear_rx, p->gear_tx);
+	int lane = max_t(u32, p->lane_rx, p->lane_tx);
+
+	if (ufshcd_is_hs_mode(p)) {
+		if (p->hs_rate == PA_HS_MODE_B)
+			return ufs_qcom_bw_table[MODE_HS_RB][gear][lane];
+		else
+			return ufs_qcom_bw_table[MODE_HS_RA][gear][lane];
+	} else {
+		return ufs_qcom_bw_table[MODE_PWM][gear][lane];
+	}
+}
+
+static int ufs_qcom_icc_update_bw(struct ufs_qcom_host *host)
+{
+	struct __ufs_qcom_bw_table bw_table;
+
+	bw_table = ufs_qcom_get_bw_table(host);
+
+	return ufs_qcom_icc_set_bw(host, bw_table.mem_bw, bw_table.cfg_bw);
+}
+
 static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
 				enum ufs_notify_change_status status,
 				struct ufs_pa_layer_attr *dev_max_params,
@@ -852,6 +941,8 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
 		memcpy(&host->dev_req_params,
 				dev_req_params, sizeof(*dev_req_params));
 
+		ufs_qcom_icc_update_bw(host);
+
 		/* disable the device ref clock if entered PWM mode */
 		if (ufshcd_is_hs_mode(&hba->pwr_info) &&
 			!ufshcd_is_hs_mode(dev_req_params))
@@ -981,7 +1072,9 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
 
 	switch (status) {
 	case PRE_CHANGE:
-		if (!on) {
+		if (on) {
+			ufs_qcom_icc_update_bw(host);
+		} else {
 			if (!ufs_qcom_is_link_active(hba)) {
 				/* disable device ref_clk */
 				ufs_qcom_dev_ref_clk_ctrl(host, false);
@@ -993,6 +1086,9 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
 			/* enable the device ref clock for HS mode*/
 			if (ufshcd_is_hs_mode(&hba->pwr_info))
 				ufs_qcom_dev_ref_clk_ctrl(host, true);
+		} else {
+			ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MIN][0][0].mem_bw,
+					    ufs_qcom_bw_table[MODE_MIN][0][0].cfg_bw);
 		}
 		break;
 	}
@@ -1031,6 +1127,34 @@ static const struct reset_control_ops ufs_qcom_reset_ops = {
 	.deassert = ufs_qcom_reset_deassert,
 };
 
+static int ufs_qcom_icc_init(struct ufs_qcom_host *host)
+{
+	struct device *dev = host->hba->dev;
+	int ret;
+
+	host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr");
+	if (IS_ERR(host->icc_ddr))
+		return dev_err_probe(dev, PTR_ERR(host->icc_ddr),
+				    "failed to acquire interconnect path\n");
+
+	host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs");
+	if (IS_ERR(host->icc_cpu))
+		return dev_err_probe(dev, PTR_ERR(host->icc_cpu),
+				    "failed to acquire interconnect path\n");
+
+	/*
+	 * Set Maximum bandwidth vote before initializing the UFS controller and
+	 * device. Ideally, a minimal interconnect vote would suffice for the
+	 * initialization, but a max vote would allow faster initialization.
+	 */
+	ret = ufs_qcom_icc_set_bw(host, ufs_qcom_bw_table[MODE_MAX][0][0].mem_bw,
+				  ufs_qcom_bw_table[MODE_MAX][0][0].cfg_bw);
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "failed to set bandwidth request\n");
+
+	return 0;
+}
+
 /**
  * ufs_qcom_init - bind phy with controller
  * @hba: host controller instance
@@ -1085,6 +1209,10 @@ static int ufs_qcom_init(struct ufs_hba *hba)
 		}
 	}
 
+	err = ufs_qcom_icc_init(host);
+	if (err)
+		goto out_variant_clear;
+
 	host->device_reset = devm_gpiod_get_optional(dev, "reset",
 						     GPIOD_OUT_HIGH);
 	if (IS_ERR(host->device_reset)) {
@@ -1282,6 +1410,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
 				    dev_req_params->pwr_rx,
 				    dev_req_params->hs_rate,
 				    false);
+		ufs_qcom_icc_update_bw(host);
 		ufshcd_uic_hibern8_exit(hba);
 	}
 
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 729240367e70..d6f8e74bd538 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -206,6 +206,9 @@ struct ufs_qcom_host {
 	struct clk *tx_l1_sync_clk;
 	bool is_lane_clks_enabled;
 
+	struct icc_path *icc_ddr;
+	struct icc_path *icc_cpu;
+
 #ifdef CONFIG_SCSI_UFS_CRYPTO
 	struct qcom_ice *ice;
 #endif
-- 
2.25.1

Re: [PATCH 2/2] scsi: ufs: qcom: Add support for scaling interconnects

[Bart Van Assche]

On 7/31/23 07:50, Manivannan Sadhasivam wrote:
> +struct __ufs_qcom_bw_table {
> +	u32 mem_bw;
> +	u32 cfg_bw;
> +} ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = {
> +	[MODE_MIN][0][0]		   = { 0,		0 }, /* Bandwidth values in KB/s */
> +	[MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922,		1000 },
> +	[MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844,		1000 },
> +	[MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688,		1000 },
> +	[MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376,		1000 },
> +	[MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844,		1000 },
> +	[MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688,		1000 },
> +	[MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376,		1000 },
> +	[MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752,		1000 },
> +	[MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796,		1000 },
> +	[MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591,		1000 },
> +	[MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582,	102400 },
> +	[MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200,	204800 },
> +	[MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591,		1000 },
> +	[MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181,		1000 },
> +	[MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582,	204800 },
> +	[MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200,	409600 },
> +	[MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422,		1000 },
> +	[MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189,		1000 },
> +	[MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582,	102400 },
> +	[MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200,	204800 },
> +	[MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189,		1000 },
> +	[MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378,		1000 },
> +	[MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582,	204800 },
> +	[MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200,	409600 },
> +	[MODE_MAX][0][0]		    = { 7643136,	307200 },
> +};

Why has the above data structure not been declared as 'static const'?

Thanks,

Bart.

Re: [PATCH 2/2] scsi: ufs: qcom: Add support for scaling interconnects

[Manivannan Sadhasivam]

On Mon, Jul 31, 2023 at 01:09:52PM -0700, Bart Van Assche wrote:
> On 7/31/23 07:50, Manivannan Sadhasivam wrote:
> > +struct __ufs_qcom_bw_table {
> > +	u32 mem_bw;
> > +	u32 cfg_bw;
> > +} ufs_qcom_bw_table[MODE_MAX + 1][QCOM_UFS_MAX_GEAR + 1][QCOM_UFS_MAX_LANE + 1] = {
> > +	[MODE_MIN][0][0]		   = { 0,		0 }, /* Bandwidth values in KB/s */
> > +	[MODE_PWM][UFS_PWM_G1][UFS_LANE_1] = { 922,		1000 },
> > +	[MODE_PWM][UFS_PWM_G2][UFS_LANE_1] = { 1844,		1000 },
> > +	[MODE_PWM][UFS_PWM_G3][UFS_LANE_1] = { 3688,		1000 },
> > +	[MODE_PWM][UFS_PWM_G4][UFS_LANE_1] = { 7376,		1000 },
> > +	[MODE_PWM][UFS_PWM_G1][UFS_LANE_2] = { 1844,		1000 },
> > +	[MODE_PWM][UFS_PWM_G2][UFS_LANE_2] = { 3688,		1000 },
> > +	[MODE_PWM][UFS_PWM_G3][UFS_LANE_2] = { 7376,		1000 },
> > +	[MODE_PWM][UFS_PWM_G4][UFS_LANE_2] = { 14752,		1000 },
> > +	[MODE_HS_RA][UFS_HS_G1][UFS_LANE_1] = { 127796,		1000 },
> > +	[MODE_HS_RA][UFS_HS_G2][UFS_LANE_1] = { 255591,		1000 },
> > +	[MODE_HS_RA][UFS_HS_G3][UFS_LANE_1] = { 1492582,	102400 },
> > +	[MODE_HS_RA][UFS_HS_G4][UFS_LANE_1] = { 2915200,	204800 },
> > +	[MODE_HS_RA][UFS_HS_G1][UFS_LANE_2] = { 255591,		1000 },
> > +	[MODE_HS_RA][UFS_HS_G2][UFS_LANE_2] = { 511181,		1000 },
> > +	[MODE_HS_RA][UFS_HS_G3][UFS_LANE_2] = { 1492582,	204800 },
> > +	[MODE_HS_RA][UFS_HS_G4][UFS_LANE_2] = { 2915200,	409600 },
> > +	[MODE_HS_RB][UFS_HS_G1][UFS_LANE_1] = { 149422,		1000 },
> > +	[MODE_HS_RB][UFS_HS_G2][UFS_LANE_1] = { 298189,		1000 },
> > +	[MODE_HS_RB][UFS_HS_G3][UFS_LANE_1] = { 1492582,	102400 },
> > +	[MODE_HS_RB][UFS_HS_G4][UFS_LANE_1] = { 2915200,	204800 },
> > +	[MODE_HS_RB][UFS_HS_G1][UFS_LANE_2] = { 298189,		1000 },
> > +	[MODE_HS_RB][UFS_HS_G2][UFS_LANE_2] = { 596378,		1000 },
> > +	[MODE_HS_RB][UFS_HS_G3][UFS_LANE_2] = { 1492582,	204800 },
> > +	[MODE_HS_RB][UFS_HS_G4][UFS_LANE_2] = { 2915200,	409600 },
> > +	[MODE_MAX][0][0]		    = { 7643136,	307200 },
> > +};
> 
> Why has the above data structure not been declared as 'static const'?
> 

Missed that! Sent a patch now. Thanks for spotting.

- Mani

> Thanks,
> 
> Bart.

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH 0/2] scsi: ufs: qcom: Add interconnect support

[Martin K. Petersen]

Manivannan,

> This series adds interconnect support to Qcom UFS driver. Interconnect
> support is added to Qcom UFS driver for scaling the interconnect path
> dynamically. This is required to avoid boot crash in recent SoCs and
> also to save power during runtime. More information is available in
> patch 2/2.

Applied to 6.6/scsi-staging, thanks!

-- 
Martin K. Petersen	Oracle Linux Engineering

Re: [PATCH 0/2] scsi: ufs: qcom: Add interconnect support

[Martin K. Petersen]

On Mon, 31 Jul 2023 20:20:18 +0530, Manivannan Sadhasivam wrote:

> This series adds interconnect support to Qcom UFS driver. Interconnect support
> is added to Qcom UFS driver for scaling the interconnect path dynamically. This
> is required to avoid boot crash in recent SoCs and also to save power during
> runtime. More information is available in patch 2/2.
> 
> Credits
> =======
> 
> [...]

Applied to 6.6/scsi-queue, thanks!

[1/2] scsi: ufs: core: Add enums for UFS lanes
      https://git.kernel.org/mkp/scsi/c/e0d01da2cb0f
[2/2] scsi: ufs: qcom: Add support for scaling interconnects
      https://git.kernel.org/mkp/scsi/c/03ce80a1bb86

-- 
Martin K. Petersen	Oracle Linux Engineering