Re: [PATCH v7 2/2] PCI: Don't put non-power manageable PCIe root ports into D3

[Mika Westerberg <mika.westerberg@linux.intel.com>]

Hi Mario,

On Tue, Aug 01, 2023 at 10:17:11PM -0500, Mario Limonciello wrote:
> > Consequently, platform_pci_bridge_d3() will return false and the only
> > thing that may allow the port to go into D0 is the dmi_get_bios_year()
> > check at the end of pci_bridge_d3_possible().
> > 
> > However, that was added, because there are Intel platforms on which
> > Root Ports need to be programmed into D3hot on suspend (which allows
> > the whole platform to reduce power significantly) and there are no
> > ACPI device power management objects associated with them (Mika should
> > know the gory details related to this).  It looks like under Windows
> > the additional power reduction would not be possible on those systems,
> > but that would be a problem, wouldn't it?
> > 
> 
> I've been thinking on this today, and I at least have a hypothesis about
> this behavior.  Perhaps Windows is actually utilizing enabled PEP
> constraints to enforce what state device should be put into over Modern
> Standby cycles in the absence of ACPI objects.
> 
> In the case of one of my problematic system the PEP constraints for the root
> port are:
> 
> Package (0x04)
> {
> 	0x00,
> 	"\\_SB.PCI0.GP17",
> 	0x00,
> 	0x00
> },
> 
> That first 0x00 means the constraint isn't actually enabled for the root
> port.
> 
> Mika,
> 
> Could you get an acpidump from one of these problematic Intel systems so we
> can check the PEP constraints to see if this theory works? Or maybe you have
> some other ideas why this is different?

The patch adding this was merged in 2016 and unfortunately I don't have
any of the ACPI dumps from them available anymore (and do not recall the
details either). I think these were Apollo Lake-P based systems with the
initial runtime D3cold and S0ix support at the time.