From: Liam Beguin <liambeguin@gmail.com>
To: Mike Looijmans <mike.looijmans@topic.nl>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
sboyd@kernel.org, mturquette@baylibre.com
Subject: Re: [PATCH 3/3] clk: lmk04832: Support using PLL1_LD as SPI readback pin
Date: Wed, 23 Aug 2023 15:15:06 -0400 [thread overview]
Message-ID: <20230823191506.GC2572839@shaak> (raw)
In-Reply-To: <20230802064100.15793-3-mike.looijmans@topic.nl>
On Wed, Aug 02, 2023 at 08:41:00AM +0200, Mike Looijmans wrote:
> The PLL1_PD pin (a.k.a. STATUS_LD1) can be used as SPI readback pin. Make
> this possible.
>
> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Reviewed-by: Liam Beguin <liambeguin@gmail.com>
> ---
> drivers/clk/clk-lmk04832.c | 23 ++++++++++++++++++-----
> 1 file changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/clk-lmk04832.c b/drivers/clk/clk-lmk04832.c
> index dd1f0c59ee71..99b271c1278a 100644
> --- a/drivers/clk/clk-lmk04832.c
> +++ b/drivers/clk/clk-lmk04832.c
> @@ -134,6 +134,11 @@
> /* 0x14b - 0x152 Holdover */
>
> /* 0x153 - 0x15f PLL1 Configuration */
> +#define LMK04832_REG_PLL1_LD 0x15f
> +#define LMK04832_BIT_PLL1_LD_MUX GENMASK(7, 3)
> +#define LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK 0x07
> +#define LMK04832_BIT_PLL1_LD_TYPE GENMASK(2, 0)
> +#define LMK04832_VAL_PLL1_LD_TYPE_OUT_PP 0x03
>
> /* 0x160 - 0x16e PLL2 Configuration */
> #define LMK04832_REG_PLL2_R_MSB 0x160
> @@ -206,6 +211,7 @@ enum lmk04832_rdbk_type {
> RDBK_CLKIN_SEL0,
> RDBK_CLKIN_SEL1,
> RDBK_RESET,
> + RDBK_PLL1_LD,
> };
>
> struct lmk_dclk {
> @@ -1346,6 +1352,10 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
> {
> int reg;
> int ret;
> + int val = FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
> + LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
> + FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
> + LMK04832_VAL_CLKIN_SEL_TYPE_OUT);
>
> dev_info(lmk->dev, "setting up 4-wire mode\n");
> ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W,
> @@ -1363,15 +1373,18 @@ static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
> case RDBK_RESET:
> reg = LMK04832_REG_CLKIN_RST;
> break;
> + case RDBK_PLL1_LD:
> + reg = LMK04832_REG_PLL1_LD;
> + val = FIELD_PREP(LMK04832_BIT_PLL1_LD_MUX,
> + LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK) |
> + FIELD_PREP(LMK04832_BIT_PLL1_LD_TYPE,
> + LMK04832_VAL_PLL1_LD_TYPE_OUT_PP);
> + break;
> default:
> return -EINVAL;
> }
>
> - return regmap_write(lmk->regmap, reg,
> - FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
> - LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
> - FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
> - LMK04832_VAL_CLKIN_SEL_TYPE_OUT));
> + return regmap_write(lmk->regmap, reg, val);
> }
>
> static int lmk04832_probe(struct spi_device *spi)
> --
> 2.17.1
>
>
> Met vriendelijke groet / kind regards,
>
> Mike Looijmans
> System Expert
>
>
> TOPIC Embedded Products B.V.
> Materiaalweg 4, 5681 RJ Best
> The Netherlands
>
> T: +31 (0) 499 33 69 69
> E: mike.looijmans@topicproducts.com
> W: www.topic.nl
>
> Please consider the environment before printing this e-mail
next prev parent reply other threads:[~2023-08-23 19:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1b153bce-a66a-45ee-a5c6-963ea6fb1c82.949ef384-8293-46b8-903f-40a477c056ae.05b2cfbe-0414-4869-b825-034b9be5bf9a@emailsignatures365.codetwo.com>
2023-08-02 6:40 ` [PATCH 1/3] clk: lmk04832: Set missing parent_names for output clocks Mike Looijmans
2023-08-02 6:40 ` [PATCH 2/3] clk: lmk04832: Don't disable vco clock on probe fail Mike Looijmans
2023-08-23 19:14 ` Liam Beguin
2023-08-23 22:48 ` Stephen Boyd
2023-08-02 6:41 ` [PATCH 3/3] clk: lmk04832: Support using PLL1_LD as SPI readback pin Mike Looijmans
2023-08-23 19:15 ` Liam Beguin [this message]
2023-08-23 22:48 ` Stephen Boyd
2023-08-23 19:13 ` [PATCH 1/3] clk: lmk04832: Set missing parent_names for output clocks Liam Beguin
2023-08-23 22:48 ` Stephen Boyd
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