From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A752C83F14 for ; Tue, 29 Aug 2023 07:51:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233908AbjH2Huk (ORCPT ); Tue, 29 Aug 2023 03:50:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233878AbjH2HuH (ORCPT ); Tue, 29 Aug 2023 03:50:07 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1E4419F for ; Tue, 29 Aug 2023 00:50:02 -0700 (PDT) Received: from ptx.hi.pengutronix.de ([2001:67c:670:100:1d::c0]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1qatU2-0000LO-Fo; Tue, 29 Aug 2023 09:49:54 +0200 Received: from mtr by ptx.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1qatU0-0003hv-5P; Tue, 29 Aug 2023 09:49:52 +0200 Date: Tue, 29 Aug 2023 09:49:52 +0200 From: Michael Tretter To: Adam Ford Cc: Marco Felsch , Neil Armstrong , Robert Foss , Jonas Karlman , dri-devel@lists.freedesktop.org, Laurent Pinchart , linux-kernel@vger.kernel.org, Jernej Skrabec , Jagan Teki , Andrzej Hajda , kernel@pengutronix.de, Marek Szyprowski Subject: Re: [PATCH 3/5] drm/bridge: samsung-dsim: update PLL reference clock Message-ID: <20230829074952.GF17387@pengutronix.de> References: <20230818-samsung-dsim-v1-0-b39716db6b7a@pengutronix.de> <20230818-samsung-dsim-v1-3-b39716db6b7a@pengutronix.de> <20230828164148.tm23yudt76eqefzh@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Sent-From: Pengutronix Hildesheim X-URL: http://www.pengutronix.de/ X-Accept-Language: de,en X-Accept-Content-Type: text/plain User-Agent: Mutt/1.10.1 (2018-07-13) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: mtr@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 28 Aug 2023 13:17:44 -0500, Adam Ford wrote: > On Mon, Aug 28, 2023 at 11:42 AM Marco Felsch wrote: > > > > On 23-08-28, Michael Tretter wrote: > > > The PLL requires a clock between 2 MHz and 30 MHz after the pre-divider. > > > The reference clock for the PLL may change due to changes to it's parent > > > clock. Thus, the frequency may be out of range or unsuited for > > > generating the high speed clock for MIPI DSI. > > > > > > Try to keep the pre-devider small, and set the reference clock close to > > > 30 MHz before recalculating the PLL configuration. Use a divider with a > > > power of two for the reference clock as this seems to work best in > > > my tests. > > > > > > Signed-off-by: Michael Tretter > > > --- > > > drivers/gpu/drm/bridge/samsung-dsim.c | 15 +++++++++++++-- > > > 1 file changed, 13 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c > > > index da90c2038042..4de6e4f116db 100644 > > > --- a/drivers/gpu/drm/bridge/samsung-dsim.c > > > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c > > > @@ -611,10 +611,21 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, > > > u16 m; > > > u32 reg; > > > > > > - if (dsi->pll_clk) > > > + if (dsi->pll_clk) { > > > + /* > > > + * Ensure that the reference clock is generated with a power of > > > + * two divider from its parent, but close to the PLLs upper > > > + * limit of the valid range of 2 MHz to 30 MHz. > > > + */ > > > + fin = clk_get_rate(clk_get_parent(dsi->pll_clk)); > > > + while (fin > 30 * MHZ) > > > + fin = fin / 2; > > > > Really just a cosmetic nit: fin /= 2; > > > > Reviewed-by: Marco Felsch > > > > > + clk_set_rate(dsi->pll_clk, fin); > > > + > > > fin = clk_get_rate(dsi->pll_clk); > > > - else > > > + } else { > > > fin = dsi->pll_clk_rate; > > > + } > > I don't have all the code style rules memorized. Did you run it > through checkpatch? I wonder if the braces here are appropriate for a > 1-line after the else. If checkpatch is happy, I am fine with it. checkpatch is happy: The coding style states that if one of the branches needs braces because it has multiple statements, all branches should have braces. Michael > > adam > > > dev_dbg(dsi->dev, "PLL ref clock freq %lu\n", fin); > > > > > > fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s); > > > > > > -- > > > 2.39.2 > > > > > > > > > >